2 * Contains CPU feature definitions
4 * Copyright (C) 2015 ARM Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #define pr_fmt(fmt) "CPU features: " fmt
21 #include <linux/bsearch.h>
22 #include <linux/cpumask.h>
23 #include <linux/sort.h>
24 #include <linux/stop_machine.h>
25 #include <linux/types.h>
28 #include <asm/cpufeature.h>
29 #include <asm/cpu_ops.h>
30 #include <asm/fpsimd.h>
31 #include <asm/mmu_context.h>
32 #include <asm/processor.h>
33 #include <asm/sysreg.h>
34 #include <asm/traps.h>
37 unsigned long elf_hwcap __read_mostly;
38 EXPORT_SYMBOL_GPL(elf_hwcap);
41 #define COMPAT_ELF_HWCAP_DEFAULT \
42 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
43 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
44 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
45 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
46 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
48 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
49 unsigned int compat_elf_hwcap2 __read_mostly;
52 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
53 EXPORT_SYMBOL(cpu_hwcaps);
56 * Flag to indicate if we have computed the system wide
57 * capabilities based on the boot time active CPUs. This
58 * will be used to determine if a new booting CPU should
59 * go through the verification process to make sure that it
60 * supports the system capabilities, without using a hotplug
63 static bool sys_caps_initialised;
65 static inline void set_sys_caps_initialised(void)
67 sys_caps_initialised = true;
70 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
72 /* file-wide pr_fmt adds "CPU features: " prefix */
73 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
77 static struct notifier_block cpu_hwcaps_notifier = {
78 .notifier_call = dump_cpu_hwcaps
81 static int __init register_cpu_hwcaps_dumper(void)
83 atomic_notifier_chain_register(&panic_notifier_list,
84 &cpu_hwcaps_notifier);
87 __initcall(register_cpu_hwcaps_dumper);
89 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
90 EXPORT_SYMBOL(cpu_hwcap_keys);
92 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
100 .safe_val = SAFE_VAL, \
103 /* Define a feature with unsigned values */
104 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
105 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
107 /* Define a feature with a signed value */
108 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
109 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
111 #define ARM64_FTR_END \
116 /* meta feature for alternatives */
117 static bool __maybe_unused
118 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
122 * NOTE: Any changes to the visibility of features should be kept in
123 * sync with the documentation of the CPU feature register ABI.
125 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
126 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
127 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
128 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
129 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
130 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
131 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
132 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
133 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
134 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
135 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
136 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
137 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
141 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
142 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
143 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
144 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
145 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
149 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
150 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
151 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
152 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
153 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
154 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
155 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
156 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
157 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
158 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
159 /* Linux doesn't care about the EL3 */
160 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
161 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
162 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
163 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
167 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
168 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
169 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
170 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
171 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
172 /* Linux shouldn't care about secure memory */
173 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
174 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
175 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
177 * Differing PARange is fine as long as all peripherals and memory are mapped
178 * within the minimum PARange of all CPUs
180 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
184 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
185 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
186 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
187 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
188 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
189 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
190 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
194 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
195 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
198 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
199 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
200 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
201 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
205 static const struct arm64_ftr_bits ftr_ctr[] = {
206 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
207 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
208 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
209 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_CWG_SHIFT, 4, 0),
210 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_ERG_SHIFT, 4, 0),
211 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
213 * Linux can handle differing I-cache policies. Userspace JITs will
214 * make use of *minLine.
215 * If we have differing I-cache policies, report it as the weakest - VIPT.
217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */
218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */
222 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
223 .name = "SYS_CTR_EL0",
227 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
228 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */
229 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */
230 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
231 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */
232 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */
233 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */
234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */
235 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */
239 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
240 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
243 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
244 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
246 * We can instantiate multiple PMU instances with different levels
249 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
255 static const struct arm64_ftr_bits ftr_mvfr2[] = {
256 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */
257 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */
261 static const struct arm64_ftr_bits ftr_dczid[] = {
262 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
263 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
268 static const struct arm64_ftr_bits ftr_id_isar5[] = {
269 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
270 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
271 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
272 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
273 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
274 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
278 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */
283 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
284 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */
285 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */
286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */
287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */
291 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
293 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
297 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
299 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
303 static const struct arm64_ftr_bits ftr_zcr[] = {
304 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
305 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
310 * Common ftr bits for a 32bit register with all hidden, strict
311 * attributes, with 4bit feature fields and a default safe value of
312 * 0. Covers the following 32bit registers:
313 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
315 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
317 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
318 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
319 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
327 /* Table for a single 32bit feature value */
328 static const struct arm64_ftr_bits ftr_single32[] = {
329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
333 static const struct arm64_ftr_bits ftr_raz[] = {
337 #define ARM64_FTR_REG(id, table) { \
339 .reg = &(struct arm64_ftr_reg){ \
341 .ftr_bits = &((table)[0]), \
344 static const struct __ftr_reg_entry {
346 struct arm64_ftr_reg *reg;
347 } arm64_ftr_regs[] = {
349 /* Op1 = 0, CRn = 0, CRm = 1 */
350 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
351 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
352 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
353 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
354 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
355 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
356 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
358 /* Op1 = 0, CRn = 0, CRm = 2 */
359 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
360 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
361 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
362 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
363 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
364 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
365 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
367 /* Op1 = 0, CRn = 0, CRm = 3 */
368 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
369 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
370 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
372 /* Op1 = 0, CRn = 0, CRm = 4 */
373 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
374 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_raz),
375 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz),
377 /* Op1 = 0, CRn = 0, CRm = 5 */
378 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
379 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
381 /* Op1 = 0, CRn = 0, CRm = 6 */
382 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
383 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
385 /* Op1 = 0, CRn = 0, CRm = 7 */
386 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
387 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
388 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
390 /* Op1 = 0, CRn = 1, CRm = 2 */
391 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
393 /* Op1 = 3, CRn = 0, CRm = 0 */
394 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
395 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
397 /* Op1 = 3, CRn = 14, CRm = 0 */
398 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
401 static int search_cmp_ftr_reg(const void *id, const void *regp)
403 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
407 * get_arm64_ftr_reg - Lookup a feature register entry using its
408 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
409 * ascending order of sys_id , we use binary search to find a matching
412 * returns - Upon success, matching ftr_reg entry for id.
413 * - NULL on failure. It is upto the caller to decide
414 * the impact of a failure.
416 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
418 const struct __ftr_reg_entry *ret;
420 ret = bsearch((const void *)(unsigned long)sys_id,
422 ARRAY_SIZE(arm64_ftr_regs),
423 sizeof(arm64_ftr_regs[0]),
430 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
433 u64 mask = arm64_ftr_mask(ftrp);
436 reg |= (ftr_val << ftrp->shift) & mask;
440 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
445 switch (ftrp->type) {
447 ret = ftrp->safe_val;
450 ret = new < cur ? new : cur;
452 case FTR_HIGHER_SAFE:
453 ret = new > cur ? new : cur;
462 static void __init sort_ftr_regs(void)
466 /* Check that the array is sorted so that we can do the binary search */
467 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
468 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
472 * Initialise the CPU feature register from Boot CPU values.
473 * Also initiliases the strict_mask for the register.
474 * Any bits that are not covered by an arm64_ftr_bits entry are considered
475 * RES0 for the system-wide value, and must strictly match.
477 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
480 u64 strict_mask = ~0x0ULL;
484 const struct arm64_ftr_bits *ftrp;
485 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
489 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
490 u64 ftr_mask = arm64_ftr_mask(ftrp);
491 s64 ftr_new = arm64_ftr_value(ftrp, new);
493 val = arm64_ftr_set_value(ftrp, val, ftr_new);
495 valid_mask |= ftr_mask;
497 strict_mask &= ~ftr_mask;
499 user_mask |= ftr_mask;
501 reg->user_val = arm64_ftr_set_value(ftrp,
509 reg->strict_mask = strict_mask;
510 reg->user_mask = user_mask;
513 extern const struct arm64_cpu_capabilities arm64_errata[];
514 static void __init setup_boot_cpu_capabilities(void);
516 void __init init_cpu_features(struct cpuinfo_arm64 *info)
518 /* Before we start using the tables, make sure it is sorted */
521 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
522 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
523 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
524 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
525 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
526 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
527 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
528 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
529 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
530 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
531 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
532 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
533 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
535 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
536 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
537 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
538 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
539 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
540 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
541 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
542 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
543 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
544 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
545 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
546 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
547 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
548 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
549 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
550 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
551 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
554 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
555 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
560 * Detect and enable early CPU capabilities based on the boot CPU,
561 * after we have initialised the CPU feature infrastructure.
563 setup_boot_cpu_capabilities();
566 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
568 const struct arm64_ftr_bits *ftrp;
570 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
571 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
572 s64 ftr_new = arm64_ftr_value(ftrp, new);
574 if (ftr_cur == ftr_new)
576 /* Find a safe value */
577 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
578 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
583 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
585 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
588 update_cpu_ftr_reg(regp, val);
589 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
591 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
592 regp->name, boot, cpu, val);
597 * Update system wide CPU feature registers with the values from a
598 * non-boot CPU. Also performs SANITY checks to make sure that there
599 * aren't any insane variations from that of the boot CPU.
601 void update_cpu_features(int cpu,
602 struct cpuinfo_arm64 *info,
603 struct cpuinfo_arm64 *boot)
608 * The kernel can handle differing I-cache policies, but otherwise
609 * caches should look identical. Userspace JITs will make use of
612 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
613 info->reg_ctr, boot->reg_ctr);
616 * Userspace may perform DC ZVA instructions. Mismatched block sizes
617 * could result in too much or too little memory being zeroed if a
618 * process is preempted and migrated between CPUs.
620 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
621 info->reg_dczid, boot->reg_dczid);
623 /* If different, timekeeping will be broken (especially with KVM) */
624 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
625 info->reg_cntfrq, boot->reg_cntfrq);
628 * The kernel uses self-hosted debug features and expects CPUs to
629 * support identical debug features. We presently need CTX_CMPs, WRPs,
630 * and BRPs to be identical.
631 * ID_AA64DFR1 is currently RES0.
633 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
634 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
635 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
636 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
638 * Even in big.LITTLE, processors should be identical instruction-set
641 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
642 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
643 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
644 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
647 * Differing PARange support is fine as long as all peripherals and
648 * memory are mapped within the minimum PARange of all CPUs.
649 * Linux should not care about secure memory.
651 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
652 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
653 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
654 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
655 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
656 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
659 * EL3 is not our concern.
660 * ID_AA64PFR1 is currently RES0.
662 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
663 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
664 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
665 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
667 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
668 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
671 * If we have AArch32, we care about 32-bit features for compat.
672 * If the system doesn't support AArch32, don't update them.
674 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
675 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
677 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
678 info->reg_id_dfr0, boot->reg_id_dfr0);
679 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
680 info->reg_id_isar0, boot->reg_id_isar0);
681 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
682 info->reg_id_isar1, boot->reg_id_isar1);
683 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
684 info->reg_id_isar2, boot->reg_id_isar2);
685 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
686 info->reg_id_isar3, boot->reg_id_isar3);
687 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
688 info->reg_id_isar4, boot->reg_id_isar4);
689 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
690 info->reg_id_isar5, boot->reg_id_isar5);
693 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
694 * ACTLR formats could differ across CPUs and therefore would have to
695 * be trapped for virtualization anyway.
697 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
698 info->reg_id_mmfr0, boot->reg_id_mmfr0);
699 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
700 info->reg_id_mmfr1, boot->reg_id_mmfr1);
701 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
702 info->reg_id_mmfr2, boot->reg_id_mmfr2);
703 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
704 info->reg_id_mmfr3, boot->reg_id_mmfr3);
705 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
706 info->reg_id_pfr0, boot->reg_id_pfr0);
707 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
708 info->reg_id_pfr1, boot->reg_id_pfr1);
709 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
710 info->reg_mvfr0, boot->reg_mvfr0);
711 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
712 info->reg_mvfr1, boot->reg_mvfr1);
713 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
714 info->reg_mvfr2, boot->reg_mvfr2);
717 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
718 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
719 info->reg_zcr, boot->reg_zcr);
721 /* Probe vector lengths, unless we already gave up on SVE */
722 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
723 !sys_caps_initialised)
728 * Mismatched CPU features are a recipe for disaster. Don't even
729 * pretend to support them.
732 pr_warn_once("Unsupported CPU feature variation detected.\n");
733 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
737 u64 read_sanitised_ftr_reg(u32 id)
739 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
741 /* We shouldn't get a request for an unsupported register */
743 return regp->sys_val;
746 #define read_sysreg_case(r) \
747 case r: return read_sysreg_s(r)
750 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
751 * Read the system register on the current CPU
753 static u64 __read_sysreg_by_encoding(u32 sys_id)
756 read_sysreg_case(SYS_ID_PFR0_EL1);
757 read_sysreg_case(SYS_ID_PFR1_EL1);
758 read_sysreg_case(SYS_ID_DFR0_EL1);
759 read_sysreg_case(SYS_ID_MMFR0_EL1);
760 read_sysreg_case(SYS_ID_MMFR1_EL1);
761 read_sysreg_case(SYS_ID_MMFR2_EL1);
762 read_sysreg_case(SYS_ID_MMFR3_EL1);
763 read_sysreg_case(SYS_ID_ISAR0_EL1);
764 read_sysreg_case(SYS_ID_ISAR1_EL1);
765 read_sysreg_case(SYS_ID_ISAR2_EL1);
766 read_sysreg_case(SYS_ID_ISAR3_EL1);
767 read_sysreg_case(SYS_ID_ISAR4_EL1);
768 read_sysreg_case(SYS_ID_ISAR5_EL1);
769 read_sysreg_case(SYS_MVFR0_EL1);
770 read_sysreg_case(SYS_MVFR1_EL1);
771 read_sysreg_case(SYS_MVFR2_EL1);
773 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
774 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
775 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
776 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
777 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
778 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
779 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
780 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
781 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
783 read_sysreg_case(SYS_CNTFRQ_EL0);
784 read_sysreg_case(SYS_CTR_EL0);
785 read_sysreg_case(SYS_DCZID_EL0);
793 #include <linux/irqchip/arm-gic-v3.h>
796 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
798 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
800 return val >= entry->min_field_value;
804 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
808 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
809 if (scope == SCOPE_SYSTEM)
810 val = read_sanitised_ftr_reg(entry->sys_reg);
812 val = __read_sysreg_by_encoding(entry->sys_reg);
814 return feature_matches(val, entry);
817 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
821 if (!has_cpuid_feature(entry, scope))
824 has_sre = gic_enable_sre();
826 pr_warn_once("%s present but disabled by higher exception level\n",
832 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
834 u32 midr = read_cpuid_id();
836 /* Cavium ThunderX pass 1.x and 2.x */
837 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
838 MIDR_CPU_VAR_REV(0, 0),
839 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
842 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
844 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
846 return cpuid_feature_extract_signed_field(pfr0,
847 ID_AA64PFR0_FP_SHIFT) < 0;
850 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
853 return read_sanitised_ftr_reg(SYS_CTR_EL0) & BIT(CTR_IDC_SHIFT);
856 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
859 return read_sanitised_ftr_reg(SYS_CTR_EL0) & BIT(CTR_DIC_SHIFT);
862 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
863 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
865 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
868 /* List of CPUs that are not vulnerable and don't need KPTI */
869 static const struct midr_range kpti_safe_list[] = {
870 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
871 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
874 char const *str = "command line option";
877 * For reasons that aren't entirely clear, enabling KPTI on Cavium
878 * ThunderX leads to apparent I-cache corruption of kernel text, which
879 * ends as well as you might imagine. Don't even try.
881 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
882 str = "ARM64_WORKAROUND_CAVIUM_27456";
888 pr_info_once("kernel page table isolation forced %s by %s\n",
889 __kpti_forced > 0 ? "ON" : "OFF", str);
890 return __kpti_forced > 0;
893 /* Useful for KASLR robustness */
894 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE))
897 /* Don't force KPTI for CPUs that are not vulnerable */
898 if (is_midr_in_range_list(read_cpuid_id(), kpti_safe_list))
901 /* Defer to CPU feature registers */
902 return !has_cpuid_feature(entry, scope);
906 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
908 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
909 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
910 kpti_remap_fn *remap_fn;
912 static bool kpti_applied = false;
913 int cpu = smp_processor_id();
918 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
921 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
922 cpu_uninstall_idmap();
930 static int __init parse_kpti(char *str)
933 int ret = strtobool(str, &enabled);
938 __kpti_forced = enabled ? 1 : -1;
941 early_param("kpti", parse_kpti);
942 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
944 #ifdef CONFIG_ARM64_HW_AFDBM
945 static inline void __cpu_enable_hw_dbm(void)
947 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
949 write_sysreg(tcr, tcr_el1);
953 static bool cpu_has_broken_dbm(void)
955 /* List of CPUs which have broken DBM support. */
956 static const struct midr_range cpus[] = {
957 #ifdef CONFIG_ARM64_ERRATUM_1024718
958 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
963 return is_midr_in_range_list(read_cpuid_id(), cpus);
966 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
968 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
969 !cpu_has_broken_dbm();
972 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
974 if (cpu_can_use_dbm(cap))
975 __cpu_enable_hw_dbm();
978 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
981 static bool detected = false;
983 * DBM is a non-conflicting feature. i.e, the kernel can safely
984 * run a mix of CPUs with and without the feature. So, we
985 * unconditionally enable the capability to allow any late CPU
986 * to use the feature. We only enable the control bits on the
987 * CPU, if it actually supports.
989 * We have to make sure we print the "feature" detection only
990 * when at least one CPU actually uses it. So check if this CPU
991 * can actually use it and print the message exactly once.
993 * This is safe as all CPUs (including secondary CPUs - due to the
994 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
995 * goes through the "matches" check exactly once. Also if a CPU
996 * matches the criteria, it is guaranteed that the CPU will turn
997 * the DBM on, as the capability is unconditionally enabled.
999 if (!detected && cpu_can_use_dbm(cap)) {
1001 pr_info("detected: Hardware dirty bit management\n");
1009 #ifdef CONFIG_ARM64_VHE
1010 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1012 return is_kernel_in_hyp_mode();
1015 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1018 * Copy register values that aren't redirected by hardware.
1020 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1021 * this value to tpidr_el2 before we patch the code. Once we've done
1022 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1025 if (!alternatives_applied)
1026 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1030 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1032 u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1034 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1035 WARN_ON(val & (7 << 27 | 7 << 21));
1038 static const struct arm64_cpu_capabilities arm64_features[] = {
1040 .desc = "GIC system register CPU interface",
1041 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1042 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1043 .matches = has_useable_gicv3_cpuif,
1044 .sys_reg = SYS_ID_AA64PFR0_EL1,
1045 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1046 .sign = FTR_UNSIGNED,
1047 .min_field_value = 1,
1049 #ifdef CONFIG_ARM64_PAN
1051 .desc = "Privileged Access Never",
1052 .capability = ARM64_HAS_PAN,
1053 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1054 .matches = has_cpuid_feature,
1055 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1056 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1057 .sign = FTR_UNSIGNED,
1058 .min_field_value = 1,
1059 .cpu_enable = cpu_enable_pan,
1061 #endif /* CONFIG_ARM64_PAN */
1062 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1064 .desc = "LSE atomic instructions",
1065 .capability = ARM64_HAS_LSE_ATOMICS,
1066 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1067 .matches = has_cpuid_feature,
1068 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1069 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1070 .sign = FTR_UNSIGNED,
1071 .min_field_value = 2,
1073 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
1075 .desc = "Software prefetching using PRFM",
1076 .capability = ARM64_HAS_NO_HW_PREFETCH,
1077 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1078 .matches = has_no_hw_prefetch,
1080 #ifdef CONFIG_ARM64_UAO
1082 .desc = "User Access Override",
1083 .capability = ARM64_HAS_UAO,
1084 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1085 .matches = has_cpuid_feature,
1086 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1087 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1088 .min_field_value = 1,
1090 * We rely on stop_machine() calling uao_thread_switch() to set
1091 * UAO immediately after patching.
1094 #endif /* CONFIG_ARM64_UAO */
1095 #ifdef CONFIG_ARM64_PAN
1097 .capability = ARM64_ALT_PAN_NOT_UAO,
1098 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1099 .matches = cpufeature_pan_not_uao,
1101 #endif /* CONFIG_ARM64_PAN */
1102 #ifdef CONFIG_ARM64_VHE
1104 .desc = "Virtualization Host Extensions",
1105 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1106 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1107 .matches = runs_at_el2,
1108 .cpu_enable = cpu_copy_el2regs,
1110 #endif /* CONFIG_ARM64_VHE */
1112 .desc = "32-bit EL0 Support",
1113 .capability = ARM64_HAS_32BIT_EL0,
1114 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1115 .matches = has_cpuid_feature,
1116 .sys_reg = SYS_ID_AA64PFR0_EL1,
1117 .sign = FTR_UNSIGNED,
1118 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1119 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1121 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1123 .desc = "Kernel page table isolation (KPTI)",
1124 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1125 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1127 * The ID feature fields below are used to indicate that
1128 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1131 .sys_reg = SYS_ID_AA64PFR0_EL1,
1132 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1133 .min_field_value = 1,
1134 .matches = unmap_kernel_at_el0,
1135 .cpu_enable = kpti_install_ng_mappings,
1139 /* FP/SIMD is not implemented */
1140 .capability = ARM64_HAS_NO_FPSIMD,
1141 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1142 .min_field_value = 0,
1143 .matches = has_no_fpsimd,
1145 #ifdef CONFIG_ARM64_PMEM
1147 .desc = "Data cache clean to Point of Persistence",
1148 .capability = ARM64_HAS_DCPOP,
1149 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1150 .matches = has_cpuid_feature,
1151 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1152 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1153 .min_field_value = 1,
1156 #ifdef CONFIG_ARM64_SVE
1158 .desc = "Scalable Vector Extension",
1159 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1160 .capability = ARM64_SVE,
1161 .sys_reg = SYS_ID_AA64PFR0_EL1,
1162 .sign = FTR_UNSIGNED,
1163 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1164 .min_field_value = ID_AA64PFR0_SVE,
1165 .matches = has_cpuid_feature,
1166 .cpu_enable = sve_kernel_enable,
1168 #endif /* CONFIG_ARM64_SVE */
1169 #ifdef CONFIG_ARM64_RAS_EXTN
1171 .desc = "RAS Extension Support",
1172 .capability = ARM64_HAS_RAS_EXTN,
1173 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1174 .matches = has_cpuid_feature,
1175 .sys_reg = SYS_ID_AA64PFR0_EL1,
1176 .sign = FTR_UNSIGNED,
1177 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1178 .min_field_value = ID_AA64PFR0_RAS_V1,
1179 .cpu_enable = cpu_clear_disr,
1181 #endif /* CONFIG_ARM64_RAS_EXTN */
1183 .desc = "Data cache clean to the PoU not required for I/D coherence",
1184 .capability = ARM64_HAS_CACHE_IDC,
1185 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1186 .matches = has_cache_idc,
1189 .desc = "Instruction cache invalidation not required for I/D coherence",
1190 .capability = ARM64_HAS_CACHE_DIC,
1191 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1192 .matches = has_cache_dic,
1195 .desc = "Stage-2 Force Write-Back",
1196 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1197 .capability = ARM64_HAS_STAGE2_FWB,
1198 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1199 .sign = FTR_UNSIGNED,
1200 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1201 .min_field_value = 1,
1202 .matches = has_cpuid_feature,
1203 .cpu_enable = cpu_has_fwb,
1205 #ifdef CONFIG_ARM64_HW_AFDBM
1208 * Since we turn this on always, we don't want the user to
1209 * think that the feature is available when it may not be.
1210 * So hide the description.
1212 * .desc = "Hardware pagetable Dirty Bit Management",
1215 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1216 .capability = ARM64_HW_DBM,
1217 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1218 .sign = FTR_UNSIGNED,
1219 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1220 .min_field_value = 2,
1221 .matches = has_hw_dbm,
1222 .cpu_enable = cpu_enable_hw_dbm,
1228 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
1231 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
1232 .matches = has_cpuid_feature, \
1234 .field_pos = field, \
1236 .min_field_value = min_value, \
1237 .hwcap_type = cap_type, \
1241 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1242 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
1243 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
1244 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
1245 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
1246 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512),
1247 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
1248 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
1249 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM),
1250 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3),
1251 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3),
1252 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4),
1253 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP),
1254 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM),
1255 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FLAGM),
1256 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
1257 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
1258 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
1259 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
1260 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_DIT),
1261 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),
1262 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
1263 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
1264 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
1265 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ILRCPC),
1266 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_USCAT),
1267 #ifdef CONFIG_ARM64_SVE
1268 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE),
1273 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1274 #ifdef CONFIG_COMPAT
1275 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1276 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1277 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1278 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1279 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1284 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1286 switch (cap->hwcap_type) {
1288 elf_hwcap |= cap->hwcap;
1290 #ifdef CONFIG_COMPAT
1291 case CAP_COMPAT_HWCAP:
1292 compat_elf_hwcap |= (u32)cap->hwcap;
1294 case CAP_COMPAT_HWCAP2:
1295 compat_elf_hwcap2 |= (u32)cap->hwcap;
1304 /* Check if we have a particular HWCAP enabled */
1305 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1309 switch (cap->hwcap_type) {
1311 rc = (elf_hwcap & cap->hwcap) != 0;
1313 #ifdef CONFIG_COMPAT
1314 case CAP_COMPAT_HWCAP:
1315 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1317 case CAP_COMPAT_HWCAP2:
1318 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1329 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1331 /* We support emulation of accesses to CPU ID feature registers */
1332 elf_hwcap |= HWCAP_CPUID;
1333 for (; hwcaps->matches; hwcaps++)
1334 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
1335 cap_set_elf_hwcap(hwcaps);
1339 * Check if the current CPU has a given feature capability.
1340 * Should be called from non-preemptible context.
1342 static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array,
1345 const struct arm64_cpu_capabilities *caps;
1347 if (WARN_ON(preemptible()))
1350 for (caps = cap_array; caps->matches; caps++)
1351 if (caps->capability == cap)
1352 return caps->matches(caps, SCOPE_LOCAL_CPU);
1357 static void __update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1358 u16 scope_mask, const char *info)
1360 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1361 for (; caps->matches; caps++) {
1362 if (!(caps->type & scope_mask) ||
1363 !caps->matches(caps, cpucap_default_scope(caps)))
1366 if (!cpus_have_cap(caps->capability) && caps->desc)
1367 pr_info("%s %s\n", info, caps->desc);
1368 cpus_set_cap(caps->capability);
1372 static void update_cpu_capabilities(u16 scope_mask)
1374 __update_cpu_capabilities(arm64_features, scope_mask, "detected:");
1375 __update_cpu_capabilities(arm64_errata, scope_mask,
1376 "enabling workaround for");
1379 static int __enable_cpu_capability(void *arg)
1381 const struct arm64_cpu_capabilities *cap = arg;
1383 cap->cpu_enable(cap);
1388 * Run through the enabled capabilities and enable() it on all active
1392 __enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1395 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1396 for (; caps->matches; caps++) {
1397 unsigned int num = caps->capability;
1399 if (!(caps->type & scope_mask) || !cpus_have_cap(num))
1402 /* Ensure cpus_have_const_cap(num) works */
1403 static_branch_enable(&cpu_hwcap_keys[num]);
1405 if (caps->cpu_enable) {
1407 * Capabilities with SCOPE_BOOT_CPU scope are finalised
1408 * before any secondary CPU boots. Thus, each secondary
1409 * will enable the capability as appropriate via
1410 * check_local_cpu_capabilities(). The only exception is
1411 * the boot CPU, for which the capability must be
1412 * enabled here. This approach avoids costly
1413 * stop_machine() calls for this case.
1415 * Otherwise, use stop_machine() as it schedules the
1416 * work allowing us to modify PSTATE, instead of
1417 * on_each_cpu() which uses an IPI, giving us a PSTATE
1418 * that disappears when we return.
1420 if (scope_mask & SCOPE_BOOT_CPU)
1421 caps->cpu_enable(caps);
1423 stop_machine(__enable_cpu_capability,
1424 (void *)caps, cpu_online_mask);
1429 static void __init enable_cpu_capabilities(u16 scope_mask)
1431 __enable_cpu_capabilities(arm64_features, scope_mask);
1432 __enable_cpu_capabilities(arm64_errata, scope_mask);
1436 * Run through the list of capabilities to check for conflicts.
1437 * If the system has already detected a capability, take necessary
1438 * action on this CPU.
1440 * Returns "false" on conflicts.
1443 __verify_local_cpu_caps(const struct arm64_cpu_capabilities *caps,
1446 bool cpu_has_cap, system_has_cap;
1448 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1450 for (; caps->matches; caps++) {
1451 if (!(caps->type & scope_mask))
1454 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
1455 system_has_cap = cpus_have_cap(caps->capability);
1457 if (system_has_cap) {
1459 * Check if the new CPU misses an advertised feature,
1460 * which is not safe to miss.
1462 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1465 * We have to issue cpu_enable() irrespective of
1466 * whether the CPU has it or not, as it is enabeld
1467 * system wide. It is upto the call back to take
1468 * appropriate action on this CPU.
1470 if (caps->cpu_enable)
1471 caps->cpu_enable(caps);
1474 * Check if the CPU has this capability if it isn't
1475 * safe to have when the system doesn't.
1477 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1482 if (caps->matches) {
1483 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1484 smp_processor_id(), caps->capability,
1485 caps->desc, system_has_cap, cpu_has_cap);
1492 static bool verify_local_cpu_caps(u16 scope_mask)
1494 return __verify_local_cpu_caps(arm64_errata, scope_mask) &&
1495 __verify_local_cpu_caps(arm64_features, scope_mask);
1499 * Check for CPU features that are used in early boot
1500 * based on the Boot CPU value.
1502 static void check_early_cpu_features(void)
1504 verify_cpu_asid_bits();
1506 * Early features are used by the kernel already. If there
1507 * is a conflict, we cannot proceed further.
1509 if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1514 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1517 for (; caps->matches; caps++)
1518 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1519 pr_crit("CPU%d: missing HWCAP: %s\n",
1520 smp_processor_id(), caps->desc);
1525 static void verify_sve_features(void)
1527 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1528 u64 zcr = read_zcr_features();
1530 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1531 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1533 if (len < safe_len || sve_verify_vq_map()) {
1534 pr_crit("CPU%d: SVE: required vector length(s) missing\n",
1535 smp_processor_id());
1539 /* Add checks on other ZCR bits here if necessary */
1544 * Run through the enabled system capabilities and enable() it on this CPU.
1545 * The capabilities were decided based on the available CPUs at the boot time.
1546 * Any new CPU should match the system wide status of the capability. If the
1547 * new CPU doesn't have a capability which the system now has enabled, we
1548 * cannot do anything to fix it up and could cause unexpected failures. So
1551 static void verify_local_cpu_capabilities(void)
1554 * The capabilities with SCOPE_BOOT_CPU are checked from
1555 * check_early_cpu_features(), as they need to be verified
1556 * on all secondary CPUs.
1558 if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
1561 verify_local_elf_hwcaps(arm64_elf_hwcaps);
1563 if (system_supports_32bit_el0())
1564 verify_local_elf_hwcaps(compat_elf_hwcaps);
1566 if (system_supports_sve())
1567 verify_sve_features();
1570 void check_local_cpu_capabilities(void)
1573 * All secondary CPUs should conform to the early CPU features
1574 * in use by the kernel based on boot CPU.
1576 check_early_cpu_features();
1579 * If we haven't finalised the system capabilities, this CPU gets
1580 * a chance to update the errata work arounds and local features.
1581 * Otherwise, this CPU should verify that it has all the system
1582 * advertised capabilities.
1584 if (!sys_caps_initialised)
1585 update_cpu_capabilities(SCOPE_LOCAL_CPU);
1587 verify_local_cpu_capabilities();
1590 static void __init setup_boot_cpu_capabilities(void)
1592 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
1593 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
1594 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
1595 enable_cpu_capabilities(SCOPE_BOOT_CPU);
1598 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1599 EXPORT_SYMBOL(arm64_const_caps_ready);
1601 static void __init mark_const_caps_ready(void)
1603 static_branch_enable(&arm64_const_caps_ready);
1606 extern const struct arm64_cpu_capabilities arm64_errata[];
1608 bool this_cpu_has_cap(unsigned int cap)
1610 return (__this_cpu_has_cap(arm64_features, cap) ||
1611 __this_cpu_has_cap(arm64_errata, cap));
1614 static void __init setup_system_capabilities(void)
1617 * We have finalised the system-wide safe feature
1618 * registers, finalise the capabilities that depend
1619 * on it. Also enable all the available capabilities,
1620 * that are not enabled already.
1622 update_cpu_capabilities(SCOPE_SYSTEM);
1623 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
1626 void __init setup_cpu_features(void)
1630 setup_system_capabilities();
1631 mark_const_caps_ready();
1632 setup_elf_hwcaps(arm64_elf_hwcaps);
1634 if (system_supports_32bit_el0())
1635 setup_elf_hwcaps(compat_elf_hwcaps);
1637 if (system_uses_ttbr0_pan())
1638 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
1641 minsigstksz_setup();
1643 /* Advertise that we have computed the system capabilities */
1644 set_sys_caps_initialised();
1647 * Check for sane CTR_EL0.CWG value.
1649 cwg = cache_type_cwg();
1651 pr_warn("No Cache Writeback Granule information, assuming %d\n",
1655 static bool __maybe_unused
1656 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
1658 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
1662 * We emulate only the following system register space.
1663 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1664 * See Table C5-6 System instruction encodings for System register accesses,
1665 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1667 static inline bool __attribute_const__ is_emulated(u32 id)
1669 return (sys_reg_Op0(id) == 0x3 &&
1670 sys_reg_CRn(id) == 0x0 &&
1671 sys_reg_Op1(id) == 0x0 &&
1672 (sys_reg_CRm(id) == 0 ||
1673 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
1677 * With CRm == 0, reg should be one of :
1678 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1680 static inline int emulate_id_reg(u32 id, u64 *valp)
1684 *valp = read_cpuid_id();
1687 *valp = SYS_MPIDR_SAFE_VAL;
1689 case SYS_REVIDR_EL1:
1690 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1700 static int emulate_sys_reg(u32 id, u64 *valp)
1702 struct arm64_ftr_reg *regp;
1704 if (!is_emulated(id))
1707 if (sys_reg_CRm(id) == 0)
1708 return emulate_id_reg(id, valp);
1710 regp = get_arm64_ftr_reg(id);
1712 *valp = arm64_ftr_reg_user_value(regp);
1715 * The untracked registers are either IMPLEMENTATION DEFINED
1716 * (e.g, ID_AFR0_EL1) or reserved RAZ.
1722 static int emulate_mrs(struct pt_regs *regs, u32 insn)
1729 * sys_reg values are defined as used in mrs/msr instruction.
1730 * shift the imm value to get the encoding.
1732 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
1733 rc = emulate_sys_reg(sys_reg, &val);
1735 dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
1736 pt_regs_write_reg(regs, dst, val);
1737 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
1743 static struct undef_hook mrs_hook = {
1744 .instr_mask = 0xfff00000,
1745 .instr_val = 0xd5300000,
1746 .pstate_mask = COMPAT_PSR_MODE_MASK,
1747 .pstate_val = PSR_MODE_EL0t,
1751 static int __init enable_mrs_emulation(void)
1753 register_undef_hook(&mrs_hook);
1757 core_initcall(enable_mrs_emulation);
1759 void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1761 /* Firmware may have left a deferred SError in this register. */
1762 write_sysreg_s(0, SYS_DISR_EL1);