2 * Low-level exception handling code
4 * Copyright (C) 2012 ARM Ltd.
5 * Authors: Catalin Marinas <catalin.marinas@arm.com>
6 * Will Deacon <will.deacon@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/init.h>
22 #include <linux/linkage.h>
24 #include <asm/alternative.h>
25 #include <asm/assembler.h>
26 #include <asm/asm-offsets.h>
27 #include <asm/cpufeature.h>
28 #include <asm/errno.h>
31 #include <asm/memory.h>
32 #include <asm/ptrace.h>
33 #include <asm/thread_info.h>
34 #include <asm/asm-uaccess.h>
35 #include <asm/unistd.h>
38 * Context tracking subsystem. Used to instrument transitions
39 * between user and kernel mode.
41 .macro ct_user_exit, syscall = 0
42 #ifdef CONFIG_CONTEXT_TRACKING
43 bl context_tracking_user_exit
46 * Save/restore needed during syscalls. Restore syscall arguments from
47 * the values already saved on stack during kernel_entry.
50 ldp x2, x3, [sp, #S_X2]
51 ldp x4, x5, [sp, #S_X4]
52 ldp x6, x7, [sp, #S_X6]
58 #ifdef CONFIG_CONTEXT_TRACKING
59 bl context_tracking_user_enter
72 .macro kernel_entry, el, regsize = 64
73 sub sp, sp, #S_FRAME_SIZE
75 mov w0, w0 // zero upper 32 bits of x0
77 stp x0, x1, [sp, #16 * 0]
78 stp x2, x3, [sp, #16 * 1]
79 stp x4, x5, [sp, #16 * 2]
80 stp x6, x7, [sp, #16 * 3]
81 stp x8, x9, [sp, #16 * 4]
82 stp x10, x11, [sp, #16 * 5]
83 stp x12, x13, [sp, #16 * 6]
84 stp x14, x15, [sp, #16 * 7]
85 stp x16, x17, [sp, #16 * 8]
86 stp x18, x19, [sp, #16 * 9]
87 stp x20, x21, [sp, #16 * 10]
88 stp x22, x23, [sp, #16 * 11]
89 stp x24, x25, [sp, #16 * 12]
90 stp x26, x27, [sp, #16 * 13]
91 stp x28, x29, [sp, #16 * 14]
95 ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear,
96 ldr x19, [tsk, #TSK_TI_FLAGS] // since we can unmask debug
97 disable_step_tsk x19, x20 // exceptions when scheduling.
99 mov x29, xzr // fp pointed to user-space
101 add x21, sp, #S_FRAME_SIZE
103 /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */
104 ldr x20, [tsk, #TSK_TI_ADDR_LIMIT]
105 str x20, [sp, #S_ORIG_ADDR_LIMIT]
106 mov x20, #TASK_SIZE_64
107 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
108 /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */
109 .endif /* \el == 0 */
112 stp lr, x21, [sp, #S_LR]
115 * In order to be able to dump the contents of struct pt_regs at the
116 * time the exception was taken (in case we attempt to walk the call
117 * stack later), chain it together with the stack frames.
120 stp xzr, xzr, [sp, #S_STACKFRAME]
122 stp x29, x22, [sp, #S_STACKFRAME]
124 add x29, sp, #S_STACKFRAME
126 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
128 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
129 * EL0, there is no need to check the state of TTBR0_EL1 since
130 * accesses are always enabled.
131 * Note that the meaning of this bit differs from the ARMv8.1 PAN
132 * feature as all TTBR0_EL1 accesses are disabled, not just those to
135 alternative_if ARM64_HAS_PAN
136 b 1f // skip TTBR0 PAN
137 alternative_else_nop_endif
141 tst x21, #0xffff << 48 // Check for the reserved ASID
142 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
143 b.eq 1f // TTBR0 access already disabled
144 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
147 __uaccess_ttbr0_disable x21
151 stp x22, x23, [sp, #S_PC]
153 /* Not in a syscall by default (el0_svc overwrites for real syscall) */
156 str w21, [sp, #S_SYSCALLNO]
160 * Set sp_el0 to current thread_info.
167 * Registers that may be useful after this macro is invoked:
171 * x23 - aborted PSTATE
175 .macro kernel_exit, el
177 /* Restore the task's original addr_limit. */
178 ldr x20, [sp, #S_ORIG_ADDR_LIMIT]
179 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
181 /* No need to restore UAO, it will be restored from SPSR_EL1 */
184 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
189 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
191 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
194 alternative_if ARM64_HAS_PAN
195 b 2f // skip TTBR0 PAN
196 alternative_else_nop_endif
199 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
202 __uaccess_ttbr0_enable x0
206 * Enable errata workarounds only if returning to user. The only
207 * workaround currently required for TTBR0_EL1 changes are for the
208 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
211 post_ttbr0_update_workaround
215 and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
221 ldr x23, [sp, #S_SP] // load return stack pointer
223 #ifdef CONFIG_ARM64_ERRATUM_845719
224 alternative_if ARM64_WORKAROUND_845719
226 #ifdef CONFIG_PID_IN_CONTEXTIDR
227 mrs x29, contextidr_el1
228 msr contextidr_el1, x29
230 msr contextidr_el1, xzr
233 alternative_else_nop_endif
237 msr elr_el1, x21 // set up the return data
239 ldp x0, x1, [sp, #16 * 0]
240 ldp x2, x3, [sp, #16 * 1]
241 ldp x4, x5, [sp, #16 * 2]
242 ldp x6, x7, [sp, #16 * 3]
243 ldp x8, x9, [sp, #16 * 4]
244 ldp x10, x11, [sp, #16 * 5]
245 ldp x12, x13, [sp, #16 * 6]
246 ldp x14, x15, [sp, #16 * 7]
247 ldp x16, x17, [sp, #16 * 8]
248 ldp x18, x19, [sp, #16 * 9]
249 ldp x20, x21, [sp, #16 * 10]
250 ldp x22, x23, [sp, #16 * 11]
251 ldp x24, x25, [sp, #16 * 12]
252 ldp x26, x27, [sp, #16 * 13]
253 ldp x28, x29, [sp, #16 * 14]
255 add sp, sp, #S_FRAME_SIZE // restore sp
256 eret // return to kernel
259 .macro irq_stack_entry
260 mov x19, sp // preserve the original sp
263 * Compare sp with the base of the task stack.
264 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
265 * and should switch to the irq stack.
267 ldr x25, [tsk, TSK_STACK]
269 and x25, x25, #~(THREAD_SIZE - 1)
272 adr_this_cpu x25, irq_stack, x26
273 mov x26, #IRQ_STACK_START_SP
276 /* switch to the irq stack */
282 * x19 should be preserved between irq_stack_entry and
285 .macro irq_stack_exit
290 * These are the registers used in the syscall handler, and allow us to
291 * have in theory up to 7 arguments to a function - x0 to x6.
293 * x7 is reserved for the system call number in 32-bit mode.
295 wsc_nr .req w25 // number of system calls
296 wscno .req w26 // syscall number
297 xscno .req x26 // syscall number (zero-extended)
298 stbl .req x27 // syscall table pointer
299 tsk .req x28 // current thread_info
302 * Interrupt handling.
305 ldr_l x1, handle_arch_irq
317 .pushsection ".entry.text", "ax"
321 ventry el1_sync_invalid // Synchronous EL1t
322 ventry el1_irq_invalid // IRQ EL1t
323 ventry el1_fiq_invalid // FIQ EL1t
324 ventry el1_error_invalid // Error EL1t
326 ventry el1_sync // Synchronous EL1h
327 ventry el1_irq // IRQ EL1h
328 ventry el1_fiq_invalid // FIQ EL1h
329 ventry el1_error_invalid // Error EL1h
331 ventry el0_sync // Synchronous 64-bit EL0
332 ventry el0_irq // IRQ 64-bit EL0
333 ventry el0_fiq_invalid // FIQ 64-bit EL0
334 ventry el0_error_invalid // Error 64-bit EL0
337 ventry el0_sync_compat // Synchronous 32-bit EL0
338 ventry el0_irq_compat // IRQ 32-bit EL0
339 ventry el0_fiq_invalid_compat // FIQ 32-bit EL0
340 ventry el0_error_invalid_compat // Error 32-bit EL0
342 ventry el0_sync_invalid // Synchronous 32-bit EL0
343 ventry el0_irq_invalid // IRQ 32-bit EL0
344 ventry el0_fiq_invalid // FIQ 32-bit EL0
345 ventry el0_error_invalid // Error 32-bit EL0
350 * Invalid mode handlers
352 .macro inv_entry, el, reason, regsize = 64
353 kernel_entry \el, \regsize
362 inv_entry 0, BAD_SYNC
363 ENDPROC(el0_sync_invalid)
367 ENDPROC(el0_irq_invalid)
371 ENDPROC(el0_fiq_invalid)
374 inv_entry 0, BAD_ERROR
375 ENDPROC(el0_error_invalid)
378 el0_fiq_invalid_compat:
379 inv_entry 0, BAD_FIQ, 32
380 ENDPROC(el0_fiq_invalid_compat)
382 el0_error_invalid_compat:
383 inv_entry 0, BAD_ERROR, 32
384 ENDPROC(el0_error_invalid_compat)
388 inv_entry 1, BAD_SYNC
389 ENDPROC(el1_sync_invalid)
393 ENDPROC(el1_irq_invalid)
397 ENDPROC(el1_fiq_invalid)
400 inv_entry 1, BAD_ERROR
401 ENDPROC(el1_error_invalid)
409 mrs x1, esr_el1 // read the syndrome register
410 lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class
411 cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1
413 cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1
415 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
417 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
419 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
421 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1
423 cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1
429 * Fall through to the Data abort case
433 * Data abort handling
437 // re-enable interrupts if they were enabled in the aborted context
438 tbnz x23, #7, 1f // PSR_I_BIT
441 clear_address_tag x0, x3
442 mov x2, sp // struct pt_regs
445 // disable interrupts before pulling preserved data off the stack
450 * Stack or PC alignment exception handling
459 * Undefined instruction
467 * Debug exception handling
469 cmp x24, #ESR_ELx_EC_BRK64 // if BRK64
470 cinc x24, x24, eq // set bit '0'
471 tbz x24, #0, el1_inv // EL1 only
473 mov x2, sp // struct pt_regs
474 bl do_debug_exception
477 // TODO: add support for undefined instructions in kernel mode
490 #ifdef CONFIG_TRACE_IRQFLAGS
491 bl trace_hardirqs_off
496 #ifdef CONFIG_PREEMPT
497 ldr w24, [tsk, #TSK_TI_PREEMPT] // get preempt count
498 cbnz w24, 1f // preempt count != 0
499 ldr x0, [tsk, #TSK_TI_FLAGS] // get flags
500 tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
504 #ifdef CONFIG_TRACE_IRQFLAGS
510 #ifdef CONFIG_PREEMPT
513 1: bl preempt_schedule_irq // irq en/disable is done inside
514 ldr x0, [tsk, #TSK_TI_FLAGS] // get new tasks TI_FLAGS
515 tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
525 mrs x25, esr_el1 // read the syndrome register
526 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
527 cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state
529 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
531 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
533 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
535 cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception
537 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
539 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
541 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
543 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
545 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
553 mrs x25, esr_el1 // read the syndrome register
554 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
555 cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state
557 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
559 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
561 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
563 cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception
565 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
567 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
569 cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap
571 cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap
573 cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap
575 cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap
577 cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap
579 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
584 * AArch32 syscall handling
586 adrp stbl, compat_sys_call_table // load compat syscall table pointer
587 mov wscno, w7 // syscall number in w7 (r7)
588 mov wsc_nr, #__NR_compat_syscalls
599 * Data abort handling
602 // enable interrupts before calling the main handler
605 clear_address_tag x0, x26
612 * Instruction abort handling
615 // enable interrupts before calling the main handler
625 * Floating Point or Advanced SIMD access
635 * Floating Point or Advanced SIMD exception
645 * Stack or PC alignment exception handling
648 // enable interrupts before calling the main handler
658 * Undefined instruction
660 // enable interrupts before calling the main handler
668 * System instructions, for trapped cache maintenance instructions
678 * Debug exception handling
680 tbnz x24, #0, el0_inv // EL0 only
684 bl do_debug_exception
703 #ifdef CONFIG_TRACE_IRQFLAGS
704 bl trace_hardirqs_off
710 #ifdef CONFIG_TRACE_IRQFLAGS
717 * This is the fast syscall return path. We do as little as possible here,
718 * and this includes saving x0 back into the kernel stack.
721 disable_irq // disable interrupts
722 str x0, [sp, #S_X0] // returned x0
723 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for syscall tracing
724 and x2, x1, #_TIF_SYSCALL_WORK
725 cbnz x2, ret_fast_syscall_trace
726 and x2, x1, #_TIF_WORK_MASK
727 cbnz x2, work_pending
728 enable_step_tsk x1, x2
730 ret_fast_syscall_trace:
731 enable_irq // enable interrupts
732 b __sys_trace_return_skipped // we already saved x0
735 * Ok, we need to do extra processing, enter the slow path.
740 #ifdef CONFIG_TRACE_IRQFLAGS
741 bl trace_hardirqs_on // enabled while in userspace
743 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step
746 * "slow" syscall return path.
749 disable_irq // disable interrupts
750 ldr x1, [tsk, #TSK_TI_FLAGS]
751 and x2, x1, #_TIF_WORK_MASK
752 cbnz x2, work_pending
754 enable_step_tsk x1, x2
763 adrp stbl, sys_call_table // load syscall table pointer
764 mov wscno, w8 // syscall number in w8
765 mov wsc_nr, #__NR_syscalls
766 el0_svc_naked: // compat entry point
767 stp x0, xscno, [sp, #S_ORIG_X0] // save the original x0 and syscall number
771 ldr x16, [tsk, #TSK_TI_FLAGS] // check for syscall hooks
772 tst x16, #_TIF_SYSCALL_WORK
774 cmp wscno, wsc_nr // check upper syscall limit
776 ldr x16, [stbl, xscno, lsl #3] // address in the syscall table
777 blr x16 // call sys_* routine
786 * This is the really slow path. We're going to be doing context
787 * switches, and waiting for our parent to respond.
790 cmp wscno, #NO_SYSCALL // user-issued syscall(-1)?
792 mov x0, #-ENOSYS // set default errno if so
795 bl syscall_trace_enter
796 cmp w0, #NO_SYSCALL // skip the syscall?
797 b.eq __sys_trace_return_skipped
798 mov wscno, w0 // syscall number (possibly new)
799 mov x1, sp // pointer to regs
800 cmp wscno, wsc_nr // check upper syscall limit
802 ldp x0, x1, [sp] // restore the syscall args
803 ldp x2, x3, [sp, #S_X2]
804 ldp x4, x5, [sp, #S_X4]
805 ldp x6, x7, [sp, #S_X6]
806 ldr x16, [stbl, xscno, lsl #3] // address in the syscall table
807 blr x16 // call sys_* routine
810 str x0, [sp, #S_X0] // save returned x0
811 __sys_trace_return_skipped:
813 bl syscall_trace_exit
821 .popsection // .entry.text
824 * Special system call wrappers.
826 ENTRY(sys_rt_sigreturn_wrapper)
829 ENDPROC(sys_rt_sigreturn_wrapper)
832 * Register switch for AArch64. The callee-saved registers need to be saved
833 * and restored. On entry:
834 * x0 = previous task_struct (must be preserved across the switch)
835 * x1 = next task_struct
836 * Previous and next are guaranteed not to be the same.
840 mov x10, #THREAD_CPU_CONTEXT
843 stp x19, x20, [x8], #16 // store callee-saved registers
844 stp x21, x22, [x8], #16
845 stp x23, x24, [x8], #16
846 stp x25, x26, [x8], #16
847 stp x27, x28, [x8], #16
848 stp x29, x9, [x8], #16
851 ldp x19, x20, [x8], #16 // restore callee-saved registers
852 ldp x21, x22, [x8], #16
853 ldp x23, x24, [x8], #16
854 ldp x25, x26, [x8], #16
855 ldp x27, x28, [x8], #16
856 ldp x29, x9, [x8], #16
861 ENDPROC(cpu_switch_to)
862 NOKPROBE(cpu_switch_to)
865 * This is how we return from a fork.
869 cbz x19, 1f // not a kernel thread
872 1: get_thread_info tsk
874 ENDPROC(ret_from_fork)
875 NOKPROBE(ret_from_fork)