2 * Based on arch/arm/kernel/traps.c
4 * Copyright (C) 1995-2009 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/bug.h>
21 #include <linux/signal.h>
22 #include <linux/personality.h>
23 #include <linux/kallsyms.h>
24 #include <linux/spinlock.h>
25 #include <linux/uaccess.h>
26 #include <linux/hardirq.h>
27 #include <linux/kdebug.h>
28 #include <linux/module.h>
29 #include <linux/kexec.h>
30 #include <linux/delay.h>
31 #include <linux/init.h>
32 #include <linux/sched/signal.h>
33 #include <linux/sched/debug.h>
34 #include <linux/sched/task_stack.h>
35 #include <linux/sizes.h>
36 #include <linux/syscalls.h>
37 #include <linux/mm_types.h>
38 #include <linux/kasan.h>
40 #include <asm/atomic.h>
42 #include <asm/cpufeature.h>
43 #include <asm/daifflags.h>
44 #include <asm/debug-monitors.h>
47 #include <asm/traps.h>
49 #include <asm/stack_pointer.h>
50 #include <asm/stacktrace.h>
51 #include <asm/exception.h>
52 #include <asm/system_misc.h>
53 #include <asm/sysreg.h>
55 static const char *handler[]= {
62 int show_unhandled_signals = 0;
64 static void dump_backtrace_entry(unsigned long where)
66 printk(" %pS\n", (void *)where);
69 static void __dump_instr(const char *lvl, struct pt_regs *regs)
71 unsigned long addr = instruction_pointer(regs);
72 char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str;
75 for (i = -4; i < 1; i++) {
76 unsigned int val, bad;
78 bad = get_user(val, &((u32 *)addr)[i]);
81 p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val);
83 p += sprintf(p, "bad PC value");
87 printk("%sCode: %s\n", lvl, str);
90 static void dump_instr(const char *lvl, struct pt_regs *regs)
92 if (!user_mode(regs)) {
93 mm_segment_t fs = get_fs();
95 __dump_instr(lvl, regs);
98 __dump_instr(lvl, regs);
102 void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk)
104 struct stackframe frame;
107 pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk);
112 if (!try_get_task_stack(tsk))
115 if (tsk == current) {
116 frame.fp = (unsigned long)__builtin_frame_address(0);
117 frame.pc = (unsigned long)dump_backtrace;
120 * task blocked in __switch_to
122 frame.fp = thread_saved_fp(tsk);
123 frame.pc = thread_saved_pc(tsk);
125 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
126 frame.graph = tsk->curr_ret_stack;
130 printk("Call trace:\n");
132 /* skip until specified stack frame */
134 dump_backtrace_entry(frame.pc);
135 } else if (frame.fp == regs->regs[29]) {
138 * Mostly, this is the case where this function is
139 * called in panic/abort. As exception handler's
140 * stack frame does not contain the corresponding pc
141 * at which an exception has taken place, use regs->pc
144 dump_backtrace_entry(regs->pc);
146 } while (!unwind_frame(tsk, &frame));
151 void show_stack(struct task_struct *tsk, unsigned long *sp)
153 dump_backtrace(NULL, tsk);
157 #ifdef CONFIG_PREEMPT
158 #define S_PREEMPT " PREEMPT"
164 static int __die(const char *str, int err, struct pt_regs *regs)
166 struct task_struct *tsk = current;
167 static int die_counter;
170 pr_emerg("Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n",
171 str, err, ++die_counter);
173 /* trap and error numbers are mostly meaningless on ARM */
174 ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV);
175 if (ret == NOTIFY_STOP)
180 pr_emerg("Process %.*s (pid: %d, stack limit = 0x%p)\n",
181 TASK_COMM_LEN, tsk->comm, task_pid_nr(tsk),
184 if (!user_mode(regs)) {
185 dump_backtrace(regs, tsk);
186 dump_instr(KERN_EMERG, regs);
192 static DEFINE_RAW_SPINLOCK(die_lock);
195 * This function is protected against re-entrancy.
197 void die(const char *str, struct pt_regs *regs, int err)
202 raw_spin_lock_irqsave(&die_lock, flags);
208 ret = __die(str, err, regs);
210 if (regs && kexec_should_crash(current))
214 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
218 panic("Fatal exception in interrupt");
220 panic("Fatal exception");
222 raw_spin_unlock_irqrestore(&die_lock, flags);
224 if (ret != NOTIFY_STOP)
228 static void arm64_show_signal(int signo, const char *str)
230 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
231 DEFAULT_RATELIMIT_BURST);
232 struct task_struct *tsk = current;
233 unsigned int esr = tsk->thread.fault_code;
234 struct pt_regs *regs = task_pt_regs(tsk);
236 /* Leave if the signal won't be shown */
237 if (!show_unhandled_signals ||
238 !unhandled_signal(tsk, signo) ||
242 pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk));
244 pr_cont("%s, ESR 0x%08x, ", esr_get_class_string(esr), esr);
247 print_vma_addr(KERN_CONT " in ", regs->pc);
252 void arm64_force_sig_fault(int signo, int code, void __user *addr,
255 arm64_show_signal(signo, str);
256 force_sig_fault(signo, code, addr, current);
259 void arm64_force_sig_mceerr(int code, void __user *addr, short lsb,
262 arm64_show_signal(SIGBUS, str);
263 force_sig_mceerr(code, addr, lsb, current);
266 void arm64_force_sig_ptrace_errno_trap(int errno, void __user *addr,
269 arm64_show_signal(SIGTRAP, str);
270 force_sig_ptrace_errno_trap(errno, addr);
273 void arm64_notify_die(const char *str, struct pt_regs *regs,
274 int signo, int sicode, void __user *addr,
277 if (user_mode(regs)) {
278 WARN_ON(regs != current_pt_regs());
279 current->thread.fault_address = 0;
280 current->thread.fault_code = err;
282 arm64_force_sig_fault(signo, sicode, addr, str);
288 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size)
293 * If we were single stepping, we want to get the step exception after
294 * we return from the trap.
297 user_fastforward_single_step(current);
300 static LIST_HEAD(undef_hook);
301 static DEFINE_RAW_SPINLOCK(undef_lock);
303 void register_undef_hook(struct undef_hook *hook)
307 raw_spin_lock_irqsave(&undef_lock, flags);
308 list_add(&hook->node, &undef_hook);
309 raw_spin_unlock_irqrestore(&undef_lock, flags);
312 void unregister_undef_hook(struct undef_hook *hook)
316 raw_spin_lock_irqsave(&undef_lock, flags);
317 list_del(&hook->node);
318 raw_spin_unlock_irqrestore(&undef_lock, flags);
321 static int call_undef_hook(struct pt_regs *regs)
323 struct undef_hook *hook;
326 int (*fn)(struct pt_regs *regs, u32 instr) = NULL;
327 void __user *pc = (void __user *)instruction_pointer(regs);
329 if (!user_mode(regs)) {
331 if (probe_kernel_address((__force __le32 *)pc, instr_le))
333 instr = le32_to_cpu(instr_le);
334 } else if (compat_thumb_mode(regs)) {
335 /* 16-bit Thumb instruction */
337 if (get_user(instr_le, (__le16 __user *)pc))
339 instr = le16_to_cpu(instr_le);
340 if (aarch32_insn_is_wide(instr)) {
343 if (get_user(instr_le, (__le16 __user *)(pc + 2)))
345 instr2 = le16_to_cpu(instr_le);
346 instr = (instr << 16) | instr2;
349 /* 32-bit ARM instruction */
351 if (get_user(instr_le, (__le32 __user *)pc))
353 instr = le32_to_cpu(instr_le);
356 raw_spin_lock_irqsave(&undef_lock, flags);
357 list_for_each_entry(hook, &undef_hook, node)
358 if ((instr & hook->instr_mask) == hook->instr_val &&
359 (regs->pstate & hook->pstate_mask) == hook->pstate_val)
362 raw_spin_unlock_irqrestore(&undef_lock, flags);
364 return fn ? fn(regs, instr) : 1;
367 void force_signal_inject(int signal, int code, unsigned long address)
370 struct pt_regs *regs = current_pt_regs();
372 if (WARN_ON(!user_mode(regs)))
377 desc = "undefined instruction";
380 desc = "illegal memory access";
383 desc = "unknown or unrecoverable error";
387 /* Force signals we don't understand to SIGKILL */
388 if (WARN_ON(signal != SIGKILL &&
389 siginfo_layout(signal, code) != SIL_FAULT)) {
393 arm64_notify_die(desc, regs, signal, code, (void __user *)address, 0);
397 * Set up process info to signal segmentation fault - called on access error.
399 void arm64_notify_segfault(unsigned long addr)
403 down_read(¤t->mm->mmap_sem);
404 if (find_vma(current->mm, addr) == NULL)
408 up_read(¤t->mm->mmap_sem);
410 force_signal_inject(SIGSEGV, code, addr);
413 asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
415 /* check for AArch32 breakpoint instructions */
416 if (!aarch32_break_handler(regs))
419 if (call_undef_hook(regs) == 0)
422 BUG_ON(!user_mode(regs));
423 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
426 #define __user_cache_maint(insn, address, res) \
427 if (address >= user_addr_max()) { \
430 uaccess_ttbr0_enable(); \
432 "1: " insn ", %1\n" \
435 " .pushsection .fixup,\"ax\"\n" \
437 "3: mov %w0, %w2\n" \
440 _ASM_EXTABLE(1b, 3b) \
442 : "r" (address), "i" (-EFAULT)); \
443 uaccess_ttbr0_disable(); \
446 static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs)
448 unsigned long address;
449 int rt = ESR_ELx_SYS64_ISS_RT(esr);
450 int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;
453 address = untagged_addr(pt_regs_read_reg(regs, rt));
456 case ESR_ELx_SYS64_ISS_CRM_DC_CVAU: /* DC CVAU, gets promoted */
457 __user_cache_maint("dc civac", address, ret);
459 case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */
460 __user_cache_maint("dc civac", address, ret);
462 case ESR_ELx_SYS64_ISS_CRM_DC_CVAP: /* DC CVAP */
463 __user_cache_maint("sys 3, c7, c12, 1", address, ret);
465 case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC: /* DC CIVAC */
466 __user_cache_maint("dc civac", address, ret);
468 case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */
469 __user_cache_maint("ic ivau", address, ret);
472 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
477 arm64_notify_segfault(address);
479 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
482 static void ctr_read_handler(unsigned int esr, struct pt_regs *regs)
484 int rt = ESR_ELx_SYS64_ISS_RT(esr);
485 unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);
487 pt_regs_write_reg(regs, rt, val);
489 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
492 static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
494 int rt = ESR_ELx_SYS64_ISS_RT(esr);
496 pt_regs_write_reg(regs, rt, arch_counter_get_cntvct());
497 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
500 static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)
502 int rt = ESR_ELx_SYS64_ISS_RT(esr);
504 pt_regs_write_reg(regs, rt, arch_timer_get_rate());
505 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
508 static void mrs_handler(unsigned int esr, struct pt_regs *regs)
512 rt = ESR_ELx_SYS64_ISS_RT(esr);
513 sysreg = esr_sys64_to_sysreg(esr);
515 if (do_emulate_mrs(regs, sysreg, rt) != 0)
516 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc);
519 static void wfi_handler(unsigned int esr, struct pt_regs *regs)
521 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
525 unsigned int esr_mask;
526 unsigned int esr_val;
527 void (*handler)(unsigned int esr, struct pt_regs *regs);
530 static struct sys64_hook sys64_hooks[] = {
532 .esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK,
533 .esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL,
534 .handler = user_cache_maint_handler,
537 /* Trap read access to CTR_EL0 */
538 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
539 .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ,
540 .handler = ctr_read_handler,
543 /* Trap read access to CNTVCT_EL0 */
544 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
545 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT,
546 .handler = cntvct_read_handler,
549 /* Trap read access to CNTFRQ_EL0 */
550 .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
551 .esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ,
552 .handler = cntfrq_read_handler,
555 /* Trap read access to CPUID registers */
556 .esr_mask = ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK,
557 .esr_val = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL,
558 .handler = mrs_handler,
561 /* Trap WFI instructions executed in userspace */
562 .esr_mask = ESR_ELx_WFx_MASK,
563 .esr_val = ESR_ELx_WFx_WFI_VAL,
564 .handler = wfi_handler,
571 #define PSTATE_IT_1_0_SHIFT 25
572 #define PSTATE_IT_1_0_MASK (0x3 << PSTATE_IT_1_0_SHIFT)
573 #define PSTATE_IT_7_2_SHIFT 10
574 #define PSTATE_IT_7_2_MASK (0x3f << PSTATE_IT_7_2_SHIFT)
576 static u32 compat_get_it_state(struct pt_regs *regs)
578 u32 it, pstate = regs->pstate;
580 it = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT;
581 it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2;
586 static void compat_set_it_state(struct pt_regs *regs, u32 it)
590 pstate_it = (it << PSTATE_IT_1_0_SHIFT) & PSTATE_IT_1_0_MASK;
591 pstate_it |= ((it >> 2) << PSTATE_IT_7_2_SHIFT) & PSTATE_IT_7_2_MASK;
593 regs->pstate &= ~PSR_AA32_IT_MASK;
594 regs->pstate |= pstate_it;
597 static bool cp15_cond_valid(unsigned int esr, struct pt_regs *regs)
601 /* Only a T32 instruction can trap without CV being set */
602 if (!(esr & ESR_ELx_CV)) {
605 it = compat_get_it_state(regs);
611 cond = (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
614 return aarch32_opcode_cond_checks[cond](regs->pstate);
617 static void advance_itstate(struct pt_regs *regs)
622 if (!(regs->pstate & PSR_AA32_T_BIT) ||
623 !(regs->pstate & PSR_AA32_IT_MASK))
626 it = compat_get_it_state(regs);
629 * If this is the last instruction of the block, wipe the IT
630 * state. Otherwise advance it.
635 it = (it & 0xe0) | ((it << 1) & 0x1f);
637 compat_set_it_state(regs, it);
640 static void arm64_compat_skip_faulting_instruction(struct pt_regs *regs,
643 advance_itstate(regs);
644 arm64_skip_faulting_instruction(regs, sz);
647 static void compat_cntfrq_read_handler(unsigned int esr, struct pt_regs *regs)
649 int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT;
651 pt_regs_write_reg(regs, reg, arch_timer_get_rate());
652 arm64_compat_skip_faulting_instruction(regs, 4);
655 static struct sys64_hook cp15_32_hooks[] = {
657 .esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK,
658 .esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ,
659 .handler = compat_cntfrq_read_handler,
664 static void compat_cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
666 int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> ESR_ELx_CP15_64_ISS_RT_SHIFT;
667 int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT;
668 u64 val = arch_counter_get_cntvct();
670 pt_regs_write_reg(regs, rt, lower_32_bits(val));
671 pt_regs_write_reg(regs, rt2, upper_32_bits(val));
672 arm64_compat_skip_faulting_instruction(regs, 4);
675 static struct sys64_hook cp15_64_hooks[] = {
677 .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK,
678 .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT,
679 .handler = compat_cntvct_read_handler,
684 asmlinkage void __exception do_cp15instr(unsigned int esr, struct pt_regs *regs)
686 struct sys64_hook *hook, *hook_base;
688 if (!cp15_cond_valid(esr, regs)) {
690 * There is no T16 variant of a CP access, so we
691 * always advance PC by 4 bytes.
693 arm64_compat_skip_faulting_instruction(regs, 4);
697 switch (ESR_ELx_EC(esr)) {
698 case ESR_ELx_EC_CP15_32:
699 hook_base = cp15_32_hooks;
701 case ESR_ELx_EC_CP15_64:
702 hook_base = cp15_64_hooks;
709 for (hook = hook_base; hook->handler; hook++)
710 if ((hook->esr_mask & esr) == hook->esr_val) {
711 hook->handler(esr, regs);
716 * New cp15 instructions may previously have been undefined at
717 * EL0. Fall back to our usual undefined instruction handler
718 * so that we handle these consistently.
724 asmlinkage void __exception do_sysinstr(unsigned int esr, struct pt_regs *regs)
726 struct sys64_hook *hook;
728 for (hook = sys64_hooks; hook->handler; hook++)
729 if ((hook->esr_mask & esr) == hook->esr_val) {
730 hook->handler(esr, regs);
735 * New SYS instructions may previously have been undefined at EL0. Fall
736 * back to our usual undefined instruction handler so that we handle
737 * these consistently.
742 static const char *esr_class_str[] = {
743 [0 ... ESR_ELx_EC_MAX] = "UNRECOGNIZED EC",
744 [ESR_ELx_EC_UNKNOWN] = "Unknown/Uncategorized",
745 [ESR_ELx_EC_WFx] = "WFI/WFE",
746 [ESR_ELx_EC_CP15_32] = "CP15 MCR/MRC",
747 [ESR_ELx_EC_CP15_64] = "CP15 MCRR/MRRC",
748 [ESR_ELx_EC_CP14_MR] = "CP14 MCR/MRC",
749 [ESR_ELx_EC_CP14_LS] = "CP14 LDC/STC",
750 [ESR_ELx_EC_FP_ASIMD] = "ASIMD",
751 [ESR_ELx_EC_CP10_ID] = "CP10 MRC/VMRS",
752 [ESR_ELx_EC_CP14_64] = "CP14 MCRR/MRRC",
753 [ESR_ELx_EC_ILL] = "PSTATE.IL",
754 [ESR_ELx_EC_SVC32] = "SVC (AArch32)",
755 [ESR_ELx_EC_HVC32] = "HVC (AArch32)",
756 [ESR_ELx_EC_SMC32] = "SMC (AArch32)",
757 [ESR_ELx_EC_SVC64] = "SVC (AArch64)",
758 [ESR_ELx_EC_HVC64] = "HVC (AArch64)",
759 [ESR_ELx_EC_SMC64] = "SMC (AArch64)",
760 [ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)",
761 [ESR_ELx_EC_SVE] = "SVE",
762 [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF",
763 [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)",
764 [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)",
765 [ESR_ELx_EC_PC_ALIGN] = "PC Alignment",
766 [ESR_ELx_EC_DABT_LOW] = "DABT (lower EL)",
767 [ESR_ELx_EC_DABT_CUR] = "DABT (current EL)",
768 [ESR_ELx_EC_SP_ALIGN] = "SP Alignment",
769 [ESR_ELx_EC_FP_EXC32] = "FP (AArch32)",
770 [ESR_ELx_EC_FP_EXC64] = "FP (AArch64)",
771 [ESR_ELx_EC_SERROR] = "SError",
772 [ESR_ELx_EC_BREAKPT_LOW] = "Breakpoint (lower EL)",
773 [ESR_ELx_EC_BREAKPT_CUR] = "Breakpoint (current EL)",
774 [ESR_ELx_EC_SOFTSTP_LOW] = "Software Step (lower EL)",
775 [ESR_ELx_EC_SOFTSTP_CUR] = "Software Step (current EL)",
776 [ESR_ELx_EC_WATCHPT_LOW] = "Watchpoint (lower EL)",
777 [ESR_ELx_EC_WATCHPT_CUR] = "Watchpoint (current EL)",
778 [ESR_ELx_EC_BKPT32] = "BKPT (AArch32)",
779 [ESR_ELx_EC_VECTOR32] = "Vector catch (AArch32)",
780 [ESR_ELx_EC_BRK64] = "BRK (AArch64)",
783 const char *esr_get_class_string(u32 esr)
785 return esr_class_str[ESR_ELx_EC(esr)];
789 * bad_mode handles the impossible case in the exception vector. This is always
792 asmlinkage void bad_mode(struct pt_regs *regs, int reason, unsigned int esr)
796 pr_crit("Bad mode in %s handler detected on CPU%d, code 0x%08x -- %s\n",
797 handler[reason], smp_processor_id(), esr,
798 esr_get_class_string(esr));
805 * bad_el0_sync handles unexpected, but potentially recoverable synchronous
806 * exceptions taken from EL0. Unlike bad_mode, this returns.
808 asmlinkage void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr)
810 void __user *pc = (void __user *)instruction_pointer(regs);
812 current->thread.fault_address = 0;
813 current->thread.fault_code = esr;
815 arm64_force_sig_fault(SIGILL, ILL_ILLOPC, pc,
816 "Bad EL0 synchronous exception");
819 #ifdef CONFIG_VMAP_STACK
821 DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack)
824 asmlinkage void handle_bad_stack(struct pt_regs *regs)
826 unsigned long tsk_stk = (unsigned long)current->stack;
827 unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr);
828 unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack);
829 unsigned int esr = read_sysreg(esr_el1);
830 unsigned long far = read_sysreg(far_el1);
833 pr_emerg("Insufficient stack space to handle exception!");
835 pr_emerg("ESR: 0x%08x -- %s\n", esr, esr_get_class_string(esr));
836 pr_emerg("FAR: 0x%016lx\n", far);
838 pr_emerg("Task stack: [0x%016lx..0x%016lx]\n",
839 tsk_stk, tsk_stk + THREAD_SIZE);
840 pr_emerg("IRQ stack: [0x%016lx..0x%016lx]\n",
841 irq_stk, irq_stk + THREAD_SIZE);
842 pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n",
843 ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE);
848 * We use nmi_panic to limit the potential for recusive overflows, and
849 * to get a better stack trace.
851 nmi_panic(NULL, "kernel stack overflow");
856 void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr)
860 pr_crit("SError Interrupt on CPU%d, code 0x%08x -- %s\n",
861 smp_processor_id(), esr, esr_get_class_string(esr));
865 nmi_panic(regs, "Asynchronous SError Interrupt");
871 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr)
873 u32 aet = arm64_ras_serror_get_severity(esr);
876 case ESR_ELx_AET_CE: /* corrected error */
877 case ESR_ELx_AET_UEO: /* restartable, not yet consumed */
879 * The CPU can make progress. We may take UEO again as
880 * a more severe error.
884 case ESR_ELx_AET_UEU: /* Uncorrected Unrecoverable */
885 case ESR_ELx_AET_UER: /* Uncorrected Recoverable */
887 * The CPU can't make progress. The exception may have
892 case ESR_ELx_AET_UC: /* Uncontainable or Uncategorized error */
894 /* Error has been silently propagated */
895 arm64_serror_panic(regs, esr);
899 asmlinkage void do_serror(struct pt_regs *regs, unsigned int esr)
903 /* non-RAS errors are not containable */
904 if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr))
905 arm64_serror_panic(regs, esr);
910 void __pte_error(const char *file, int line, unsigned long val)
912 pr_err("%s:%d: bad pte %016lx.\n", file, line, val);
915 void __pmd_error(const char *file, int line, unsigned long val)
917 pr_err("%s:%d: bad pmd %016lx.\n", file, line, val);
920 void __pud_error(const char *file, int line, unsigned long val)
922 pr_err("%s:%d: bad pud %016lx.\n", file, line, val);
925 void __pgd_error(const char *file, int line, unsigned long val)
927 pr_err("%s:%d: bad pgd %016lx.\n", file, line, val);
930 /* GENERIC_BUG traps */
932 int is_valid_bugaddr(unsigned long addr)
935 * bug_handler() only called for BRK #BUG_BRK_IMM.
936 * So the answer is trivial -- any spurious instances with no
937 * bug table entry will be rejected by report_bug() and passed
938 * back to the debug-monitors code and handled as a fatal
939 * unexpected debug exception.
944 static int bug_handler(struct pt_regs *regs, unsigned int esr)
947 return DBG_HOOK_ERROR;
949 switch (report_bug(regs->pc, regs)) {
950 case BUG_TRAP_TYPE_BUG:
951 die("Oops - BUG", regs, 0);
954 case BUG_TRAP_TYPE_WARN:
958 /* unknown/unrecognised bug trap type */
959 return DBG_HOOK_ERROR;
962 /* If thread survives, skip over the BUG instruction and continue: */
963 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
964 return DBG_HOOK_HANDLED;
967 static struct break_hook bug_break_hook = {
968 .esr_val = 0xf2000000 | BUG_BRK_IMM,
969 .esr_mask = 0xffffffff,
973 #ifdef CONFIG_KASAN_SW_TAGS
975 #define KASAN_ESR_RECOVER 0x20
976 #define KASAN_ESR_WRITE 0x10
977 #define KASAN_ESR_SIZE_MASK 0x0f
978 #define KASAN_ESR_SIZE(esr) (1 << ((esr) & KASAN_ESR_SIZE_MASK))
980 static int kasan_handler(struct pt_regs *regs, unsigned int esr)
982 bool recover = esr & KASAN_ESR_RECOVER;
983 bool write = esr & KASAN_ESR_WRITE;
984 size_t size = KASAN_ESR_SIZE(esr);
985 u64 addr = regs->regs[0];
989 return DBG_HOOK_ERROR;
991 kasan_report(addr, size, write, pc);
994 * The instrumentation allows to control whether we can proceed after
995 * a crash was detected. This is done by passing the -recover flag to
996 * the compiler. Disabling recovery allows to generate more compact
999 * Unfortunately disabling recovery doesn't work for the kernel right
1000 * now. KASAN reporting is disabled in some contexts (for example when
1001 * the allocator accesses slab object metadata; this is controlled by
1002 * current->kasan_depth). All these accesses are detected by the tool,
1003 * even though the reports for them are not printed.
1005 * This is something that might be fixed at some point in the future.
1008 die("Oops - KASAN", regs, 0);
1010 /* If thread survives, skip over the brk instruction and continue: */
1011 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
1012 return DBG_HOOK_HANDLED;
1015 #define KASAN_ESR_VAL (0xf2000000 | KASAN_BRK_IMM)
1016 #define KASAN_ESR_MASK 0xffffff00
1018 static struct break_hook kasan_break_hook = {
1019 .esr_val = KASAN_ESR_VAL,
1020 .esr_mask = KASAN_ESR_MASK,
1021 .fn = kasan_handler,
1026 * Initial handler for AArch64 BRK exceptions
1027 * This handler only used until debug_traps_init().
1029 int __init early_brk64(unsigned long addr, unsigned int esr,
1030 struct pt_regs *regs)
1032 #ifdef CONFIG_KASAN_SW_TAGS
1033 if ((esr & KASAN_ESR_MASK) == KASAN_ESR_VAL)
1034 return kasan_handler(regs, esr) != DBG_HOOK_HANDLED;
1036 return bug_handler(regs, esr) != DBG_HOOK_HANDLED;
1039 /* This registration must happen early, before debug_traps_init(). */
1040 void __init trap_init(void)
1042 register_break_hook(&bug_break_hook);
1043 #ifdef CONFIG_KASAN_SW_TAGS
1044 register_break_hook(&kasan_break_hook);