1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
6 * Derived from arch/arm/kvm/guest.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
11 #include <linux/bits.h>
12 #include <linux/errno.h>
13 #include <linux/err.h>
14 #include <linux/nospec.h>
15 #include <linux/kvm_host.h>
16 #include <linux/module.h>
17 #include <linux/stddef.h>
18 #include <linux/string.h>
19 #include <linux/vmalloc.h>
21 #include <kvm/arm_psci.h>
22 #include <asm/cputype.h>
23 #include <linux/uaccess.h>
24 #include <asm/fpsimd.h>
26 #include <asm/kvm_emulate.h>
27 #include <asm/kvm_coproc.h>
28 #include <asm/kvm_host.h>
29 #include <asm/sigcontext.h>
33 #define VM_STAT(x) { #x, offsetof(struct kvm, stat.x), KVM_STAT_VM }
34 #define VCPU_STAT(x) { #x, offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU }
36 struct kvm_stats_debugfs_item debugfs_entries[] = {
37 VCPU_STAT(halt_successful_poll),
38 VCPU_STAT(halt_attempted_poll),
39 VCPU_STAT(halt_poll_invalid),
40 VCPU_STAT(halt_wakeup),
41 VCPU_STAT(hvc_exit_stat),
42 VCPU_STAT(wfe_exit_stat),
43 VCPU_STAT(wfi_exit_stat),
44 VCPU_STAT(mmio_exit_user),
45 VCPU_STAT(mmio_exit_kernel),
50 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
55 static bool core_reg_offset_is_vreg(u64 off)
57 return off >= KVM_REG_ARM_CORE_REG(fp_regs.vregs) &&
58 off < KVM_REG_ARM_CORE_REG(fp_regs.fpsr);
61 static u64 core_reg_offset_from_id(u64 id)
63 return id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE);
66 static int core_reg_size_from_offset(const struct kvm_vcpu *vcpu, u64 off)
71 case KVM_REG_ARM_CORE_REG(regs.regs[0]) ...
72 KVM_REG_ARM_CORE_REG(regs.regs[30]):
73 case KVM_REG_ARM_CORE_REG(regs.sp):
74 case KVM_REG_ARM_CORE_REG(regs.pc):
75 case KVM_REG_ARM_CORE_REG(regs.pstate):
76 case KVM_REG_ARM_CORE_REG(sp_el1):
77 case KVM_REG_ARM_CORE_REG(elr_el1):
78 case KVM_REG_ARM_CORE_REG(spsr[0]) ...
79 KVM_REG_ARM_CORE_REG(spsr[KVM_NR_SPSR - 1]):
83 case KVM_REG_ARM_CORE_REG(fp_regs.vregs[0]) ...
84 KVM_REG_ARM_CORE_REG(fp_regs.vregs[31]):
85 size = sizeof(__uint128_t);
88 case KVM_REG_ARM_CORE_REG(fp_regs.fpsr):
89 case KVM_REG_ARM_CORE_REG(fp_regs.fpcr):
97 if (!IS_ALIGNED(off, size / sizeof(__u32)))
101 * The KVM_REG_ARM64_SVE regs must be used instead of
102 * KVM_REG_ARM_CORE for accessing the FPSIMD V-registers on
105 if (vcpu_has_sve(vcpu) && core_reg_offset_is_vreg(off))
111 static int validate_core_offset(const struct kvm_vcpu *vcpu,
112 const struct kvm_one_reg *reg)
114 u64 off = core_reg_offset_from_id(reg->id);
115 int size = core_reg_size_from_offset(vcpu, off);
120 if (KVM_REG_SIZE(reg->id) != size)
126 static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
129 * Because the kvm_regs structure is a mix of 32, 64 and
130 * 128bit fields, we index it as if it was a 32bit
131 * array. Hence below, nr_regs is the number of entries, and
132 * off the index in the "array".
134 __u32 __user *uaddr = (__u32 __user *)(unsigned long)reg->addr;
135 struct kvm_regs *regs = vcpu_gp_regs(vcpu);
136 int nr_regs = sizeof(*regs) / sizeof(__u32);
139 /* Our ID is an index into the kvm_regs struct. */
140 off = core_reg_offset_from_id(reg->id);
141 if (off >= nr_regs ||
142 (off + (KVM_REG_SIZE(reg->id) / sizeof(__u32))) >= nr_regs)
145 if (validate_core_offset(vcpu, reg))
148 if (copy_to_user(uaddr, ((u32 *)regs) + off, KVM_REG_SIZE(reg->id)))
154 static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
156 __u32 __user *uaddr = (__u32 __user *)(unsigned long)reg->addr;
157 struct kvm_regs *regs = vcpu_gp_regs(vcpu);
158 int nr_regs = sizeof(*regs) / sizeof(__u32);
164 /* Our ID is an index into the kvm_regs struct. */
165 off = core_reg_offset_from_id(reg->id);
166 if (off >= nr_regs ||
167 (off + (KVM_REG_SIZE(reg->id) / sizeof(__u32))) >= nr_regs)
170 if (validate_core_offset(vcpu, reg))
173 if (KVM_REG_SIZE(reg->id) > sizeof(tmp))
176 if (copy_from_user(valp, uaddr, KVM_REG_SIZE(reg->id))) {
181 if (off == KVM_REG_ARM_CORE_REG(regs.pstate)) {
182 u64 mode = (*(u64 *)valp) & PSR_AA32_MODE_MASK;
184 case PSR_AA32_MODE_USR:
185 if (!system_supports_32bit_el0())
188 case PSR_AA32_MODE_FIQ:
189 case PSR_AA32_MODE_IRQ:
190 case PSR_AA32_MODE_SVC:
191 case PSR_AA32_MODE_ABT:
192 case PSR_AA32_MODE_UND:
193 if (!vcpu_el1_is_32bit(vcpu))
199 if (vcpu_el1_is_32bit(vcpu))
208 memcpy((u32 *)regs + off, valp, KVM_REG_SIZE(reg->id));
213 #define vq_word(vq) (((vq) - SVE_VQ_MIN) / 64)
214 #define vq_mask(vq) ((u64)1 << ((vq) - SVE_VQ_MIN) % 64)
215 #define vq_present(vqs, vq) (!!((vqs)[vq_word(vq)] & vq_mask(vq)))
217 static int get_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
219 unsigned int max_vq, vq;
220 u64 vqs[KVM_ARM64_SVE_VLS_WORDS];
222 if (!vcpu_has_sve(vcpu))
225 if (WARN_ON(!sve_vl_valid(vcpu->arch.sve_max_vl)))
228 memset(vqs, 0, sizeof(vqs));
230 max_vq = sve_vq_from_vl(vcpu->arch.sve_max_vl);
231 for (vq = SVE_VQ_MIN; vq <= max_vq; ++vq)
232 if (sve_vq_available(vq))
233 vqs[vq_word(vq)] |= vq_mask(vq);
235 if (copy_to_user((void __user *)reg->addr, vqs, sizeof(vqs)))
241 static int set_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
243 unsigned int max_vq, vq;
244 u64 vqs[KVM_ARM64_SVE_VLS_WORDS];
246 if (!vcpu_has_sve(vcpu))
249 if (kvm_arm_vcpu_sve_finalized(vcpu))
250 return -EPERM; /* too late! */
252 if (WARN_ON(vcpu->arch.sve_state))
255 if (copy_from_user(vqs, (const void __user *)reg->addr, sizeof(vqs)))
259 for (vq = SVE_VQ_MIN; vq <= SVE_VQ_MAX; ++vq)
260 if (vq_present(vqs, vq))
263 if (max_vq > sve_vq_from_vl(kvm_sve_max_vl))
267 * Vector lengths supported by the host can't currently be
268 * hidden from the guest individually: instead we can only set a
269 * maxmium via ZCR_EL2.LEN. So, make sure the available vector
270 * lengths match the set requested exactly up to the requested
273 for (vq = SVE_VQ_MIN; vq <= max_vq; ++vq)
274 if (vq_present(vqs, vq) != sve_vq_available(vq))
277 /* Can't run with no vector lengths at all: */
278 if (max_vq < SVE_VQ_MIN)
281 /* vcpu->arch.sve_state will be alloc'd by kvm_vcpu_finalize_sve() */
282 vcpu->arch.sve_max_vl = sve_vl_from_vq(max_vq);
287 #define SVE_REG_SLICE_SHIFT 0
288 #define SVE_REG_SLICE_BITS 5
289 #define SVE_REG_ID_SHIFT (SVE_REG_SLICE_SHIFT + SVE_REG_SLICE_BITS)
290 #define SVE_REG_ID_BITS 5
292 #define SVE_REG_SLICE_MASK \
293 GENMASK(SVE_REG_SLICE_SHIFT + SVE_REG_SLICE_BITS - 1, \
295 #define SVE_REG_ID_MASK \
296 GENMASK(SVE_REG_ID_SHIFT + SVE_REG_ID_BITS - 1, SVE_REG_ID_SHIFT)
298 #define SVE_NUM_SLICES (1 << SVE_REG_SLICE_BITS)
300 #define KVM_SVE_ZREG_SIZE KVM_REG_SIZE(KVM_REG_ARM64_SVE_ZREG(0, 0))
301 #define KVM_SVE_PREG_SIZE KVM_REG_SIZE(KVM_REG_ARM64_SVE_PREG(0, 0))
304 * Number of register slices required to cover each whole SVE register.
305 * NOTE: Only the first slice every exists, for now.
306 * If you are tempted to modify this, you must also rework sve_reg_to_region()
309 #define vcpu_sve_slices(vcpu) 1
311 /* Bounds of a single SVE register slice within vcpu->arch.sve_state */
312 struct sve_state_reg_region {
313 unsigned int koffset; /* offset into sve_state in kernel memory */
314 unsigned int klen; /* length in kernel memory */
315 unsigned int upad; /* extra trailing padding in user memory */
319 * Validate SVE register ID and get sanitised bounds for user/kernel SVE
322 static int sve_reg_to_region(struct sve_state_reg_region *region,
323 struct kvm_vcpu *vcpu,
324 const struct kvm_one_reg *reg)
326 /* reg ID ranges for Z- registers */
327 const u64 zreg_id_min = KVM_REG_ARM64_SVE_ZREG(0, 0);
328 const u64 zreg_id_max = KVM_REG_ARM64_SVE_ZREG(SVE_NUM_ZREGS - 1,
331 /* reg ID ranges for P- registers and FFR (which are contiguous) */
332 const u64 preg_id_min = KVM_REG_ARM64_SVE_PREG(0, 0);
333 const u64 preg_id_max = KVM_REG_ARM64_SVE_FFR(SVE_NUM_SLICES - 1);
336 unsigned int reg_num;
338 unsigned int reqoffset, reqlen; /* User-requested offset and length */
339 unsigned int maxlen; /* Maxmimum permitted length */
341 size_t sve_state_size;
343 const u64 last_preg_id = KVM_REG_ARM64_SVE_PREG(SVE_NUM_PREGS - 1,
346 /* Verify that the P-regs and FFR really do have contiguous IDs: */
347 BUILD_BUG_ON(KVM_REG_ARM64_SVE_FFR(0) != last_preg_id + 1);
349 /* Verify that we match the UAPI header: */
350 BUILD_BUG_ON(SVE_NUM_SLICES != KVM_ARM64_SVE_MAX_SLICES);
352 reg_num = (reg->id & SVE_REG_ID_MASK) >> SVE_REG_ID_SHIFT;
354 if (reg->id >= zreg_id_min && reg->id <= zreg_id_max) {
355 if (!vcpu_has_sve(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0)
358 vq = sve_vq_from_vl(vcpu->arch.sve_max_vl);
360 reqoffset = SVE_SIG_ZREG_OFFSET(vq, reg_num) -
362 reqlen = KVM_SVE_ZREG_SIZE;
363 maxlen = SVE_SIG_ZREG_SIZE(vq);
364 } else if (reg->id >= preg_id_min && reg->id <= preg_id_max) {
365 if (!vcpu_has_sve(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0)
368 vq = sve_vq_from_vl(vcpu->arch.sve_max_vl);
370 reqoffset = SVE_SIG_PREG_OFFSET(vq, reg_num) -
372 reqlen = KVM_SVE_PREG_SIZE;
373 maxlen = SVE_SIG_PREG_SIZE(vq);
378 sve_state_size = vcpu_sve_state_size(vcpu);
379 if (WARN_ON(!sve_state_size))
382 region->koffset = array_index_nospec(reqoffset, sve_state_size);
383 region->klen = min(maxlen, reqlen);
384 region->upad = reqlen - region->klen;
389 static int get_sve_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
392 struct sve_state_reg_region region;
393 char __user *uptr = (char __user *)reg->addr;
395 /* Handle the KVM_REG_ARM64_SVE_VLS pseudo-reg as a special case: */
396 if (reg->id == KVM_REG_ARM64_SVE_VLS)
397 return get_sve_vls(vcpu, reg);
399 /* Try to interpret reg ID as an architectural SVE register... */
400 ret = sve_reg_to_region(®ion, vcpu, reg);
404 if (!kvm_arm_vcpu_sve_finalized(vcpu))
407 if (copy_to_user(uptr, vcpu->arch.sve_state + region.koffset,
409 clear_user(uptr + region.klen, region.upad))
415 static int set_sve_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
418 struct sve_state_reg_region region;
419 const char __user *uptr = (const char __user *)reg->addr;
421 /* Handle the KVM_REG_ARM64_SVE_VLS pseudo-reg as a special case: */
422 if (reg->id == KVM_REG_ARM64_SVE_VLS)
423 return set_sve_vls(vcpu, reg);
425 /* Try to interpret reg ID as an architectural SVE register... */
426 ret = sve_reg_to_region(®ion, vcpu, reg);
430 if (!kvm_arm_vcpu_sve_finalized(vcpu))
433 if (copy_from_user(vcpu->arch.sve_state + region.koffset, uptr,
440 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
445 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
450 static int copy_core_reg_indices(const struct kvm_vcpu *vcpu,
451 u64 __user *uindices)
456 for (i = 0; i < sizeof(struct kvm_regs) / sizeof(__u32); i++) {
457 u64 reg = KVM_REG_ARM64 | KVM_REG_ARM_CORE | i;
458 int size = core_reg_size_from_offset(vcpu, i);
465 reg |= KVM_REG_SIZE_U32;
469 reg |= KVM_REG_SIZE_U64;
472 case sizeof(__uint128_t):
473 reg |= KVM_REG_SIZE_U128;
482 if (put_user(reg, uindices))
493 static unsigned long num_core_regs(const struct kvm_vcpu *vcpu)
495 return copy_core_reg_indices(vcpu, NULL);
499 * ARM64 versions of the TIMER registers, always available on arm64
502 #define NUM_TIMER_REGS 3
504 static bool is_timer_reg(u64 index)
507 case KVM_REG_ARM_TIMER_CTL:
508 case KVM_REG_ARM_TIMER_CNT:
509 case KVM_REG_ARM_TIMER_CVAL:
515 static int copy_timer_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
517 if (put_user(KVM_REG_ARM_TIMER_CTL, uindices))
520 if (put_user(KVM_REG_ARM_TIMER_CNT, uindices))
523 if (put_user(KVM_REG_ARM_TIMER_CVAL, uindices))
529 static int set_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
531 void __user *uaddr = (void __user *)(long)reg->addr;
535 ret = copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id));
539 return kvm_arm_timer_set_reg(vcpu, reg->id, val);
542 static int get_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
544 void __user *uaddr = (void __user *)(long)reg->addr;
547 val = kvm_arm_timer_get_reg(vcpu, reg->id);
548 return copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id)) ? -EFAULT : 0;
551 static unsigned long num_sve_regs(const struct kvm_vcpu *vcpu)
553 const unsigned int slices = vcpu_sve_slices(vcpu);
555 if (!vcpu_has_sve(vcpu))
558 /* Policed by KVM_GET_REG_LIST: */
559 WARN_ON(!kvm_arm_vcpu_sve_finalized(vcpu));
561 return slices * (SVE_NUM_PREGS + SVE_NUM_ZREGS + 1 /* FFR */)
562 + 1; /* KVM_REG_ARM64_SVE_VLS */
565 static int copy_sve_reg_indices(const struct kvm_vcpu *vcpu,
566 u64 __user *uindices)
568 const unsigned int slices = vcpu_sve_slices(vcpu);
573 if (!vcpu_has_sve(vcpu))
576 /* Policed by KVM_GET_REG_LIST: */
577 WARN_ON(!kvm_arm_vcpu_sve_finalized(vcpu));
580 * Enumerate this first, so that userspace can save/restore in
581 * the order reported by KVM_GET_REG_LIST:
583 reg = KVM_REG_ARM64_SVE_VLS;
584 if (put_user(reg, uindices++))
588 for (i = 0; i < slices; i++) {
589 for (n = 0; n < SVE_NUM_ZREGS; n++) {
590 reg = KVM_REG_ARM64_SVE_ZREG(n, i);
591 if (put_user(reg, uindices++))
596 for (n = 0; n < SVE_NUM_PREGS; n++) {
597 reg = KVM_REG_ARM64_SVE_PREG(n, i);
598 if (put_user(reg, uindices++))
603 reg = KVM_REG_ARM64_SVE_FFR(i);
604 if (put_user(reg, uindices++))
613 * kvm_arm_num_regs - how many registers do we present via KVM_GET_ONE_REG
615 * This is for all registers.
617 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu)
619 unsigned long res = 0;
621 res += num_core_regs(vcpu);
622 res += num_sve_regs(vcpu);
623 res += kvm_arm_num_sys_reg_descs(vcpu);
624 res += kvm_arm_get_fw_num_regs(vcpu);
625 res += NUM_TIMER_REGS;
631 * kvm_arm_copy_reg_indices - get indices of all registers.
633 * We do core registers right here, then we append system regs.
635 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
639 ret = copy_core_reg_indices(vcpu, uindices);
644 ret = copy_sve_reg_indices(vcpu, uindices);
649 ret = kvm_arm_copy_fw_reg_indices(vcpu, uindices);
652 uindices += kvm_arm_get_fw_num_regs(vcpu);
654 ret = copy_timer_indices(vcpu, uindices);
657 uindices += NUM_TIMER_REGS;
659 return kvm_arm_copy_sys_reg_indices(vcpu, uindices);
662 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
664 /* We currently use nothing arch-specific in upper 32 bits */
665 if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM64 >> 32)
668 switch (reg->id & KVM_REG_ARM_COPROC_MASK) {
669 case KVM_REG_ARM_CORE: return get_core_reg(vcpu, reg);
670 case KVM_REG_ARM_FW: return kvm_arm_get_fw_reg(vcpu, reg);
671 case KVM_REG_ARM64_SVE: return get_sve_reg(vcpu, reg);
674 if (is_timer_reg(reg->id))
675 return get_timer_reg(vcpu, reg);
677 return kvm_arm_sys_reg_get_reg(vcpu, reg);
680 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
682 /* We currently use nothing arch-specific in upper 32 bits */
683 if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM64 >> 32)
686 switch (reg->id & KVM_REG_ARM_COPROC_MASK) {
687 case KVM_REG_ARM_CORE: return set_core_reg(vcpu, reg);
688 case KVM_REG_ARM_FW: return kvm_arm_set_fw_reg(vcpu, reg);
689 case KVM_REG_ARM64_SVE: return set_sve_reg(vcpu, reg);
692 if (is_timer_reg(reg->id))
693 return set_timer_reg(vcpu, reg);
695 return kvm_arm_sys_reg_set_reg(vcpu, reg);
698 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
699 struct kvm_sregs *sregs)
704 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
705 struct kvm_sregs *sregs)
710 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
711 struct kvm_vcpu_events *events)
713 events->exception.serror_pending = !!(vcpu->arch.hcr_el2 & HCR_VSE);
714 events->exception.serror_has_esr = cpus_have_const_cap(ARM64_HAS_RAS_EXTN);
716 if (events->exception.serror_pending && events->exception.serror_has_esr)
717 events->exception.serror_esr = vcpu_get_vsesr(vcpu);
720 * We never return a pending ext_dabt here because we deliver it to
721 * the virtual CPU directly when setting the event and it's no longer
722 * 'pending' at this point.
728 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
729 struct kvm_vcpu_events *events)
731 bool serror_pending = events->exception.serror_pending;
732 bool has_esr = events->exception.serror_has_esr;
733 bool ext_dabt_pending = events->exception.ext_dabt_pending;
735 if (serror_pending && has_esr) {
736 if (!cpus_have_const_cap(ARM64_HAS_RAS_EXTN))
739 if (!((events->exception.serror_esr) & ~ESR_ELx_ISS_MASK))
740 kvm_set_sei_esr(vcpu, events->exception.serror_esr);
743 } else if (serror_pending) {
744 kvm_inject_vabt(vcpu);
747 if (ext_dabt_pending)
748 kvm_inject_dabt(vcpu, kvm_vcpu_get_hfar(vcpu));
753 int __attribute_const__ kvm_target_cpu(void)
755 unsigned long implementor = read_cpuid_implementor();
756 unsigned long part_number = read_cpuid_part_number();
758 switch (implementor) {
759 case ARM_CPU_IMP_ARM:
760 switch (part_number) {
761 case ARM_CPU_PART_AEM_V8:
762 return KVM_ARM_TARGET_AEM_V8;
763 case ARM_CPU_PART_FOUNDATION:
764 return KVM_ARM_TARGET_FOUNDATION_V8;
765 case ARM_CPU_PART_CORTEX_A53:
766 return KVM_ARM_TARGET_CORTEX_A53;
767 case ARM_CPU_PART_CORTEX_A57:
768 return KVM_ARM_TARGET_CORTEX_A57;
771 case ARM_CPU_IMP_APM:
772 switch (part_number) {
773 case APM_CPU_PART_POTENZA:
774 return KVM_ARM_TARGET_XGENE_POTENZA;
779 /* Return a default generic target */
780 return KVM_ARM_TARGET_GENERIC_V8;
783 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init)
785 int target = kvm_target_cpu();
790 memset(init, 0, sizeof(*init));
793 * For now, we don't return any features.
794 * In future, we might use features to return target
795 * specific features available for the preferred
798 init->target = (__u32)target;
803 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
808 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
813 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
814 struct kvm_translation *tr)
819 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \
820 KVM_GUESTDBG_USE_SW_BP | \
821 KVM_GUESTDBG_USE_HW | \
822 KVM_GUESTDBG_SINGLESTEP)
825 * kvm_arch_vcpu_ioctl_set_guest_debug - set up guest debugging
826 * @kvm: pointer to the KVM struct
827 * @kvm_guest_debug: the ioctl data buffer
829 * This sets up and enables the VM for guest debugging. Userspace
830 * passes in a control flag to enable different debug types and
831 * potentially other architecture specific information in the rest of
834 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
835 struct kvm_guest_debug *dbg)
839 trace_kvm_set_guest_debug(vcpu, dbg->control);
841 if (dbg->control & ~KVM_GUESTDBG_VALID_MASK) {
846 if (dbg->control & KVM_GUESTDBG_ENABLE) {
847 vcpu->guest_debug = dbg->control;
849 /* Hardware assisted Break and Watch points */
850 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW) {
851 vcpu->arch.external_debug_state = dbg->arch;
855 /* If not enabled clear all flags */
856 vcpu->guest_debug = 0;
863 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
864 struct kvm_device_attr *attr)
868 switch (attr->group) {
869 case KVM_ARM_VCPU_PMU_V3_CTRL:
870 ret = kvm_arm_pmu_v3_set_attr(vcpu, attr);
872 case KVM_ARM_VCPU_TIMER_CTRL:
873 ret = kvm_arm_timer_set_attr(vcpu, attr);
875 case KVM_ARM_VCPU_PVTIME_CTRL:
876 ret = kvm_arm_pvtime_set_attr(vcpu, attr);
886 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
887 struct kvm_device_attr *attr)
891 switch (attr->group) {
892 case KVM_ARM_VCPU_PMU_V3_CTRL:
893 ret = kvm_arm_pmu_v3_get_attr(vcpu, attr);
895 case KVM_ARM_VCPU_TIMER_CTRL:
896 ret = kvm_arm_timer_get_attr(vcpu, attr);
898 case KVM_ARM_VCPU_PVTIME_CTRL:
899 ret = kvm_arm_pvtime_get_attr(vcpu, attr);
909 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
910 struct kvm_device_attr *attr)
914 switch (attr->group) {
915 case KVM_ARM_VCPU_PMU_V3_CTRL:
916 ret = kvm_arm_pmu_v3_has_attr(vcpu, attr);
918 case KVM_ARM_VCPU_TIMER_CTRL:
919 ret = kvm_arm_timer_has_attr(vcpu, attr);
921 case KVM_ARM_VCPU_PVTIME_CTRL:
922 ret = kvm_arm_pvtime_has_attr(vcpu, attr);