2 * SWIOTLB-based DMA API implementation
4 * Copyright (C) 2012 ARM Ltd.
5 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/gfp.h>
21 #include <linux/acpi.h>
22 #include <linux/memblock.h>
23 #include <linux/cache.h>
24 #include <linux/export.h>
25 #include <linux/slab.h>
26 #include <linux/genalloc.h>
27 #include <linux/dma-direct.h>
28 #include <linux/dma-noncoherent.h>
29 #include <linux/dma-contiguous.h>
30 #include <linux/vmalloc.h>
31 #include <linux/swiotlb.h>
32 #include <linux/pci.h>
34 #include <asm/cacheflush.h>
36 static struct gen_pool *atomic_pool __ro_after_init;
38 #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
39 static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE;
41 static int __init early_coherent_pool(char *p)
43 atomic_pool_size = memparse(p, &p);
46 early_param("coherent_pool", early_coherent_pool);
48 static void *__alloc_from_pool(size_t size, struct page **ret_page, gfp_t flags)
54 WARN(1, "coherent pool not initialised!\n");
58 val = gen_pool_alloc(atomic_pool, size);
60 phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val);
62 *ret_page = phys_to_page(phys);
70 static bool __in_atomic_pool(void *start, size_t size)
72 return addr_in_gen_pool(atomic_pool, (unsigned long)start, size);
75 static int __free_from_pool(void *start, size_t size)
77 if (!__in_atomic_pool(start, size))
80 gen_pool_free(atomic_pool, (unsigned long)start, size);
85 void *arch_dma_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle,
86 gfp_t flags, unsigned long attrs)
89 void *ptr, *coherent_ptr;
90 pgprot_t prot = pgprot_writecombine(PAGE_KERNEL);
92 size = PAGE_ALIGN(size);
94 if (!gfpflags_allow_blocking(flags)) {
95 struct page *page = NULL;
96 void *addr = __alloc_from_pool(size, &page, flags);
99 *dma_handle = phys_to_dma(dev, page_to_phys(page));
104 ptr = dma_direct_alloc_pages(dev, size, dma_handle, flags, attrs);
108 /* remove any dirty cache lines on the kernel alias */
109 __dma_flush_area(ptr, size);
111 /* create a coherent mapping */
112 page = virt_to_page(ptr);
113 coherent_ptr = dma_common_contiguous_remap(page, size, VM_USERMAP,
114 prot, __builtin_return_address(0));
121 dma_direct_free_pages(dev, size, ptr, *dma_handle, attrs);
126 void arch_dma_free(struct device *dev, size_t size, void *vaddr,
127 dma_addr_t dma_handle, unsigned long attrs)
129 if (!__free_from_pool(vaddr, PAGE_ALIGN(size))) {
130 void *kaddr = phys_to_virt(dma_to_phys(dev, dma_handle));
133 dma_direct_free_pages(dev, size, kaddr, dma_handle, attrs);
137 long arch_dma_coherent_to_pfn(struct device *dev, void *cpu_addr,
140 return __phys_to_pfn(dma_to_phys(dev, dma_addr));
143 pgprot_t arch_dma_mmap_pgprot(struct device *dev, pgprot_t prot,
146 if (!dev_is_dma_coherent(dev) || (attrs & DMA_ATTR_WRITE_COMBINE))
147 return pgprot_writecombine(prot);
151 void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr,
152 size_t size, enum dma_data_direction dir)
154 __dma_map_area(phys_to_virt(paddr), size, dir);
157 void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr,
158 size_t size, enum dma_data_direction dir)
160 __dma_unmap_area(phys_to_virt(paddr), size, dir);
163 #ifdef CONFIG_IOMMU_DMA
164 static int __swiotlb_get_sgtable_page(struct sg_table *sgt,
165 struct page *page, size_t size)
167 int ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
170 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
175 static int __swiotlb_mmap_pfn(struct vm_area_struct *vma,
176 unsigned long pfn, size_t size)
179 unsigned long nr_vma_pages = vma_pages(vma);
180 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
181 unsigned long off = vma->vm_pgoff;
183 if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
184 ret = remap_pfn_range(vma, vma->vm_start,
186 vma->vm_end - vma->vm_start,
192 #endif /* CONFIG_IOMMU_DMA */
194 static int __init atomic_pool_init(void)
196 pgprot_t prot = __pgprot(PROT_NORMAL_NC);
197 unsigned long nr_pages = atomic_pool_size >> PAGE_SHIFT;
200 unsigned int pool_size_order = get_order(atomic_pool_size);
202 if (dev_get_cma_area(NULL))
203 page = dma_alloc_from_contiguous(NULL, nr_pages,
204 pool_size_order, false);
206 page = alloc_pages(GFP_DMA32, pool_size_order);
210 void *page_addr = page_address(page);
212 memset(page_addr, 0, atomic_pool_size);
213 __dma_flush_area(page_addr, atomic_pool_size);
215 atomic_pool = gen_pool_create(PAGE_SHIFT, -1);
219 addr = dma_common_contiguous_remap(page, atomic_pool_size,
220 VM_USERMAP, prot, atomic_pool_init);
223 goto destroy_genpool;
225 ret = gen_pool_add_virt(atomic_pool, (unsigned long)addr,
227 atomic_pool_size, -1);
231 gen_pool_set_algo(atomic_pool,
232 gen_pool_first_fit_order_align,
235 pr_info("DMA: preallocated %zu KiB pool for atomic allocations\n",
236 atomic_pool_size / 1024);
242 dma_common_free_remap(addr, atomic_pool_size, VM_USERMAP);
244 gen_pool_destroy(atomic_pool);
247 if (!dma_release_from_contiguous(NULL, page, nr_pages))
248 __free_pages(page, pool_size_order);
250 pr_err("DMA: failed to allocate %zu KiB pool for atomic coherent allocation\n",
251 atomic_pool_size / 1024);
255 /********************************************
256 * The following APIs are for dummy DMA ops *
257 ********************************************/
259 static void *__dummy_alloc(struct device *dev, size_t size,
260 dma_addr_t *dma_handle, gfp_t flags,
266 static void __dummy_free(struct device *dev, size_t size,
267 void *vaddr, dma_addr_t dma_handle,
272 static int __dummy_mmap(struct device *dev,
273 struct vm_area_struct *vma,
274 void *cpu_addr, dma_addr_t dma_addr, size_t size,
280 static dma_addr_t __dummy_map_page(struct device *dev, struct page *page,
281 unsigned long offset, size_t size,
282 enum dma_data_direction dir,
288 static void __dummy_unmap_page(struct device *dev, dma_addr_t dev_addr,
289 size_t size, enum dma_data_direction dir,
294 static int __dummy_map_sg(struct device *dev, struct scatterlist *sgl,
295 int nelems, enum dma_data_direction dir,
301 static void __dummy_unmap_sg(struct device *dev,
302 struct scatterlist *sgl, int nelems,
303 enum dma_data_direction dir,
308 static void __dummy_sync_single(struct device *dev,
309 dma_addr_t dev_addr, size_t size,
310 enum dma_data_direction dir)
314 static void __dummy_sync_sg(struct device *dev,
315 struct scatterlist *sgl, int nelems,
316 enum dma_data_direction dir)
320 static int __dummy_mapping_error(struct device *hwdev, dma_addr_t dma_addr)
325 static int __dummy_dma_supported(struct device *hwdev, u64 mask)
330 const struct dma_map_ops dummy_dma_ops = {
331 .alloc = __dummy_alloc,
332 .free = __dummy_free,
333 .mmap = __dummy_mmap,
334 .map_page = __dummy_map_page,
335 .unmap_page = __dummy_unmap_page,
336 .map_sg = __dummy_map_sg,
337 .unmap_sg = __dummy_unmap_sg,
338 .sync_single_for_cpu = __dummy_sync_single,
339 .sync_single_for_device = __dummy_sync_single,
340 .sync_sg_for_cpu = __dummy_sync_sg,
341 .sync_sg_for_device = __dummy_sync_sg,
342 .mapping_error = __dummy_mapping_error,
343 .dma_supported = __dummy_dma_supported,
345 EXPORT_SYMBOL(dummy_dma_ops);
347 static int __init arm64_dma_init(void)
349 WARN_TAINT(ARCH_DMA_MINALIGN < cache_line_size(),
350 TAINT_CPU_OUT_OF_SPEC,
351 "ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)",
352 ARCH_DMA_MINALIGN, cache_line_size());
354 return atomic_pool_init();
356 arch_initcall(arm64_dma_init);
358 #ifdef CONFIG_IOMMU_DMA
359 #include <linux/dma-iommu.h>
360 #include <linux/platform_device.h>
361 #include <linux/amba/bus.h>
363 /* Thankfully, all cache ops are by VA so we can ignore phys here */
364 static void flush_page(struct device *dev, const void *virt, phys_addr_t phys)
366 __dma_flush_area(virt, PAGE_SIZE);
369 static void *__iommu_alloc_attrs(struct device *dev, size_t size,
370 dma_addr_t *handle, gfp_t gfp,
373 bool coherent = dev_is_dma_coherent(dev);
374 int ioprot = dma_info_to_prot(DMA_BIDIRECTIONAL, coherent, attrs);
375 size_t iosize = size;
378 if (WARN(!dev, "cannot create IOMMU mapping for unknown device\n"))
381 size = PAGE_ALIGN(size);
384 * Some drivers rely on this, and we probably don't want the
385 * possibility of stale kernel data being read by devices anyway.
389 if (!gfpflags_allow_blocking(gfp)) {
392 * In atomic context we can't remap anything, so we'll only
393 * get the virtually contiguous buffer we need by way of a
394 * physically contiguous allocation.
397 page = alloc_pages(gfp, get_order(size));
398 addr = page ? page_address(page) : NULL;
400 addr = __alloc_from_pool(size, &page, gfp);
405 *handle = iommu_dma_map_page(dev, page, 0, iosize, ioprot);
406 if (iommu_dma_mapping_error(dev, *handle)) {
408 __free_pages(page, get_order(size));
410 __free_from_pool(addr, size);
413 } else if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) {
414 pgprot_t prot = arch_dma_mmap_pgprot(dev, PAGE_KERNEL, attrs);
417 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
418 get_order(size), gfp & __GFP_NOWARN);
422 *handle = iommu_dma_map_page(dev, page, 0, iosize, ioprot);
423 if (iommu_dma_mapping_error(dev, *handle)) {
424 dma_release_from_contiguous(dev, page,
428 addr = dma_common_contiguous_remap(page, size, VM_USERMAP,
430 __builtin_return_address(0));
433 __dma_flush_area(page_to_virt(page), iosize);
434 memset(addr, 0, size);
436 iommu_dma_unmap_page(dev, *handle, iosize, 0, attrs);
437 dma_release_from_contiguous(dev, page,
441 pgprot_t prot = arch_dma_mmap_pgprot(dev, PAGE_KERNEL, attrs);
444 pages = iommu_dma_alloc(dev, iosize, gfp, attrs, ioprot,
449 addr = dma_common_pages_remap(pages, size, VM_USERMAP, prot,
450 __builtin_return_address(0));
452 iommu_dma_free(dev, pages, iosize, handle);
457 static void __iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
458 dma_addr_t handle, unsigned long attrs)
460 size_t iosize = size;
462 size = PAGE_ALIGN(size);
464 * @cpu_addr will be one of 4 things depending on how it was allocated:
465 * - A remapped array of pages for contiguous allocations.
466 * - A remapped array of pages from iommu_dma_alloc(), for all
467 * non-atomic allocations.
468 * - A non-cacheable alias from the atomic pool, for atomic
469 * allocations by non-coherent devices.
470 * - A normal lowmem address, for atomic allocations by
472 * Hence how dodgy the below logic looks...
474 if (__in_atomic_pool(cpu_addr, size)) {
475 iommu_dma_unmap_page(dev, handle, iosize, 0, 0);
476 __free_from_pool(cpu_addr, size);
477 } else if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) {
478 struct page *page = vmalloc_to_page(cpu_addr);
480 iommu_dma_unmap_page(dev, handle, iosize, 0, attrs);
481 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
482 dma_common_free_remap(cpu_addr, size, VM_USERMAP);
483 } else if (is_vmalloc_addr(cpu_addr)){
484 struct vm_struct *area = find_vm_area(cpu_addr);
486 if (WARN_ON(!area || !area->pages))
488 iommu_dma_free(dev, area->pages, iosize, &handle);
489 dma_common_free_remap(cpu_addr, size, VM_USERMAP);
491 iommu_dma_unmap_page(dev, handle, iosize, 0, 0);
492 __free_pages(virt_to_page(cpu_addr), get_order(size));
496 static int __iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
497 void *cpu_addr, dma_addr_t dma_addr, size_t size,
500 struct vm_struct *area;
503 vma->vm_page_prot = arch_dma_mmap_pgprot(dev, vma->vm_page_prot, attrs);
505 if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
508 if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) {
510 * DMA_ATTR_FORCE_CONTIGUOUS allocations are always remapped,
511 * hence in the vmalloc space.
513 unsigned long pfn = vmalloc_to_pfn(cpu_addr);
514 return __swiotlb_mmap_pfn(vma, pfn, size);
517 area = find_vm_area(cpu_addr);
518 if (WARN_ON(!area || !area->pages))
521 return iommu_dma_mmap(area->pages, size, vma);
524 static int __iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
525 void *cpu_addr, dma_addr_t dma_addr,
526 size_t size, unsigned long attrs)
528 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
529 struct vm_struct *area = find_vm_area(cpu_addr);
531 if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) {
533 * DMA_ATTR_FORCE_CONTIGUOUS allocations are always remapped,
534 * hence in the vmalloc space.
536 struct page *page = vmalloc_to_page(cpu_addr);
537 return __swiotlb_get_sgtable_page(sgt, page, size);
540 if (WARN_ON(!area || !area->pages))
543 return sg_alloc_table_from_pages(sgt, area->pages, count, 0, size,
547 static void __iommu_sync_single_for_cpu(struct device *dev,
548 dma_addr_t dev_addr, size_t size,
549 enum dma_data_direction dir)
553 if (dev_is_dma_coherent(dev))
556 phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dev_addr);
557 arch_sync_dma_for_cpu(dev, phys, size, dir);
560 static void __iommu_sync_single_for_device(struct device *dev,
561 dma_addr_t dev_addr, size_t size,
562 enum dma_data_direction dir)
566 if (dev_is_dma_coherent(dev))
569 phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dev_addr);
570 arch_sync_dma_for_device(dev, phys, size, dir);
573 static dma_addr_t __iommu_map_page(struct device *dev, struct page *page,
574 unsigned long offset, size_t size,
575 enum dma_data_direction dir,
578 bool coherent = dev_is_dma_coherent(dev);
579 int prot = dma_info_to_prot(dir, coherent, attrs);
580 dma_addr_t dev_addr = iommu_dma_map_page(dev, page, offset, size, prot);
582 if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC) &&
583 !iommu_dma_mapping_error(dev, dev_addr))
584 __dma_map_area(page_address(page) + offset, size, dir);
589 static void __iommu_unmap_page(struct device *dev, dma_addr_t dev_addr,
590 size_t size, enum dma_data_direction dir,
593 if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
594 __iommu_sync_single_for_cpu(dev, dev_addr, size, dir);
596 iommu_dma_unmap_page(dev, dev_addr, size, dir, attrs);
599 static void __iommu_sync_sg_for_cpu(struct device *dev,
600 struct scatterlist *sgl, int nelems,
601 enum dma_data_direction dir)
603 struct scatterlist *sg;
606 if (dev_is_dma_coherent(dev))
609 for_each_sg(sgl, sg, nelems, i)
610 arch_sync_dma_for_cpu(dev, sg_phys(sg), sg->length, dir);
613 static void __iommu_sync_sg_for_device(struct device *dev,
614 struct scatterlist *sgl, int nelems,
615 enum dma_data_direction dir)
617 struct scatterlist *sg;
620 if (dev_is_dma_coherent(dev))
623 for_each_sg(sgl, sg, nelems, i)
624 arch_sync_dma_for_device(dev, sg_phys(sg), sg->length, dir);
627 static int __iommu_map_sg_attrs(struct device *dev, struct scatterlist *sgl,
628 int nelems, enum dma_data_direction dir,
631 bool coherent = dev_is_dma_coherent(dev);
633 if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
634 __iommu_sync_sg_for_device(dev, sgl, nelems, dir);
636 return iommu_dma_map_sg(dev, sgl, nelems,
637 dma_info_to_prot(dir, coherent, attrs));
640 static void __iommu_unmap_sg_attrs(struct device *dev,
641 struct scatterlist *sgl, int nelems,
642 enum dma_data_direction dir,
645 if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0)
646 __iommu_sync_sg_for_cpu(dev, sgl, nelems, dir);
648 iommu_dma_unmap_sg(dev, sgl, nelems, dir, attrs);
651 static const struct dma_map_ops iommu_dma_ops = {
652 .alloc = __iommu_alloc_attrs,
653 .free = __iommu_free_attrs,
654 .mmap = __iommu_mmap_attrs,
655 .get_sgtable = __iommu_get_sgtable,
656 .map_page = __iommu_map_page,
657 .unmap_page = __iommu_unmap_page,
658 .map_sg = __iommu_map_sg_attrs,
659 .unmap_sg = __iommu_unmap_sg_attrs,
660 .sync_single_for_cpu = __iommu_sync_single_for_cpu,
661 .sync_single_for_device = __iommu_sync_single_for_device,
662 .sync_sg_for_cpu = __iommu_sync_sg_for_cpu,
663 .sync_sg_for_device = __iommu_sync_sg_for_device,
664 .map_resource = iommu_dma_map_resource,
665 .unmap_resource = iommu_dma_unmap_resource,
666 .mapping_error = iommu_dma_mapping_error,
669 static int __init __iommu_dma_init(void)
671 return iommu_dma_init();
673 arch_initcall(__iommu_dma_init);
675 static void __iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
676 const struct iommu_ops *ops)
678 struct iommu_domain *domain;
684 * The IOMMU core code allocates the default DMA domain, which the
685 * underlying IOMMU driver needs to support via the dma-iommu layer.
687 domain = iommu_get_domain_for_dev(dev);
692 if (domain->type == IOMMU_DOMAIN_DMA) {
693 if (iommu_dma_init_domain(domain, dma_base, size, dev))
696 dev->dma_ops = &iommu_dma_ops;
702 pr_warn("Failed to set up IOMMU for device %s; retaining platform DMA ops\n",
706 void arch_teardown_dma_ops(struct device *dev)
713 static void __iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
714 const struct iommu_ops *iommu)
717 #endif /* CONFIG_IOMMU_DMA */
719 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
720 const struct iommu_ops *iommu, bool coherent)
723 dev->dma_ops = &swiotlb_dma_ops;
725 dev->dma_coherent = coherent;
726 __iommu_setup_dma_ops(dev, dma_base, size, iommu);
729 if (xen_initial_domain()) {
730 dev->archdata.dev_dma_ops = dev->dma_ops;
731 dev->dma_ops = xen_dma_ops;