2 * Based on arch/arm/mm/proc.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/init.h>
22 #include <linux/linkage.h>
23 #include <asm/assembler.h>
24 #include <asm/asm-offsets.h>
25 #include <asm/hwcap.h>
26 #include <asm/pgtable.h>
27 #include <asm/pgtable-hwdef.h>
28 #include <asm/cpufeature.h>
29 #include <asm/alternative.h>
31 #ifdef CONFIG_ARM64_64K_PAGES
32 #define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K
33 #elif defined(CONFIG_ARM64_16K_PAGES)
34 #define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K
35 #else /* CONFIG_ARM64_4K_PAGES */
36 #define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K
39 #ifdef CONFIG_RANDOMIZE_BASE
40 #define TCR_KASLR_FLAGS TCR_NFD1
42 #define TCR_KASLR_FLAGS 0
45 #define TCR_SMP_FLAGS TCR_SHARED
47 /* PTWs cacheable, inner/outer WBWA */
48 #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
50 #define MAIR(attr, mt) ((attr) << ((mt) * 8))
55 * Idle the processor (wait for interrupt).
58 dsb sy // WFI may enter a low-power mode
65 * cpu_do_suspend - save CPU registers context
67 * x0: virtual address of context pointer
72 mrs x4, contextidr_el1
79 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
86 stp x4, xzr, [x0, #16]
89 stp x9, x10, [x0, #64]
90 stp x11, x12, [x0, #80]
92 ENDPROC(cpu_do_suspend)
95 * cpu_do_resume - restore CPU register context
97 * x0: Address of context pointer
99 .pushsection ".idmap.text", "awx"
102 ldp x4, x5, [x0, #16]
103 ldp x6, x8, [x0, #32]
104 ldp x9, x10, [x0, #48]
105 ldp x11, x12, [x0, #64]
106 ldp x13, x14, [x0, #80]
109 msr contextidr_el1, x4
112 /* Don't change t0sz here, mask those bits when restoring */
114 bfi x8, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
120 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
121 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
122 * exception. Mask them until local_daif_restore() in cpu_suspend()
129 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
136 * Restore oslsr_el1 by writing oslar_el1
138 ubfx x11, x11, #1, #1
140 reset_pmuserenr_el0 x0 // Disable PMU access from EL0
142 alternative_if ARM64_HAS_RAS_EXTN
143 msr_s SYS_DISR_EL1, xzr
144 alternative_else_nop_endif
148 ENDPROC(cpu_do_resume)
153 * cpu_do_switch_mm(pgd_phys, tsk)
155 * Set the translation table base pointer to be pgd_phys.
157 * - pgd_phys - physical address of new TTB
159 ENTRY(cpu_do_switch_mm)
161 mmid x1, x1 // get mm->context.id
164 alternative_if ARM64_HAS_CNP
165 cbz x1, 1f // skip CNP for reserved ASID
166 orr x3, x3, #TTBR_CNP_BIT
168 alternative_else_nop_endif
169 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
170 bfi x3, x1, #48, #16 // set the ASID field in TTBR0
172 bfi x2, x1, #48, #16 // set the ASID
173 msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set)
175 msr ttbr0_el1, x3 // now update TTBR0
177 b post_ttbr_update_workaround // Back to C code...
178 ENDPROC(cpu_do_switch_mm)
180 .pushsection ".idmap.text", "awx"
182 .macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
183 adrp \tmp1, empty_zero_page
184 phys_to_ttbr \tmp2, \tmp1
194 * void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
196 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
197 * called by anything else. It can only be executed from a TTBR0 mapping.
199 ENTRY(idmap_cpu_replace_ttbr1)
200 save_and_disable_daif flags=x2
202 __idmap_cpu_set_reserved_ttbr1 x1, x3
211 ENDPROC(idmap_cpu_replace_ttbr1)
214 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
215 .pushsection ".idmap.text", "awx"
217 .macro __idmap_kpti_get_pgtable_ent, type
218 dc cvac, cur_\()\type\()p // Ensure any existing dirty
219 dmb sy // lines are written back before
220 ldr \type, [cur_\()\type\()p] // loading the entry
221 tbz \type, #0, skip_\()\type // Skip invalid and
222 tbnz \type, #11, skip_\()\type // non-global entries
225 .macro __idmap_kpti_put_pgtable_ent_ng, type
226 orr \type, \type, #PTE_NG // Same bit for blocks and pages
227 str \type, [cur_\()\type\()p] // Update the entry and ensure
228 dmb sy // that it is visible to all
229 dc civac, cur_\()\type\()p // CPUs.
233 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
235 * Called exactly once from stop_machine context by each CPU found during boot.
239 ENTRY(idmap_kpti_install_ng_mappings)
258 mrs swapper_ttb, ttbr1_el1
259 restore_ttbr1 swapper_ttb
260 adr flag_ptr, __idmap_kpti_flag
262 cbnz cpu, __idmap_kpti_secondary
264 /* We're the boot CPU. Wait for the others to catch up */
267 ldaxr w18, [flag_ptr]
268 eor w18, w18, num_cpus
271 /* We need to walk swapper, so turn off the MMU. */
272 pre_disable_mmu_workaround
274 bic x18, x18, #SCTLR_ELx_M
278 /* Everybody is enjoying the idmap, so we can rewrite swapper. */
280 mov cur_pgdp, swapper_pa
281 add end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
282 do_pgd: __idmap_kpti_get_pgtable_ent pgd
283 tbnz pgd, #1, walk_puds
285 __idmap_kpti_put_pgtable_ent_ng pgd
287 add cur_pgdp, cur_pgdp, #8
288 cmp cur_pgdp, end_pgdp
291 /* Publish the updated tables and nuke all the TLBs */
297 /* We're done: fire up the MMU again */
299 orr x18, x18, #SCTLR_ELx_M
303 /* Set the flag to zero to indicate that we're all done */
309 .if CONFIG_PGTABLE_LEVELS > 3
310 pte_to_phys cur_pudp, pgd
311 add end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
312 do_pud: __idmap_kpti_get_pgtable_ent pud
313 tbnz pud, #1, walk_pmds
315 __idmap_kpti_put_pgtable_ent_ng pud
317 add cur_pudp, cur_pudp, 8
318 cmp cur_pudp, end_pudp
321 .else /* CONFIG_PGTABLE_LEVELS <= 3 */
330 .if CONFIG_PGTABLE_LEVELS > 2
331 pte_to_phys cur_pmdp, pud
332 add end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
333 do_pmd: __idmap_kpti_get_pgtable_ent pmd
334 tbnz pmd, #1, walk_ptes
336 __idmap_kpti_put_pgtable_ent_ng pmd
338 add cur_pmdp, cur_pmdp, #8
339 cmp cur_pmdp, end_pmdp
342 .else /* CONFIG_PGTABLE_LEVELS <= 2 */
351 pte_to_phys cur_ptep, pmd
352 add end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
353 do_pte: __idmap_kpti_get_pgtable_ent pte
354 __idmap_kpti_put_pgtable_ent_ng pte
356 add cur_ptep, cur_ptep, #8
357 cmp cur_ptep, end_ptep
361 /* Secondary CPUs end up here */
362 __idmap_kpti_secondary:
363 /* Uninstall swapper before surgery begins */
364 __idmap_cpu_set_reserved_ttbr1 x18, x17
366 /* Increment the flag to let the boot CPU we're ready */
367 1: ldxr w18, [flag_ptr]
369 stxr w17, w18, [flag_ptr]
372 /* Wait for the boot CPU to finish messing around with swapper */
378 /* All done, act like nothing happened */
379 offset_ttbr1 swapper_ttb
380 msr ttbr1_el1, swapper_ttb
401 ENDPROC(idmap_kpti_install_ng_mappings)
408 * Initialise the processor for turning the MMU on. Return in x0 the
409 * value of the SCTLR_EL1 register.
411 .pushsection ".idmap.text", "awx"
413 tlbi vmalle1 // Invalidate local TLB
417 msr cpacr_el1, x0 // Enable FP/ASIMD
418 mov x0, #1 << 12 // Reset mdscr_el1 and disable
419 msr mdscr_el1, x0 // access to the DCC from EL0
420 isb // Unmask debug exceptions now,
421 enable_dbg // since this is per-cpu
422 reset_pmuserenr_el0 x0 // Disable PMU access from EL0
424 * Memory region attributes for LPAE:
428 * DEVICE_nGnRnE 000 00000000
429 * DEVICE_nGnRE 001 00000100
430 * DEVICE_GRE 010 00001100
431 * NORMAL_NC 011 01000100
432 * NORMAL 100 11111111
433 * NORMAL_WT 101 10111011
435 ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
436 MAIR(0x04, MT_DEVICE_nGnRE) | \
437 MAIR(0x0c, MT_DEVICE_GRE) | \
438 MAIR(0x44, MT_NORMAL_NC) | \
439 MAIR(0xff, MT_NORMAL) | \
440 MAIR(0xbb, MT_NORMAL_WT)
445 mov_q x0, SCTLR_EL1_SET
447 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
448 * both user and kernel.
450 ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
451 TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
454 #ifdef CONFIG_ARM64_52BIT_VA
455 ldr_l x9, vabits_user
464 * Set the IPS bits in TCR_EL1.
466 tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6
467 #ifdef CONFIG_ARM64_HW_AFDBM
469 * Enable hardware update of the Access Flags bit.
470 * Hardware dirty bit management is enabled later,
473 mrs x9, ID_AA64MMFR1_EL1
476 orr x10, x10, #TCR_HA // hardware Access flag update
478 #endif /* CONFIG_ARM64_HW_AFDBM */
480 ret // return to head.S