1 /* SPDX-License-Identifier: GPL-2.0 */
3 #ifndef __ABI_CSKY_CACHEFLUSH_H
4 #define __ABI_CSKY_CACHEFLUSH_H
6 /* Keep includes the same across arches. */
10 * The cache doesn't need to be flushed when TLB entries change when
11 * the cache is mapped to physical memory, not virtual memory
13 #define flush_cache_all() do { } while (0)
14 #define flush_cache_mm(mm) do { } while (0)
15 #define flush_cache_dup_mm(mm) do { } while (0)
17 #define flush_cache_range(vma, start, end) \
19 if (vma->vm_flags & VM_EXEC) \
23 #define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
24 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
25 #define flush_dcache_page(page) do { } while (0)
26 #define flush_dcache_mmap_lock(mapping) do { } while (0)
27 #define flush_dcache_mmap_unlock(mapping) do { } while (0)
29 #define flush_icache_range(start, end) cache_wbinv_range(start, end)
31 void flush_icache_page(struct vm_area_struct *vma, struct page *page);
32 void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
33 unsigned long vaddr, int len);
35 #define flush_cache_vmap(start, end) do { } while (0)
36 #define flush_cache_vunmap(start, end) do { } while (0)
38 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
40 memcpy(dst, src, len); \
41 cache_wbinv_range((unsigned long)dst, (unsigned long)dst + len); \
43 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
46 #endif /* __ABI_CSKY_CACHEFLUSH_H */