1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
4 #include <linux/spinlock.h>
8 #include <asm/barrier.h>
10 #define INS_CACHE (1 << 0)
11 #define CACHE_INV (1 << 4)
13 void local_icache_inv_all(void *priv)
15 mtcr("cr17", INS_CACHE|CACHE_INV);
19 void icache_inv_all(void)
21 on_each_cpu(local_icache_inv_all, NULL, 1);
24 #ifdef CONFIG_CPU_HAS_ICACHE_INS
25 void icache_inv_range(unsigned long start, unsigned long end)
27 unsigned long i = start & ~(L1_CACHE_BYTES - 1);
29 for (; i < end; i += L1_CACHE_BYTES)
30 asm volatile("icache.iva %0\n"::"r"(i):"memory");
34 void icache_inv_range(unsigned long start, unsigned long end)
40 inline void dcache_wb_line(unsigned long start)
42 asm volatile("dcache.cval1 %0\n"::"r"(start):"memory");
46 void dcache_wb_range(unsigned long start, unsigned long end)
48 unsigned long i = start & ~(L1_CACHE_BYTES - 1);
50 for (; i < end; i += L1_CACHE_BYTES)
51 asm volatile("dcache.cval1 %0\n"::"r"(i):"memory");
55 void dcache_inv_range(unsigned long start, unsigned long end)
57 unsigned long i = start & ~(L1_CACHE_BYTES - 1);
59 for (; i < end; i += L1_CACHE_BYTES)
60 asm volatile("dcache.civa %0\n"::"r"(i):"memory");
64 void cache_wbinv_range(unsigned long start, unsigned long end)
66 unsigned long i = start & ~(L1_CACHE_BYTES - 1);
68 for (; i < end; i += L1_CACHE_BYTES)
69 asm volatile("dcache.cval1 %0\n"::"r"(i):"memory");
72 icache_inv_range(start, end);
74 EXPORT_SYMBOL(cache_wbinv_range);
76 void dma_wbinv_range(unsigned long start, unsigned long end)
78 unsigned long i = start & ~(L1_CACHE_BYTES - 1);
80 for (; i < end; i += L1_CACHE_BYTES)
81 asm volatile("dcache.civa %0\n"::"r"(i):"memory");
85 void dma_inv_range(unsigned long start, unsigned long end)
87 unsigned long i = start & ~(L1_CACHE_BYTES - 1);
89 for (; i < end; i += L1_CACHE_BYTES)
90 asm volatile("dcache.iva %0\n"::"r"(i):"memory");
94 void dma_wb_range(unsigned long start, unsigned long end)
96 unsigned long i = start & ~(L1_CACHE_BYTES - 1);
98 for (; i < end; i += L1_CACHE_BYTES)
99 asm volatile("dcache.cva %0\n"::"r"(i):"memory");