2 * device.c -- common ColdFire SoC device support
4 * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
11 #include <linux/kernel.h>
12 #include <linux/init.h>
14 #include <linux/spi/spi.h>
15 #include <linux/gpio.h>
16 #include <linux/fec.h>
17 #include <linux/dmaengine.h>
18 #include <asm/traps.h>
19 #include <asm/coldfire.h>
20 #include <asm/mcfsim.h>
21 #include <asm/mcfuart.h>
22 #include <asm/mcfqspi.h>
23 #include <linux/platform_data/edma.h>
24 #include <linux/platform_data/dma-mcf-edma.h>
27 * All current ColdFire parts contain from 2, 3, 4 or 10 UARTS.
29 static struct mcf_platform_uart mcf_uart_platform_data[] = {
31 .mapbase = MCFUART_BASE0,
35 .mapbase = MCFUART_BASE1,
40 .mapbase = MCFUART_BASE2,
46 .mapbase = MCFUART_BASE3,
52 .mapbase = MCFUART_BASE4,
58 .mapbase = MCFUART_BASE5,
64 .mapbase = MCFUART_BASE6,
70 .mapbase = MCFUART_BASE7,
76 .mapbase = MCFUART_BASE8,
82 .mapbase = MCFUART_BASE9,
89 static struct platform_device mcf_uart = {
92 .dev.platform_data = mcf_uart_platform_data,
95 #if IS_ENABLED(CONFIG_FEC)
98 #define FEC_NAME "enet-fec"
99 static struct fec_platform_data fec_pdata = {
100 .phy = PHY_INTERFACE_MODE_RMII,
102 #define FEC_PDATA (&fec_pdata)
104 #define FEC_NAME "fec"
105 #define FEC_PDATA NULL
109 * Some ColdFire cores contain the Fast Ethernet Controller (FEC)
110 * block. It is Freescale's own hardware block. Some ColdFires
113 static struct resource mcf_fec0_resources[] = {
115 .start = MCFFEC_BASE0,
116 .end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
117 .flags = IORESOURCE_MEM,
120 .start = MCF_IRQ_FECRX0,
121 .end = MCF_IRQ_FECRX0,
122 .flags = IORESOURCE_IRQ,
125 .start = MCF_IRQ_FECTX0,
126 .end = MCF_IRQ_FECTX0,
127 .flags = IORESOURCE_IRQ,
130 .start = MCF_IRQ_FECENTC0,
131 .end = MCF_IRQ_FECENTC0,
132 .flags = IORESOURCE_IRQ,
136 static struct platform_device mcf_fec0 = {
139 .num_resources = ARRAY_SIZE(mcf_fec0_resources),
140 .resource = mcf_fec0_resources,
142 .dma_mask = &mcf_fec0.dev.coherent_dma_mask,
143 .coherent_dma_mask = DMA_BIT_MASK(32),
144 .platform_data = FEC_PDATA,
149 static struct resource mcf_fec1_resources[] = {
151 .start = MCFFEC_BASE1,
152 .end = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
153 .flags = IORESOURCE_MEM,
156 .start = MCF_IRQ_FECRX1,
157 .end = MCF_IRQ_FECRX1,
158 .flags = IORESOURCE_IRQ,
161 .start = MCF_IRQ_FECTX1,
162 .end = MCF_IRQ_FECTX1,
163 .flags = IORESOURCE_IRQ,
166 .start = MCF_IRQ_FECENTC1,
167 .end = MCF_IRQ_FECENTC1,
168 .flags = IORESOURCE_IRQ,
172 static struct platform_device mcf_fec1 = {
175 .num_resources = ARRAY_SIZE(mcf_fec1_resources),
176 .resource = mcf_fec1_resources,
178 .dma_mask = &mcf_fec1.dev.coherent_dma_mask,
179 .coherent_dma_mask = DMA_BIT_MASK(32),
180 .platform_data = FEC_PDATA,
183 #endif /* MCFFEC_BASE1 */
184 #endif /* CONFIG_FEC */
186 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
188 * The ColdFire QSPI module is an SPI protocol hardware block used
189 * on a number of different ColdFire CPUs.
191 static struct resource mcf_qspi_resources[] = {
193 .start = MCFQSPI_BASE,
194 .end = MCFQSPI_BASE + MCFQSPI_SIZE - 1,
195 .flags = IORESOURCE_MEM,
198 .start = MCF_IRQ_QSPI,
200 .flags = IORESOURCE_IRQ,
204 static int mcf_cs_setup(struct mcfqspi_cs_control *cs_control)
208 status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
210 pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
213 status = gpio_direction_output(MCFQSPI_CS0, 1);
215 pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
219 status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
221 pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
224 status = gpio_direction_output(MCFQSPI_CS1, 1);
226 pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
230 status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
232 pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
235 status = gpio_direction_output(MCFQSPI_CS2, 1);
237 pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
242 status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
244 pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
247 status = gpio_direction_output(MCFQSPI_CS3, 1);
249 pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
250 gpio_free(MCFQSPI_CS3);
258 gpio_free(MCFQSPI_CS2);
260 gpio_free(MCFQSPI_CS1);
262 gpio_free(MCFQSPI_CS0);
267 static void mcf_cs_teardown(struct mcfqspi_cs_control *cs_control)
270 gpio_free(MCFQSPI_CS3);
272 gpio_free(MCFQSPI_CS2);
273 gpio_free(MCFQSPI_CS1);
274 gpio_free(MCFQSPI_CS0);
277 static void mcf_cs_select(struct mcfqspi_cs_control *cs_control,
278 u8 chip_select, bool cs_high)
280 switch (chip_select) {
282 gpio_set_value(MCFQSPI_CS0, cs_high);
285 gpio_set_value(MCFQSPI_CS1, cs_high);
288 gpio_set_value(MCFQSPI_CS2, cs_high);
292 gpio_set_value(MCFQSPI_CS3, cs_high);
298 static void mcf_cs_deselect(struct mcfqspi_cs_control *cs_control,
299 u8 chip_select, bool cs_high)
301 switch (chip_select) {
303 gpio_set_value(MCFQSPI_CS0, !cs_high);
306 gpio_set_value(MCFQSPI_CS1, !cs_high);
309 gpio_set_value(MCFQSPI_CS2, !cs_high);
313 gpio_set_value(MCFQSPI_CS3, !cs_high);
319 static struct mcfqspi_cs_control mcf_cs_control = {
320 .setup = mcf_cs_setup,
321 .teardown = mcf_cs_teardown,
322 .select = mcf_cs_select,
323 .deselect = mcf_cs_deselect,
326 static struct mcfqspi_platform_data mcf_qspi_data = {
329 .cs_control = &mcf_cs_control,
332 static struct platform_device mcf_qspi = {
335 .num_resources = ARRAY_SIZE(mcf_qspi_resources),
336 .resource = mcf_qspi_resources,
337 .dev.platform_data = &mcf_qspi_data,
339 #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
341 #if IS_ENABLED(CONFIG_I2C_IMX)
342 static struct resource mcf_i2c0_resources[] = {
344 .start = MCFI2C_BASE0,
345 .end = MCFI2C_BASE0 + MCFI2C_SIZE0 - 1,
346 .flags = IORESOURCE_MEM,
349 .start = MCF_IRQ_I2C0,
351 .flags = IORESOURCE_IRQ,
355 static struct platform_device mcf_i2c0 = {
358 .num_resources = ARRAY_SIZE(mcf_i2c0_resources),
359 .resource = mcf_i2c0_resources,
363 static struct resource mcf_i2c1_resources[] = {
365 .start = MCFI2C_BASE1,
366 .end = MCFI2C_BASE1 + MCFI2C_SIZE1 - 1,
367 .flags = IORESOURCE_MEM,
370 .start = MCF_IRQ_I2C1,
372 .flags = IORESOURCE_IRQ,
376 static struct platform_device mcf_i2c1 = {
379 .num_resources = ARRAY_SIZE(mcf_i2c1_resources),
380 .resource = mcf_i2c1_resources,
383 #endif /* MCFI2C_BASE1 */
387 static struct resource mcf_i2c2_resources[] = {
389 .start = MCFI2C_BASE2,
390 .end = MCFI2C_BASE2 + MCFI2C_SIZE2 - 1,
391 .flags = IORESOURCE_MEM,
394 .start = MCF_IRQ_I2C2,
396 .flags = IORESOURCE_IRQ,
400 static struct platform_device mcf_i2c2 = {
403 .num_resources = ARRAY_SIZE(mcf_i2c2_resources),
404 .resource = mcf_i2c2_resources,
407 #endif /* MCFI2C_BASE2 */
411 static struct resource mcf_i2c3_resources[] = {
413 .start = MCFI2C_BASE3,
414 .end = MCFI2C_BASE3 + MCFI2C_SIZE3 - 1,
415 .flags = IORESOURCE_MEM,
418 .start = MCF_IRQ_I2C3,
420 .flags = IORESOURCE_IRQ,
424 static struct platform_device mcf_i2c3 = {
427 .num_resources = ARRAY_SIZE(mcf_i2c3_resources),
428 .resource = mcf_i2c3_resources,
431 #endif /* MCFI2C_BASE3 */
435 static struct resource mcf_i2c4_resources[] = {
437 .start = MCFI2C_BASE4,
438 .end = MCFI2C_BASE4 + MCFI2C_SIZE4 - 1,
439 .flags = IORESOURCE_MEM,
442 .start = MCF_IRQ_I2C4,
444 .flags = IORESOURCE_IRQ,
448 static struct platform_device mcf_i2c4 = {
451 .num_resources = ARRAY_SIZE(mcf_i2c4_resources),
452 .resource = mcf_i2c4_resources,
455 #endif /* MCFI2C_BASE4 */
459 static struct resource mcf_i2c5_resources[] = {
461 .start = MCFI2C_BASE5,
462 .end = MCFI2C_BASE5 + MCFI2C_SIZE5 - 1,
463 .flags = IORESOURCE_MEM,
466 .start = MCF_IRQ_I2C5,
468 .flags = IORESOURCE_IRQ,
472 static struct platform_device mcf_i2c5 = {
475 .num_resources = ARRAY_SIZE(mcf_i2c5_resources),
476 .resource = mcf_i2c5_resources,
479 #endif /* MCFI2C_BASE5 */
480 #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
482 #if IS_ENABLED(CONFIG_MCF_EDMA)
484 static const struct dma_slave_map mcf_edma_map[] = {
485 { "dreq0", "rx-tx", MCF_EDMA_FILTER_PARAM(0) },
486 { "dreq1", "rx-tx", MCF_EDMA_FILTER_PARAM(1) },
487 { "uart.0", "rx", MCF_EDMA_FILTER_PARAM(2) },
488 { "uart.0", "tx", MCF_EDMA_FILTER_PARAM(3) },
489 { "uart.1", "rx", MCF_EDMA_FILTER_PARAM(4) },
490 { "uart.1", "tx", MCF_EDMA_FILTER_PARAM(5) },
491 { "uart.2", "rx", MCF_EDMA_FILTER_PARAM(6) },
492 { "uart.2", "tx", MCF_EDMA_FILTER_PARAM(7) },
493 { "timer0", "rx-tx", MCF_EDMA_FILTER_PARAM(8) },
494 { "timer1", "rx-tx", MCF_EDMA_FILTER_PARAM(9) },
495 { "timer2", "rx-tx", MCF_EDMA_FILTER_PARAM(10) },
496 { "timer3", "rx-tx", MCF_EDMA_FILTER_PARAM(11) },
497 { "fsl-dspi.0", "rx", MCF_EDMA_FILTER_PARAM(12) },
498 { "fsl-dspi.0", "tx", MCF_EDMA_FILTER_PARAM(13) },
499 { "fsl-dspi.1", "rx", MCF_EDMA_FILTER_PARAM(14) },
500 { "fsl-dspi.1", "tx", MCF_EDMA_FILTER_PARAM(15) },
503 static struct mcf_edma_platform_data mcf_edma_data = {
505 .slave_map = mcf_edma_map,
506 .slavecnt = ARRAY_SIZE(mcf_edma_map),
509 static struct resource mcf_edma_resources[] = {
511 .start = MCFEDMA_BASE,
512 .end = MCFEDMA_BASE + MCFEDMA_SIZE - 1,
513 .flags = IORESOURCE_MEM,
516 .start = MCFEDMA_IRQ_INTR0,
517 .end = MCFEDMA_IRQ_INTR0 + 15,
518 .flags = IORESOURCE_IRQ,
519 .name = "edma-tx-00-15",
522 .start = MCFEDMA_IRQ_INTR16,
523 .end = MCFEDMA_IRQ_INTR16 + 39,
524 .flags = IORESOURCE_IRQ,
525 .name = "edma-tx-16-55",
528 .start = MCFEDMA_IRQ_INTR56,
529 .end = MCFEDMA_IRQ_INTR56,
530 .flags = IORESOURCE_IRQ,
531 .name = "edma-tx-56-63",
534 .start = MCFEDMA_IRQ_ERR,
535 .end = MCFEDMA_IRQ_ERR,
536 .flags = IORESOURCE_IRQ,
541 static u64 mcf_edma_dmamask = DMA_BIT_MASK(32);
543 static struct platform_device mcf_edma = {
546 .num_resources = ARRAY_SIZE(mcf_edma_resources),
547 .resource = mcf_edma_resources,
549 .dma_mask = &mcf_edma_dmamask,
550 .coherent_dma_mask = DMA_BIT_MASK(32),
551 .platform_data = &mcf_edma_data,
555 #endif /* IS_ENABLED(CONFIG_MCF_EDMA) */
557 static struct platform_device *mcf_devices[] __initdata = {
559 #if IS_ENABLED(CONFIG_FEC)
565 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
568 #if IS_ENABLED(CONFIG_I2C_IMX)
586 #if IS_ENABLED(CONFIG_MCF_EDMA)
592 * Some ColdFire UARTs let you set the IRQ line to use.
594 static void __init mcf_uart_set_irq(void)
597 /* UART0 interrupt setup */
598 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCFSIM_UART1ICR);
599 writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
600 mcf_mapirq2imr(MCF_IRQ_UART0, MCFINTC_UART0);
602 /* UART1 interrupt setup */
603 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCFSIM_UART2ICR);
604 writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
605 mcf_mapirq2imr(MCF_IRQ_UART1, MCFINTC_UART1);
609 static int __init mcf_init_devices(void)
612 platform_add_devices(mcf_devices, ARRAY_SIZE(mcf_devices));
616 arch_initcall(mcf_init_devices);