5 * In contrary to the Amiga and Atari platforms, the Mac hardware seems to
6 * exclusively use the autovector interrupts (the 'generic level0-level7'
7 * interrupts with exception vectors 0x19-0x1f). The following interrupt levels
10 * - slot 0: one second interrupt (CA2)
11 * - slot 1: VBlank (CA1)
12 * - slot 2: ADB data ready (SR full)
13 * - slot 3: ADB data (CB2)
14 * - slot 4: ADB clock (CB1)
17 * - slot 7: status of IRQ; signals 'any enabled int.'
20 * - slot 0: SCSI DRQ (CA2)
21 * - slot 1: NUBUS IRQ (CA1) need to read port A to find which
22 * - slot 2: /EXP IRQ (only on IIci)
23 * - slot 3: SCSI IRQ (CB2)
24 * - slot 4: ASC IRQ (CB1)
25 * - slot 5: timer 2 (not on IIci)
26 * - slot 6: timer 1 (not on IIci)
27 * - slot 7: status of IRQ; signals 'any enabled int.'
29 * Levels 3-6 vary by machine type. For VIA or RBV Macintoshes:
36 * [serial errors or special conditions seem to raise level 6
37 * interrupts on some models (LC4xx?)]
41 * Machines with Quadra-like VIA hardware, except PSC and PMU machines, support
42 * an alternate interrupt mapping, as used by A/UX. It spreads ethernet and
43 * sound out to their own autovector IRQs and gives VIA1 a higher priority:
49 * 5 - Apple Sound Chip (ASC)
53 * For OSS Macintoshes (IIfx only), we apply an interrupt mapping similar to
54 * the Quadra (A/UX) mapping:
66 * For PSC Macintoshes (660AV, 840AV):
72 * - slot 1: SCC channel A interrupt
73 * - slot 2: SCC channel B interrupt
80 * Finally we have good 'ole level 7, the non-maskable interrupt:
82 * 7 - NMI (programmer's switch on the back of some Macs)
83 * Also RAM parity error on models which support it (IIc, IIfx?)
85 * The current interrupt logic looks something like this:
87 * - We install dispatchers for the autovector interrupts (1-7). These
88 * dispatchers are responsible for querying the hardware (the
89 * VIA/RBV/OSS/PSC chips) to determine the actual interrupt source. Using
90 * this information a machspec interrupt number is generated by placing the
91 * index of the interrupt hardware into the low three bits and the original
92 * autovector interrupt number in the upper 5 bits. The handlers for the
93 * resulting machspec interrupt are then called.
95 * - Nubus is a special case because its interrupts are hidden behind two
96 * layers of hardware. Nubus interrupts come in as index 1 on VIA #2,
97 * which translates to IRQ number 17. In this spot we install _another_
98 * dispatcher. This dispatcher finds the interrupting slot number (9-F) and
99 * then forms a new machspec interrupt number as above with the slot number
100 * minus 9 in the low three bits and the pseudo-level 7 in the upper five
101 * bits. The handlers for this new machspec interrupt number are then
102 * called. This puts Nubus interrupts into the range 56-62.
104 * - The Baboon interrupts (used on some PowerBooks) are an even more special
105 * case. They're hidden behind the Nubus slot $C interrupt thus adding a
106 * third layer of indirection. Why oh why did the Apple engineers do that?
110 #include <linux/types.h>
111 #include <linux/kernel.h>
112 #include <linux/sched.h>
113 #include <linux/interrupt.h>
114 #include <linux/irq.h>
115 #include <linux/delay.h>
118 #include <asm/macintosh.h>
119 #include <asm/macints.h>
120 #include <asm/mac_via.h>
121 #include <asm/mac_psc.h>
122 #include <asm/mac_oss.h>
123 #include <asm/mac_iop.h>
124 #include <asm/mac_baboon.h>
125 #include <asm/hwtest.h>
126 #include <asm/irq_regs.h>
130 extern void show_registers(struct pt_regs *);
132 irqreturn_t mac_nmi_handler(int, void *);
134 /* #define DEBUG_MACINTS */
136 static unsigned int mac_irq_startup(struct irq_data *);
137 static void mac_irq_shutdown(struct irq_data *);
139 static struct irq_chip mac_irq_chip = {
141 .irq_enable = mac_irq_enable,
142 .irq_disable = mac_irq_disable,
143 .irq_startup = mac_irq_startup,
144 .irq_shutdown = mac_irq_shutdown,
147 void __init mac_init_IRQ(void)
150 printk("mac_init_IRQ(): Setting things up...\n");
152 m68k_setup_irq_controller(&mac_irq_chip, handle_simple_irq, IRQ_USER,
153 NUM_MAC_SOURCES - IRQ_USER);
154 /* Make sure the SONIC interrupt is cleared or things get ugly */
156 printk("Killing onboard sonic... ");
157 /* This address should hopefully be mapped already */
158 if (hwreg_present((void*)(0x50f0a000))) {
159 *(long *)(0x50f0a014) = 0x7fffL;
160 *(long *)(0x50f0a010) = 0L;
163 #endif /* SHUTUP_SONIC */
166 * Now register the handlers for the master IRQ handlers
167 * at levels 1-7. Most of the work is done elsewhere.
171 oss_register_interrupts();
173 via_register_interrupts();
175 psc_register_interrupts();
177 baboon_register_interrupts();
178 iop_register_interrupts();
179 if (request_irq(IRQ_AUTO_7, mac_nmi_handler, 0, "NMI",
181 pr_err("Couldn't register NMI\n");
183 printk("mac_init_IRQ(): Done!\n");
188 * mac_irq_enable - enable an interrupt source
189 * mac_irq_disable - disable an interrupt source
191 * These routines are just dispatchers to the VIA/OSS/PSC routines.
194 void mac_irq_enable(struct irq_data *data)
197 int irq_src = IRQ_SRC(irq);
214 else if (oss_present)
219 baboon_irq_enable(irq);
224 void mac_irq_disable(struct irq_data *data)
227 int irq_src = IRQ_SRC(irq);
234 oss_irq_disable(irq);
236 via_irq_disable(irq);
243 psc_irq_disable(irq);
244 else if (oss_present)
245 oss_irq_disable(irq);
249 baboon_irq_disable(irq);
254 static unsigned int mac_irq_startup(struct irq_data *data)
258 if (IRQ_SRC(irq) == 7 && !oss_present)
259 via_nubus_irq_startup(irq);
261 mac_irq_enable(data);
266 static void mac_irq_shutdown(struct irq_data *data)
270 if (IRQ_SRC(irq) == 7 && !oss_present)
271 via_nubus_irq_shutdown(irq);
273 mac_irq_disable(data);
276 static volatile int in_nmi;
278 irqreturn_t mac_nmi_handler(int irq, void *dev_id)
284 pr_info("Non-Maskable Interrupt\n");
285 show_registers(get_irq_regs());