1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/jz4740-cgu.h>
7 compatible = "ingenic,jz4740";
9 cpuintc: interrupt-controller {
11 #interrupt-cells = <1>;
13 compatible = "mti,cpu-interrupt-controller";
16 intc: interrupt-controller@10001000 {
17 compatible = "ingenic,jz4740-intc";
18 reg = <0x10001000 0x14>;
21 #interrupt-cells = <1>;
23 interrupt-parent = <&cpuintc>;
28 compatible = "fixed-clock";
33 compatible = "fixed-clock";
35 clock-frequency = <32768>;
38 cgu: jz4740-cgu@10000000 {
39 compatible = "ingenic,jz4740-cgu";
40 reg = <0x10000000 0x100>;
42 clocks = <&ext>, <&rtc>;
43 clock-names = "ext", "rtc";
48 watchdog: watchdog@10002000 {
49 compatible = "ingenic,jz4740-watchdog";
50 reg = <0x10002000 0x10>;
52 clocks = <&cgu JZ4740_CLK_RTC>;
57 compatible = "ingenic,jz4740-tcu", "simple-mfd";
58 reg = <0x10002000 0x1000>;
61 ranges = <0x0 0x10002000 0x1000>;
65 clocks = <&cgu JZ4740_CLK_RTC
69 clock-names = "rtc", "ext", "pclk", "tcu";
72 #interrupt-cells = <1>;
74 interrupt-parent = <&intc>;
75 interrupts = <23 22 21>;
78 rtc_dev: rtc@10003000 {
79 compatible = "ingenic,jz4740-rtc";
80 reg = <0x10003000 0x40>;
82 interrupt-parent = <&intc>;
85 clocks = <&cgu JZ4740_CLK_RTC>;
89 pinctrl: pin-controller@10010000 {
90 compatible = "ingenic,jz4740-pinctrl";
91 reg = <0x10010000 0x400>;
97 compatible = "ingenic,jz4740-gpio";
101 gpio-ranges = <&pinctrl 0 0 32>;
104 interrupt-controller;
105 #interrupt-cells = <2>;
107 interrupt-parent = <&intc>;
112 compatible = "ingenic,jz4740-gpio";
116 gpio-ranges = <&pinctrl 0 32 32>;
119 interrupt-controller;
120 #interrupt-cells = <2>;
122 interrupt-parent = <&intc>;
127 compatible = "ingenic,jz4740-gpio";
131 gpio-ranges = <&pinctrl 0 64 32>;
134 interrupt-controller;
135 #interrupt-cells = <2>;
137 interrupt-parent = <&intc>;
142 compatible = "ingenic,jz4740-gpio";
146 gpio-ranges = <&pinctrl 0 96 32>;
149 interrupt-controller;
150 #interrupt-cells = <2>;
152 interrupt-parent = <&intc>;
157 aic: audio-controller@10020000 {
158 compatible = "ingenic,jz4740-i2s";
159 reg = <0x10020000 0x38>;
161 #sound-dai-cells = <0>;
163 interrupt-parent = <&intc>;
166 clocks = <&cgu JZ4740_CLK_AIC>,
167 <&cgu JZ4740_CLK_I2S>,
168 <&cgu JZ4740_CLK_EXT>,
169 <&cgu JZ4740_CLK_PLL_HALF>;
170 clock-names = "aic", "i2s", "ext", "pll half";
172 dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
173 dma-names = "rx", "tx";
176 codec: audio-codec@100200a4 {
177 compatible = "ingenic,jz4740-codec";
178 reg = <0x10020080 0x8>;
180 #sound-dai-cells = <0>;
182 clocks = <&cgu JZ4740_CLK_AIC>;
187 compatible = "ingenic,jz4740-mmc";
188 reg = <0x10021000 0x1000>;
190 clocks = <&cgu JZ4740_CLK_MMC>;
193 interrupt-parent = <&intc>;
196 dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>;
197 dma-names = "rx", "tx";
204 uart0: serial@10030000 {
205 compatible = "ingenic,jz4740-uart";
206 reg = <0x10030000 0x100>;
208 interrupt-parent = <&intc>;
211 clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
212 clock-names = "baud", "module";
215 uart1: serial@10031000 {
216 compatible = "ingenic,jz4740-uart";
217 reg = <0x10031000 0x100>;
219 interrupt-parent = <&intc>;
222 clocks = <&ext>, <&cgu JZ4740_CLK_UART1>;
223 clock-names = "baud", "module";
227 compatible = "ingenic,jz4740-adc";
228 reg = <0x10070000 0x30>;
229 #io-channel-cells = <1>;
231 clocks = <&cgu JZ4740_CLK_ADC>;
234 interrupt-parent = <&intc>;
238 nemc: memory-controller@13010000 {
239 compatible = "ingenic,jz4740-nemc";
240 reg = <0x13010000 0x54>;
241 #address-cells = <2>;
243 ranges = <1 0 0x18000000 0x4000000
244 2 0 0x14000000 0x4000000
245 3 0 0x0c000000 0x4000000
246 4 0 0x08000000 0x4000000>;
248 clocks = <&cgu JZ4740_CLK_MCLK>;
251 ecc: ecc-controller@13010100 {
252 compatible = "ingenic,jz4740-ecc";
253 reg = <0x13010100 0x2C>;
255 clocks = <&cgu JZ4740_CLK_MCLK>;
258 dmac: dma-controller@13020000 {
259 compatible = "ingenic,jz4740-dma";
260 reg = <0x13020000 0xbc
264 interrupt-parent = <&intc>;
267 clocks = <&cgu JZ4740_CLK_DMA>;
271 compatible = "ingenic,jz4740-ohci", "generic-ohci";
272 reg = <0x13030000 0x1000>;
274 clocks = <&cgu JZ4740_CLK_UHC>;
275 assigned-clocks = <&cgu JZ4740_CLK_UHC>;
276 assigned-clock-rates = <48000000>;
278 interrupt-parent = <&intc>;
285 compatible = "ingenic,jz4740-musb";
286 reg = <0x13040000 0x10000>;
288 interrupt-parent = <&intc>;
290 interrupt-names = "mc";
292 clocks = <&cgu JZ4740_CLK_UDC>;
296 lcd: lcd-controller@13050000 {
297 compatible = "ingenic,jz4740-lcd";
298 reg = <0x13050000 0x1000>;
300 interrupt-parent = <&intc>;
303 clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>;
304 clock-names = "lcd_pclk", "lcd";