2 * Atomic operations that C can't guarantee us. Useful for
3 * resource counting etc..
5 * But use these as seldom as possible since they are much more slower
6 * than regular operations.
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
12 * Copyright (C) 1996, 97, 99, 2000, 03, 04, 06 by Ralf Baechle
17 #include <linux/irqflags.h>
18 #include <linux/types.h>
19 #include <asm/barrier.h>
20 #include <asm/compiler.h>
21 #include <asm/cpu-features.h>
22 #include <asm/cmpxchg.h>
26 * Using a branch-likely instruction to check the result of an sc instruction
27 * works around a bug present in R10000 CPUs prior to revision 3.0 that could
28 * cause ll-sc sequences to execute non-atomically.
31 # define __scbeqz "beqzl"
33 # define __scbeqz "beqz"
36 #define ATOMIC_INIT(i) { (i) }
39 * atomic_read - read atomic variable
40 * @v: pointer of type atomic_t
42 * Atomically reads the value of @v.
44 #define atomic_read(v) READ_ONCE((v)->counter)
47 * atomic_set - set atomic variable
48 * @v: pointer of type atomic_t
51 * Atomically sets the value of @v to @i.
53 #define atomic_set(v, i) WRITE_ONCE((v)->counter, (i))
55 #define ATOMIC_OP(op, c_op, asm_op) \
56 static __inline__ void atomic_##op(int i, atomic_t * v) \
58 if (kernel_uses_llsc) { \
62 __asm__ __volatile__( \
64 " .set "MIPS_ISA_LEVEL" \n" \
65 "1: ll %0, %1 # atomic_" #op " \n" \
66 " " #asm_op " %0, %2 \n" \
68 "\t" __scbeqz " %0, 1b \n" \
70 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
73 unsigned long flags; \
75 raw_local_irq_save(flags); \
77 raw_local_irq_restore(flags); \
81 #define ATOMIC_OP_RETURN(op, c_op, asm_op) \
82 static __inline__ int atomic_##op##_return_relaxed(int i, atomic_t * v) \
86 if (kernel_uses_llsc) { \
90 __asm__ __volatile__( \
92 " .set "MIPS_ISA_LEVEL" \n" \
93 "1: ll %1, %2 # atomic_" #op "_return \n" \
94 " " #asm_op " %0, %1, %3 \n" \
96 "\t" __scbeqz " %0, 1b \n" \
97 " " #asm_op " %0, %1, %3 \n" \
99 : "=&r" (result), "=&r" (temp), \
100 "+" GCC_OFF_SMALL_ASM() (v->counter) \
103 unsigned long flags; \
105 raw_local_irq_save(flags); \
106 result = v->counter; \
108 v->counter = result; \
109 raw_local_irq_restore(flags); \
115 #define ATOMIC_FETCH_OP(op, c_op, asm_op) \
116 static __inline__ int atomic_fetch_##op##_relaxed(int i, atomic_t * v) \
120 if (kernel_uses_llsc) { \
123 loongson_llsc_mb(); \
124 __asm__ __volatile__( \
126 " .set "MIPS_ISA_LEVEL" \n" \
127 "1: ll %1, %2 # atomic_fetch_" #op " \n" \
128 " " #asm_op " %0, %1, %3 \n" \
130 "\t" __scbeqz " %0, 1b \n" \
133 : "=&r" (result), "=&r" (temp), \
134 "+" GCC_OFF_SMALL_ASM() (v->counter) \
137 unsigned long flags; \
139 raw_local_irq_save(flags); \
140 result = v->counter; \
142 raw_local_irq_restore(flags); \
148 #define ATOMIC_OPS(op, c_op, asm_op) \
149 ATOMIC_OP(op, c_op, asm_op) \
150 ATOMIC_OP_RETURN(op, c_op, asm_op) \
151 ATOMIC_FETCH_OP(op, c_op, asm_op)
153 ATOMIC_OPS(add, +=, addu)
154 ATOMIC_OPS(sub, -=, subu)
156 #define atomic_add_return_relaxed atomic_add_return_relaxed
157 #define atomic_sub_return_relaxed atomic_sub_return_relaxed
158 #define atomic_fetch_add_relaxed atomic_fetch_add_relaxed
159 #define atomic_fetch_sub_relaxed atomic_fetch_sub_relaxed
162 #define ATOMIC_OPS(op, c_op, asm_op) \
163 ATOMIC_OP(op, c_op, asm_op) \
164 ATOMIC_FETCH_OP(op, c_op, asm_op)
166 ATOMIC_OPS(and, &=, and)
167 ATOMIC_OPS(or, |=, or)
168 ATOMIC_OPS(xor, ^=, xor)
170 #define atomic_fetch_and_relaxed atomic_fetch_and_relaxed
171 #define atomic_fetch_or_relaxed atomic_fetch_or_relaxed
172 #define atomic_fetch_xor_relaxed atomic_fetch_xor_relaxed
175 #undef ATOMIC_FETCH_OP
176 #undef ATOMIC_OP_RETURN
180 * atomic_sub_if_positive - conditionally subtract integer from atomic variable
181 * @i: integer value to subtract
182 * @v: pointer of type atomic_t
184 * Atomically test @v and subtract @i if @v is greater or equal than @i.
185 * The function returns the old value of @v minus @i.
187 static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
191 smp_mb__before_llsc();
193 if (kernel_uses_llsc) {
196 __asm__ __volatile__(
198 " .set "MIPS_ISA_LEVEL" \n"
199 "1: ll %1, %2 # atomic_sub_if_positive\n"
201 " subu %0, %1, %3 \n"
205 " .set "MIPS_ISA_LEVEL" \n"
207 "\t" __scbeqz " %1, 1b \n"
210 : "=&r" (result), "=&r" (temp),
211 "+" GCC_OFF_SMALL_ASM() (v->counter)
216 raw_local_irq_save(flags);
221 raw_local_irq_restore(flags);
229 #define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
230 #define atomic_xchg(v, new) (xchg(&((v)->counter), (new)))
233 * atomic_dec_if_positive - decrement by 1 if old value positive
234 * @v: pointer of type atomic_t
236 #define atomic_dec_if_positive(v) atomic_sub_if_positive(1, v)
240 #define ATOMIC64_INIT(i) { (i) }
243 * atomic64_read - read atomic variable
244 * @v: pointer of type atomic64_t
247 #define atomic64_read(v) READ_ONCE((v)->counter)
250 * atomic64_set - set atomic variable
251 * @v: pointer of type atomic64_t
254 #define atomic64_set(v, i) WRITE_ONCE((v)->counter, (i))
256 #define ATOMIC64_OP(op, c_op, asm_op) \
257 static __inline__ void atomic64_##op(s64 i, atomic64_t * v) \
259 if (kernel_uses_llsc) { \
262 loongson_llsc_mb(); \
263 __asm__ __volatile__( \
265 " .set "MIPS_ISA_LEVEL" \n" \
266 "1: lld %0, %1 # atomic64_" #op " \n" \
267 " " #asm_op " %0, %2 \n" \
269 "\t" __scbeqz " %0, 1b \n" \
271 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
274 unsigned long flags; \
276 raw_local_irq_save(flags); \
278 raw_local_irq_restore(flags); \
282 #define ATOMIC64_OP_RETURN(op, c_op, asm_op) \
283 static __inline__ s64 atomic64_##op##_return_relaxed(s64 i, atomic64_t * v) \
287 if (kernel_uses_llsc) { \
290 loongson_llsc_mb(); \
291 __asm__ __volatile__( \
293 " .set "MIPS_ISA_LEVEL" \n" \
294 "1: lld %1, %2 # atomic64_" #op "_return\n" \
295 " " #asm_op " %0, %1, %3 \n" \
297 "\t" __scbeqz " %0, 1b \n" \
298 " " #asm_op " %0, %1, %3 \n" \
300 : "=&r" (result), "=&r" (temp), \
301 "+" GCC_OFF_SMALL_ASM() (v->counter) \
304 unsigned long flags; \
306 raw_local_irq_save(flags); \
307 result = v->counter; \
309 v->counter = result; \
310 raw_local_irq_restore(flags); \
316 #define ATOMIC64_FETCH_OP(op, c_op, asm_op) \
317 static __inline__ s64 atomic64_fetch_##op##_relaxed(s64 i, atomic64_t * v) \
321 if (kernel_uses_llsc) { \
324 loongson_llsc_mb(); \
325 __asm__ __volatile__( \
327 " .set "MIPS_ISA_LEVEL" \n" \
328 "1: lld %1, %2 # atomic64_fetch_" #op "\n" \
329 " " #asm_op " %0, %1, %3 \n" \
331 "\t" __scbeqz " %0, 1b \n" \
334 : "=&r" (result), "=&r" (temp), \
335 "+" GCC_OFF_SMALL_ASM() (v->counter) \
338 unsigned long flags; \
340 raw_local_irq_save(flags); \
341 result = v->counter; \
343 raw_local_irq_restore(flags); \
349 #define ATOMIC64_OPS(op, c_op, asm_op) \
350 ATOMIC64_OP(op, c_op, asm_op) \
351 ATOMIC64_OP_RETURN(op, c_op, asm_op) \
352 ATOMIC64_FETCH_OP(op, c_op, asm_op)
354 ATOMIC64_OPS(add, +=, daddu)
355 ATOMIC64_OPS(sub, -=, dsubu)
357 #define atomic64_add_return_relaxed atomic64_add_return_relaxed
358 #define atomic64_sub_return_relaxed atomic64_sub_return_relaxed
359 #define atomic64_fetch_add_relaxed atomic64_fetch_add_relaxed
360 #define atomic64_fetch_sub_relaxed atomic64_fetch_sub_relaxed
363 #define ATOMIC64_OPS(op, c_op, asm_op) \
364 ATOMIC64_OP(op, c_op, asm_op) \
365 ATOMIC64_FETCH_OP(op, c_op, asm_op)
367 ATOMIC64_OPS(and, &=, and)
368 ATOMIC64_OPS(or, |=, or)
369 ATOMIC64_OPS(xor, ^=, xor)
371 #define atomic64_fetch_and_relaxed atomic64_fetch_and_relaxed
372 #define atomic64_fetch_or_relaxed atomic64_fetch_or_relaxed
373 #define atomic64_fetch_xor_relaxed atomic64_fetch_xor_relaxed
376 #undef ATOMIC64_FETCH_OP
377 #undef ATOMIC64_OP_RETURN
381 * atomic64_sub_if_positive - conditionally subtract integer from atomic
383 * @i: integer value to subtract
384 * @v: pointer of type atomic64_t
386 * Atomically test @v and subtract @i if @v is greater or equal than @i.
387 * The function returns the old value of @v minus @i.
389 static __inline__ s64 atomic64_sub_if_positive(s64 i, atomic64_t * v)
393 smp_mb__before_llsc();
395 if (kernel_uses_llsc) {
398 __asm__ __volatile__(
400 " .set "MIPS_ISA_LEVEL" \n"
401 "1: lld %1, %2 # atomic64_sub_if_positive\n"
402 " dsubu %0, %1, %3 \n"
406 "\t" __scbeqz " %1, 1b \n"
409 : "=&r" (result), "=&r" (temp),
410 "+" GCC_OFF_SMALL_ASM() (v->counter)
415 raw_local_irq_save(flags);
420 raw_local_irq_restore(flags);
428 #define atomic64_cmpxchg(v, o, n) \
429 ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
430 #define atomic64_xchg(v, new) (xchg(&((v)->counter), (new)))
433 * atomic64_dec_if_positive - decrement by 1 if old value positive
434 * @v: pointer of type atomic64_t
436 #define atomic64_dec_if_positive(v) atomic64_sub_if_positive(1, v)
438 #endif /* CONFIG_64BIT */
440 #endif /* _ASM_ATOMIC_H */