2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (c) 1994 - 1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (c) 1999, 2000 Silicon Graphics, Inc.
12 #ifndef _LINUX_BITOPS_H
13 #error only <linux/bitops.h> can be included directly
16 #include <linux/compiler.h>
17 #include <linux/types.h>
18 #include <asm/barrier.h>
19 #include <asm/byteorder.h> /* sigh ... */
20 #include <asm/compiler.h>
21 #include <asm/cpu-features.h>
23 #include <asm/sgidefs.h>
27 * These are the "slower" versions of the functions and are in bitops.c.
28 * These functions call raw_local_irq_{save,restore}().
30 void __mips_set_bit(unsigned long nr, volatile unsigned long *addr);
31 void __mips_clear_bit(unsigned long nr, volatile unsigned long *addr);
32 void __mips_change_bit(unsigned long nr, volatile unsigned long *addr);
33 int __mips_test_and_set_bit(unsigned long nr,
34 volatile unsigned long *addr);
35 int __mips_test_and_set_bit_lock(unsigned long nr,
36 volatile unsigned long *addr);
37 int __mips_test_and_clear_bit(unsigned long nr,
38 volatile unsigned long *addr);
39 int __mips_test_and_change_bit(unsigned long nr,
40 volatile unsigned long *addr);
44 * set_bit - Atomically set a bit in memory
46 * @addr: the address to start counting from
48 * This function is atomic and may not be reordered. See __set_bit()
49 * if you do not require the atomic guarantees.
50 * Note that @nr may be almost arbitrarily large; this function is not
51 * restricted to acting on a single-word quantity.
53 static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
55 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
56 int bit = nr & SZLONG_MASK;
59 if (kernel_uses_llsc && R10000_LLSC_WAR) {
63 "1: " __LL "%0, %1 # set_bit \n"
68 : "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*m)
69 : "ir" (1UL << bit), GCC_OFF_SMALL_ASM() (*m));
70 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
71 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
75 " " __LL "%0, %1 # set_bit \n"
76 " " __INS "%0, %3, %2, 1 \n"
78 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
79 : "ir" (bit), "r" (~0));
80 } while (unlikely(!temp));
81 #endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */
82 } else if (kernel_uses_llsc) {
87 " .set "MIPS_ISA_ARCH_LEVEL" \n"
88 " " __LL "%0, %1 # set_bit \n"
92 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
94 } while (unlikely(!temp));
96 __mips_set_bit(nr, addr);
100 * clear_bit - Clears a bit in memory
102 * @addr: Address to start counting from
104 * clear_bit() is atomic and may not be reordered. However, it does
105 * not contain a memory barrier, so if it is used for locking purposes,
106 * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic()
107 * in order to ensure changes are visible on other processors.
109 static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
111 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
112 int bit = nr & SZLONG_MASK;
115 if (kernel_uses_llsc && R10000_LLSC_WAR) {
116 __asm__ __volatile__(
118 " .set arch=r4000 \n"
119 "1: " __LL "%0, %1 # clear_bit \n"
124 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
125 : "ir" (~(1UL << bit)));
126 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
127 } else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
130 __asm__ __volatile__(
131 " " __LL "%0, %1 # clear_bit \n"
132 " " __INS "%0, $0, %2, 1 \n"
134 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
136 } while (unlikely(!temp));
137 #endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */
138 } else if (kernel_uses_llsc) {
141 __asm__ __volatile__(
143 " .set "MIPS_ISA_ARCH_LEVEL" \n"
144 " " __LL "%0, %1 # clear_bit \n"
148 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
149 : "ir" (~(1UL << bit)));
150 } while (unlikely(!temp));
152 __mips_clear_bit(nr, addr);
156 * clear_bit_unlock - Clears a bit in memory
158 * @addr: Address to start counting from
160 * clear_bit() is atomic and implies release semantics before the memory
161 * operation. It can be used for an unlock.
163 static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
165 smp_mb__before_atomic();
170 * change_bit - Toggle a bit in memory
172 * @addr: Address to start counting from
174 * change_bit() is atomic and may not be reordered.
175 * Note that @nr may be almost arbitrarily large; this function is not
176 * restricted to acting on a single-word quantity.
178 static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
180 int bit = nr & SZLONG_MASK;
182 if (kernel_uses_llsc && R10000_LLSC_WAR) {
183 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
186 __asm__ __volatile__(
188 " .set arch=r4000 \n"
189 "1: " __LL "%0, %1 # change_bit \n"
194 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
195 : "ir" (1UL << bit));
196 } else if (kernel_uses_llsc) {
197 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
202 __asm__ __volatile__(
204 " .set "MIPS_ISA_ARCH_LEVEL" \n"
205 " " __LL "%0, %1 # change_bit \n"
209 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
210 : "ir" (1UL << bit));
211 } while (unlikely(!temp));
213 __mips_change_bit(nr, addr);
217 * test_and_set_bit - Set a bit and return its old value
219 * @addr: Address to count from
221 * This operation is atomic and cannot be reordered.
222 * It also implies a memory barrier.
224 static inline int test_and_set_bit(unsigned long nr,
225 volatile unsigned long *addr)
227 int bit = nr & SZLONG_MASK;
230 smp_mb__before_llsc();
232 if (kernel_uses_llsc && R10000_LLSC_WAR) {
233 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
236 __asm__ __volatile__(
238 " .set arch=r4000 \n"
239 "1: " __LL "%0, %1 # test_and_set_bit \n"
245 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
248 } else if (kernel_uses_llsc) {
249 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
253 __asm__ __volatile__(
255 " .set "MIPS_ISA_ARCH_LEVEL" \n"
256 " " __LL "%0, %1 # test_and_set_bit \n"
260 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
263 } while (unlikely(!res));
265 res = temp & (1UL << bit);
267 res = __mips_test_and_set_bit(nr, addr);
275 * test_and_set_bit_lock - Set a bit and return its old value
277 * @addr: Address to count from
279 * This operation is atomic and implies acquire ordering semantics
280 * after the memory operation.
282 static inline int test_and_set_bit_lock(unsigned long nr,
283 volatile unsigned long *addr)
285 int bit = nr & SZLONG_MASK;
288 if (kernel_uses_llsc && R10000_LLSC_WAR) {
289 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
292 __asm__ __volatile__(
294 " .set arch=r4000 \n"
295 "1: " __LL "%0, %1 # test_and_set_bit \n"
301 : "=&r" (temp), "+m" (*m), "=&r" (res)
304 } else if (kernel_uses_llsc) {
305 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
309 __asm__ __volatile__(
311 " .set "MIPS_ISA_ARCH_LEVEL" \n"
312 " " __LL "%0, %1 # test_and_set_bit \n"
316 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
319 } while (unlikely(!res));
321 res = temp & (1UL << bit);
323 res = __mips_test_and_set_bit_lock(nr, addr);
330 * test_and_clear_bit - Clear a bit and return its old value
332 * @addr: Address to count from
334 * This operation is atomic and cannot be reordered.
335 * It also implies a memory barrier.
337 static inline int test_and_clear_bit(unsigned long nr,
338 volatile unsigned long *addr)
340 int bit = nr & SZLONG_MASK;
343 smp_mb__before_llsc();
345 if (kernel_uses_llsc && R10000_LLSC_WAR) {
346 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
349 __asm__ __volatile__(
351 " .set arch=r4000 \n"
352 "1: " __LL "%0, %1 # test_and_clear_bit \n"
359 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
362 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
363 } else if (kernel_uses_llsc && __builtin_constant_p(nr)) {
364 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
368 __asm__ __volatile__(
369 " " __LL "%0, %1 # test_and_clear_bit \n"
370 " " __EXT "%2, %0, %3, 1 \n"
371 " " __INS "%0, $0, %3, 1 \n"
373 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
376 } while (unlikely(!temp));
378 } else if (kernel_uses_llsc) {
379 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
383 __asm__ __volatile__(
385 " .set "MIPS_ISA_ARCH_LEVEL" \n"
386 " " __LL "%0, %1 # test_and_clear_bit \n"
391 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
394 } while (unlikely(!res));
396 res = temp & (1UL << bit);
398 res = __mips_test_and_clear_bit(nr, addr);
406 * test_and_change_bit - Change a bit and return its old value
408 * @addr: Address to count from
410 * This operation is atomic and cannot be reordered.
411 * It also implies a memory barrier.
413 static inline int test_and_change_bit(unsigned long nr,
414 volatile unsigned long *addr)
416 int bit = nr & SZLONG_MASK;
419 smp_mb__before_llsc();
421 if (kernel_uses_llsc && R10000_LLSC_WAR) {
422 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
425 __asm__ __volatile__(
427 " .set arch=r4000 \n"
428 "1: " __LL "%0, %1 # test_and_change_bit \n"
434 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
437 } else if (kernel_uses_llsc) {
438 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
442 __asm__ __volatile__(
444 " .set "MIPS_ISA_ARCH_LEVEL" \n"
445 " " __LL "%0, %1 # test_and_change_bit \n"
447 " " __SC "\t%2, %1 \n"
449 : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
452 } while (unlikely(!res));
454 res = temp & (1UL << bit);
456 res = __mips_test_and_change_bit(nr, addr);
463 #include <asm-generic/bitops/non-atomic.h>
466 * __clear_bit_unlock - Clears a bit in memory
468 * @addr: Address to start counting from
470 * __clear_bit() is non-atomic and implies release semantics before the memory
471 * operation. It can be used for an unlock if no other CPUs can concurrently
472 * modify other bits in the word.
474 static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
476 smp_mb__before_llsc();
477 __clear_bit(nr, addr);
482 * Return the bit position (0..63) of the most significant 1 bit in a word
483 * Returns -1 if no 1 bit exists
485 static __always_inline unsigned long __fls(unsigned long word)
489 if (BITS_PER_LONG == 32 && !__builtin_constant_p(word) &&
490 __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
493 " .set "MIPS_ISA_LEVEL" \n"
502 if (BITS_PER_LONG == 64 && !__builtin_constant_p(word) &&
503 __builtin_constant_p(cpu_has_mips64) && cpu_has_mips64) {
506 " .set "MIPS_ISA_LEVEL" \n"
515 num = BITS_PER_LONG - 1;
517 #if BITS_PER_LONG == 64
518 if (!(word & (~0ul << 32))) {
523 if (!(word & (~0ul << (BITS_PER_LONG-16)))) {
527 if (!(word & (~0ul << (BITS_PER_LONG-8)))) {
531 if (!(word & (~0ul << (BITS_PER_LONG-4)))) {
535 if (!(word & (~0ul << (BITS_PER_LONG-2)))) {
539 if (!(word & (~0ul << (BITS_PER_LONG-1))))
545 * __ffs - find first bit in word.
546 * @word: The word to search
548 * Returns 0..SZLONG-1
549 * Undefined if no bit exists, so code should check against 0 first.
551 static __always_inline unsigned long __ffs(unsigned long word)
553 return __fls(word & -word);
557 * fls - find last bit set.
558 * @word: The word to search
560 * This is defined the same way as ffs.
561 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
563 static inline int fls(unsigned int x)
567 if (!__builtin_constant_p(x) &&
568 __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
571 " .set "MIPS_ISA_LEVEL" \n"
583 if (!(x & 0xffff0000u)) {
587 if (!(x & 0xff000000u)) {
591 if (!(x & 0xf0000000u)) {
595 if (!(x & 0xc0000000u)) {
599 if (!(x & 0x80000000u)) {
606 #include <asm-generic/bitops/fls64.h>
609 * ffs - find first bit set.
610 * @word: The word to search
612 * This is defined the same way as
613 * the libc and compiler builtin ffs routines, therefore
614 * differs in spirit from the above ffz (man ffs).
616 static inline int ffs(int word)
621 return fls(word & -word);
624 #include <asm-generic/bitops/ffz.h>
625 #include <asm-generic/bitops/find.h>
629 #include <asm-generic/bitops/sched.h>
631 #include <asm/arch_hweight.h>
632 #include <asm-generic/bitops/const_hweight.h>
634 #include <asm-generic/bitops/le.h>
635 #include <asm-generic/bitops/ext2-atomic.h>
637 #endif /* __KERNEL__ */
639 #endif /* _ASM_BITOPS_H */