arch/mips/include/asm/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/linkage.h>
  17 #include <linux/types.h>
  18 #include <asm/hazards.h>
  19 #include <asm/war.h>
  20
  21 /*
  22  * The following macros are especially useful for __asm__
  23  * inline assembler.
  24  */
  25 #ifndef __STR
  26 #define __STR(x) #x
  27 #endif
  28 #ifndef STR
  29 #define STR(x) __STR(x)
  30 #endif
  31
  32 /*
  33  *  Configure language
  34  */
  35 #ifdef __ASSEMBLY__
  36 #define _ULCAST_
  37 #else
  38 #define _ULCAST_ (unsigned long)
  39 #endif
  40
  41 /*
  42  * Coprocessor 0 register names
  43  */
  44 #define CP0_INDEX $0
  45 #define CP0_RANDOM $1
  46 #define CP0_ENTRYLO0 $2
  47 #define CP0_ENTRYLO1 $3
  48 #define CP0_CONF $3
  49 #define CP0_CONTEXT $4
  50 #define CP0_PAGEMASK $5
  51 #define CP0_SEGCTL0 $5, 2
  52 #define CP0_SEGCTL1 $5, 3
  53 #define CP0_SEGCTL2 $5, 4
  54 #define CP0_WIRED $6
  55 #define CP0_INFO $7
  56 #define CP0_HWRENA $7
  57 #define CP0_BADVADDR $8
  58 #define CP0_BADINSTR $8, 1
  59 #define CP0_COUNT $9
  60 #define CP0_ENTRYHI $10
  61 #define CP0_GUESTCTL1 $10, 4
  62 #define CP0_GUESTCTL2 $10, 5
  63 #define CP0_GUESTCTL3 $10, 6
  64 #define CP0_COMPARE $11
  65 #define CP0_GUESTCTL0EXT $11, 4
  66 #define CP0_STATUS $12
  67 #define CP0_GUESTCTL0 $12, 6
  68 #define CP0_GTOFFSET $12, 7
  69 #define CP0_CAUSE $13
  70 #define CP0_EPC $14
  71 #define CP0_PRID $15
  72 #define CP0_EBASE $15, 1
  73 #define CP0_CMGCRBASE $15, 3
  74 #define CP0_CONFIG $16
  75 #define CP0_CONFIG3 $16, 3
  76 #define CP0_CONFIG5 $16, 5
  77 #define CP0_LLADDR $17
  78 #define CP0_WATCHLO $18
  79 #define CP0_WATCHHI $19
  80 #define CP0_XCONTEXT $20
  81 #define CP0_FRAMEMASK $21
  82 #define CP0_DIAGNOSTIC $22
  83 #define CP0_DEBUG $23
  84 #define CP0_DEPC $24
  85 #define CP0_PERFORMANCE $25
  86 #define CP0_ECC $26
  87 #define CP0_CACHEERR $27
  88 #define CP0_TAGLO $28
  89 #define CP0_TAGHI $29
  90 #define CP0_ERROREPC $30
  91 #define CP0_DESAVE $31
  92
  93 /*
  94  * R4640/R4650 cp0 register names.  These registers are listed
  95  * here only for completeness; without MMU these CPUs are not useable
  96  * by Linux.  A future ELKS port might take make Linux run on them
  97  * though ...
  98  */
  99 #define CP0_IBASE $0
 100 #define CP0_IBOUND $1
 101 #define CP0_DBASE $2
 102 #define CP0_DBOUND $3
 103 #define CP0_CALG $17
 104 #define CP0_IWATCH $18
 105 #define CP0_DWATCH $19
 106
 107 /*
 108  * Coprocessor 0 Set 1 register names
 109  */
 110 #define CP0_S1_DERRADDR0  $26
 111 #define CP0_S1_DERRADDR1  $27
 112 #define CP0_S1_INTCONTROL $20
 113
 114 /*
 115  * Coprocessor 0 Set 2 register names
 116  */
 117 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 118
 119 /*
 120  * Coprocessor 0 Set 3 register names
 121  */
 122 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 123
 124 /*
 125  *  TX39 Series
 126  */
 127 #define CP0_TX39_CACHE  $7
 128
 129
 130 /* Generic EntryLo bit definitions */
 131 #define ENTRYLO_G               (_ULCAST_(1) << 0)
 132 #define ENTRYLO_V               (_ULCAST_(1) << 1)
 133 #define ENTRYLO_D               (_ULCAST_(1) << 2)
 134 #define ENTRYLO_C_SHIFT         3
 135 #define ENTRYLO_C               (_ULCAST_(7) << ENTRYLO_C_SHIFT)
 136
 137 /* R3000 EntryLo bit definitions */
 138 #define R3K_ENTRYLO_G           (_ULCAST_(1) << 8)
 139 #define R3K_ENTRYLO_V           (_ULCAST_(1) << 9)
 140 #define R3K_ENTRYLO_D           (_ULCAST_(1) << 10)
 141 #define R3K_ENTRYLO_N           (_ULCAST_(1) << 11)
 142
 143 /* MIPS32/64 EntryLo bit definitions */
 144 #define MIPS_ENTRYLO_PFN_SHIFT  6
 145 #define MIPS_ENTRYLO_XI         (_ULCAST_(1) << (BITS_PER_LONG - 2))
 146 #define MIPS_ENTRYLO_RI         (_ULCAST_(1) << (BITS_PER_LONG - 1))
 147
 148 /*
 149  * Values for PageMask register
 150  */
 151 #ifdef CONFIG_CPU_VR41XX
 152
 153 /* Why doesn't stupidity hurt ... */
 154
 155 #define PM_1K           0x00000000
 156 #define PM_4K           0x00001800
 157 #define PM_16K          0x00007800
 158 #define PM_64K          0x0001f800
 159 #define PM_256K         0x0007f800
 160
 161 #else
 162
 163 #define PM_4K           0x00000000
 164 #define PM_8K           0x00002000
 165 #define PM_16K          0x00006000
 166 #define PM_32K          0x0000e000
 167 #define PM_64K          0x0001e000
 168 #define PM_128K         0x0003e000
 169 #define PM_256K         0x0007e000
 170 #define PM_512K         0x000fe000
 171 #define PM_1M           0x001fe000
 172 #define PM_2M           0x003fe000
 173 #define PM_4M           0x007fe000
 174 #define PM_8M           0x00ffe000
 175 #define PM_16M          0x01ffe000
 176 #define PM_32M          0x03ffe000
 177 #define PM_64M          0x07ffe000
 178 #define PM_256M         0x1fffe000
 179 #define PM_1G           0x7fffe000
 180
 181 #endif
 182
 183 /*
 184  * Default page size for a given kernel configuration
 185  */
 186 #ifdef CONFIG_PAGE_SIZE_4KB
 187 #define PM_DEFAULT_MASK PM_4K
 188 #elif defined(CONFIG_PAGE_SIZE_8KB)
 189 #define PM_DEFAULT_MASK PM_8K
 190 #elif defined(CONFIG_PAGE_SIZE_16KB)
 191 #define PM_DEFAULT_MASK PM_16K
 192 #elif defined(CONFIG_PAGE_SIZE_32KB)
 193 #define PM_DEFAULT_MASK PM_32K
 194 #elif defined(CONFIG_PAGE_SIZE_64KB)
 195 #define PM_DEFAULT_MASK PM_64K
 196 #else
 197 #error Bad page size configuration!
 198 #endif
 199
 200 /*
 201  * Default huge tlb size for a given kernel configuration
 202  */
 203 #ifdef CONFIG_PAGE_SIZE_4KB
 204 #define PM_HUGE_MASK    PM_1M
 205 #elif defined(CONFIG_PAGE_SIZE_8KB)
 206 #define PM_HUGE_MASK    PM_4M
 207 #elif defined(CONFIG_PAGE_SIZE_16KB)
 208 #define PM_HUGE_MASK    PM_16M
 209 #elif defined(CONFIG_PAGE_SIZE_32KB)
 210 #define PM_HUGE_MASK    PM_64M
 211 #elif defined(CONFIG_PAGE_SIZE_64KB)
 212 #define PM_HUGE_MASK    PM_256M
 213 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 214 #error Bad page size configuration for hugetlbfs!
 215 #endif
 216
 217 /*
 218  * Wired register bits
 219  */
 220 #define MIPSR6_WIRED_LIMIT      (_ULCAST_(0xffff) << 16)
 221 #define MIPSR6_WIRED_WIRED      (_ULCAST_(0xffff) << 0)
 222
 223 /*
 224  * Values used for computation of new tlb entries
 225  */
 226 #define PL_4K           12
 227 #define PL_16K          14
 228 #define PL_64K          16
 229 #define PL_256K         18
 230 #define PL_1M           20
 231 #define PL_4M           22
 232 #define PL_16M          24
 233 #define PL_64M          26
 234 #define PL_256M         28
 235
 236 /*
 237  * PageGrain bits
 238  */
 239 #define PG_RIE          (_ULCAST_(1) <<  31)
 240 #define PG_XIE          (_ULCAST_(1) <<  30)
 241 #define PG_ELPA         (_ULCAST_(1) <<  29)
 242 #define PG_ESP          (_ULCAST_(1) <<  28)
 243 #define PG_IEC          (_ULCAST_(1) <<  27)
 244
 245 /* MIPS32/64 EntryHI bit definitions */
 246 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
 247 #define MIPS_ENTRYHI_ASIDX      (_ULCAST_(0x3) << 8)
 248 #define MIPS_ENTRYHI_ASID       (_ULCAST_(0xff) << 0)
 249
 250 /*
 251  * R4x00 interrupt enable / cause bits
 252  */
 253 #define IE_SW0          (_ULCAST_(1) <<  8)
 254 #define IE_SW1          (_ULCAST_(1) <<  9)
 255 #define IE_IRQ0         (_ULCAST_(1) << 10)
 256 #define IE_IRQ1         (_ULCAST_(1) << 11)
 257 #define IE_IRQ2         (_ULCAST_(1) << 12)
 258 #define IE_IRQ3         (_ULCAST_(1) << 13)
 259 #define IE_IRQ4         (_ULCAST_(1) << 14)
 260 #define IE_IRQ5         (_ULCAST_(1) << 15)
 261
 262 /*
 263  * R4x00 interrupt cause bits
 264  */
 265 #define C_SW0           (_ULCAST_(1) <<  8)
 266 #define C_SW1           (_ULCAST_(1) <<  9)
 267 #define C_IRQ0          (_ULCAST_(1) << 10)
 268 #define C_IRQ1          (_ULCAST_(1) << 11)
 269 #define C_IRQ2          (_ULCAST_(1) << 12)
 270 #define C_IRQ3          (_ULCAST_(1) << 13)
 271 #define C_IRQ4          (_ULCAST_(1) << 14)
 272 #define C_IRQ5          (_ULCAST_(1) << 15)
 273
 274 /*
 275  * Bitfields in the R4xx0 cp0 status register
 276  */
 277 #define ST0_IE                  0x00000001
 278 #define ST0_EXL                 0x00000002
 279 #define ST0_ERL                 0x00000004
 280 #define ST0_KSU                 0x00000018
 281 #  define KSU_USER              0x00000010
 282 #  define KSU_SUPERVISOR        0x00000008
 283 #  define KSU_KERNEL            0x00000000
 284 #define ST0_UX                  0x00000020
 285 #define ST0_SX                  0x00000040
 286 #define ST0_KX                  0x00000080
 287 #define ST0_DE                  0x00010000
 288 #define ST0_CE                  0x00020000
 289
 290 /*
 291  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 292  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 293  * processors.
 294  */
 295 #define ST0_CO                  0x08000000
 296
 297 /*
 298  * Bitfields in the R[23]000 cp0 status register.
 299  */
 300 #define ST0_IEC                 0x00000001
 301 #define ST0_KUC                 0x00000002
 302 #define ST0_IEP                 0x00000004
 303 #define ST0_KUP                 0x00000008
 304 #define ST0_IEO                 0x00000010
 305 #define ST0_KUO                 0x00000020
 306 /* bits 6 & 7 are reserved on R[23]000 */
 307 #define ST0_ISC                 0x00010000
 308 #define ST0_SWC                 0x00020000
 309 #define ST0_CM                  0x00080000
 310
 311 /*
 312  * Bits specific to the R4640/R4650
 313  */
 314 #define ST0_UM                  (_ULCAST_(1) <<  4)
 315 #define ST0_IL                  (_ULCAST_(1) << 23)
 316 #define ST0_DL                  (_ULCAST_(1) << 24)
 317
 318 /*
 319  * Enable the MIPS MDMX and DSP ASEs
 320  */
 321 #define ST0_MX                  0x01000000
 322
 323 /*
 324  * Status register bits available in all MIPS CPUs.
 325  */
 326 #define ST0_IM                  0x0000ff00
 327 #define  STATUSB_IP0            8
 328 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 329 #define  STATUSB_IP1            9
 330 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 331 #define  STATUSB_IP2            10
 332 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 333 #define  STATUSB_IP3            11
 334 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 335 #define  STATUSB_IP4            12
 336 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 337 #define  STATUSB_IP5            13
 338 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 339 #define  STATUSB_IP6            14
 340 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 341 #define  STATUSB_IP7            15
 342 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 343 #define  STATUSB_IP8            0
 344 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 345 #define  STATUSB_IP9            1
 346 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 347 #define  STATUSB_IP10           2
 348 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 349 #define  STATUSB_IP11           3
 350 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 351 #define  STATUSB_IP12           4
 352 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 353 #define  STATUSB_IP13           5
 354 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 355 #define  STATUSB_IP14           6
 356 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 357 #define  STATUSB_IP15           7
 358 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 359 #define ST0_CH                  0x00040000
 360 #define ST0_NMI                 0x00080000
 361 #define ST0_SR                  0x00100000
 362 #define ST0_TS                  0x00200000
 363 #define ST0_BEV                 0x00400000
 364 #define ST0_RE                  0x02000000
 365 #define ST0_FR                  0x04000000
 366 #define ST0_CU                  0xf0000000
 367 #define ST0_CU0                 0x10000000
 368 #define ST0_CU1                 0x20000000
 369 #define ST0_CU2                 0x40000000
 370 #define ST0_CU3                 0x80000000
 371 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 372
 373 /*
 374  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 375  */
 376 #define INTCTLB_IPFDC           23
 377 #define INTCTLF_IPFDC           (_ULCAST_(7) << INTCTLB_IPFDC)
 378 #define INTCTLB_IPPCI           26
 379 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 380 #define INTCTLB_IPTI            29
 381 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
 382
 383 /*
 384  * Bitfields and bit numbers in the coprocessor 0 cause register.
 385  *
 386  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 387  */
 388 #define CAUSEB_EXCCODE          2
 389 #define CAUSEF_EXCCODE          (_ULCAST_(31)  <<  2)
 390 #define CAUSEB_IP               8
 391 #define CAUSEF_IP               (_ULCAST_(255) <<  8)
 392 #define  CAUSEB_IP0             8
 393 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 394 #define  CAUSEB_IP1             9
 395 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 396 #define  CAUSEB_IP2             10
 397 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 398 #define  CAUSEB_IP3             11
 399 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 400 #define  CAUSEB_IP4             12
 401 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 402 #define  CAUSEB_IP5             13
 403 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 404 #define  CAUSEB_IP6             14
 405 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 406 #define  CAUSEB_IP7             15
 407 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 408 #define CAUSEB_FDCI             21
 409 #define CAUSEF_FDCI             (_ULCAST_(1)   << 21)
 410 #define CAUSEB_WP               22
 411 #define CAUSEF_WP               (_ULCAST_(1)   << 22)
 412 #define CAUSEB_IV               23
 413 #define CAUSEF_IV               (_ULCAST_(1)   << 23)
 414 #define CAUSEB_PCI              26
 415 #define CAUSEF_PCI              (_ULCAST_(1)   << 26)
 416 #define CAUSEB_DC               27
 417 #define CAUSEF_DC               (_ULCAST_(1)   << 27)
 418 #define CAUSEB_CE               28
 419 #define CAUSEF_CE               (_ULCAST_(3)   << 28)
 420 #define CAUSEB_TI               30
 421 #define CAUSEF_TI               (_ULCAST_(1)   << 30)
 422 #define CAUSEB_BD               31
 423 #define CAUSEF_BD               (_ULCAST_(1)   << 31)
 424
 425 /*
 426  * Cause.ExcCode trap codes.
 427  */
 428 #define EXCCODE_INT             0       /* Interrupt pending */
 429 #define EXCCODE_MOD             1       /* TLB modified fault */
 430 #define EXCCODE_TLBL            2       /* TLB miss on load or ifetch */
 431 #define EXCCODE_TLBS            3       /* TLB miss on a store */
 432 #define EXCCODE_ADEL            4       /* Address error on a load or ifetch */
 433 #define EXCCODE_ADES            5       /* Address error on a store */
 434 #define EXCCODE_IBE             6       /* Bus error on an ifetch */
 435 #define EXCCODE_DBE             7       /* Bus error on a load or store */
 436 #define EXCCODE_SYS             8       /* System call */
 437 #define EXCCODE_BP              9       /* Breakpoint */
 438 #define EXCCODE_RI              10      /* Reserved instruction exception */
 439 #define EXCCODE_CPU             11      /* Coprocessor unusable */
 440 #define EXCCODE_OV              12      /* Arithmetic overflow */
 441 #define EXCCODE_TR              13      /* Trap instruction */
 442 #define EXCCODE_MSAFPE          14      /* MSA floating point exception */
 443 #define EXCCODE_FPE             15      /* Floating point exception */
 444 #define EXCCODE_TLBRI           19      /* TLB Read-Inhibit exception */
 445 #define EXCCODE_TLBXI           20      /* TLB Execution-Inhibit exception */
 446 #define EXCCODE_MSADIS          21      /* MSA disabled exception */
 447 #define EXCCODE_MDMX            22      /* MDMX unusable exception */
 448 #define EXCCODE_WATCH           23      /* Watch address reference */
 449 #define EXCCODE_MCHECK          24      /* Machine check */
 450 #define EXCCODE_THREAD          25      /* Thread exceptions (MT) */
 451 #define EXCCODE_DSPDIS          26      /* DSP disabled exception */
 452 #define EXCCODE_GE              27      /* Virtualized guest exception (VZ) */
 453
 454 /* Implementation specific trap codes used by MIPS cores */
 455 #define MIPS_EXCCODE_TLBPAR     16      /* TLB parity error exception */
 456
 457 /*
 458  * Bits in the coprocessor 0 config register.
 459  */
 460 /* Generic bits.  */
 461 #define CONF_CM_CACHABLE_NO_WA          0
 462 #define CONF_CM_CACHABLE_WA             1
 463 #define CONF_CM_UNCACHED                2
 464 #define CONF_CM_CACHABLE_NONCOHERENT    3
 465 #define CONF_CM_CACHABLE_CE             4
 466 #define CONF_CM_CACHABLE_COW            5
 467 #define CONF_CM_CACHABLE_CUW            6
 468 #define CONF_CM_CACHABLE_ACCELERATED    7
 469 #define CONF_CM_CMASK                   7
 470 #define CONF_BE                 (_ULCAST_(1) << 15)
 471
 472 /* Bits common to various processors.  */
 473 #define CONF_CU                 (_ULCAST_(1) <<  3)
 474 #define CONF_DB                 (_ULCAST_(1) <<  4)
 475 #define CONF_IB                 (_ULCAST_(1) <<  5)
 476 #define CONF_DC                 (_ULCAST_(7) <<  6)
 477 #define CONF_IC                 (_ULCAST_(7) <<  9)
 478 #define CONF_EB                 (_ULCAST_(1) << 13)
 479 #define CONF_EM                 (_ULCAST_(1) << 14)
 480 #define CONF_SM                 (_ULCAST_(1) << 16)
 481 #define CONF_SC                 (_ULCAST_(1) << 17)
 482 #define CONF_EW                 (_ULCAST_(3) << 18)
 483 #define CONF_EP                 (_ULCAST_(15)<< 24)
 484 #define CONF_EC                 (_ULCAST_(7) << 28)
 485 #define CONF_CM                 (_ULCAST_(1) << 31)
 486
 487 /* Bits specific to the R4xx0.  */
 488 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 489 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 490 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 491
 492 /* Bits specific to the R5000.  */
 493 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 494 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 495
 496 /* Bits specific to the RM7000.  */
 497 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 498 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 499 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 500 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 501 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 502 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 503
 504 /* Bits specific to the R10000.  */
 505 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 506 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 507 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 508 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 509 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 510 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 511 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 512 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 513 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 514 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 515 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 516
 517 /* Bits specific to the VR41xx.  */
 518 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 519 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 520 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 521 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 522 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 523
 524 /* Bits specific to the R30xx.  */
 525 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 526 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 527 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 528 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 529 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 530 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 531 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 532 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 533 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 534
 535 /* Bits specific to the TX49.  */
 536 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 537 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 538 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 539 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 540
 541 /* Bits specific to the MIPS32/64 PRA.  */
 542 #define MIPS_CONF_VI            (_ULCAST_(1) <<  3)
 543 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 544 #define MIPS_CONF_MT_TLB        (_ULCAST_(1) <<  7)
 545 #define MIPS_CONF_MT_FTLB       (_ULCAST_(4) <<  7)
 546 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 547 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 548 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 549
 550 /*
 551  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 552  */
 553 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 554 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 555 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 556 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 557 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 558 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 559 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 560 #define MIPS_CONF1_DA_SHF       7
 561 #define MIPS_CONF1_DA_SZ        3
 562 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 563 #define MIPS_CONF1_DL_SHF       10
 564 #define MIPS_CONF1_DL_SZ        3
 565 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 566 #define MIPS_CONF1_DS_SHF       13
 567 #define MIPS_CONF1_DS_SZ        3
 568 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 569 #define MIPS_CONF1_IA_SHF       16
 570 #define MIPS_CONF1_IA_SZ        3
 571 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 572 #define MIPS_CONF1_IL_SHF       19
 573 #define MIPS_CONF1_IL_SZ        3
 574 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 575 #define MIPS_CONF1_IS_SHF       22
 576 #define MIPS_CONF1_IS_SZ        3
 577 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 578 #define MIPS_CONF1_TLBS_SHIFT   (25)
 579 #define MIPS_CONF1_TLBS_SIZE    (6)
 580 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 581
 582 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 583 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 584 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 585 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 586 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 587 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 588 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 589 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 590
 591 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 592 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 593 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 594 #define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
 595 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 596 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 597 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 598 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 599 #define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
 600 #define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
 601 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 602 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 603 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 604 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 605 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 606 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 607 #define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
 608 #define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
 609 #define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
 610 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 611 #define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
 612 #define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
 613 #define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
 614 #define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
 615 #define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
 616 #define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
 617 #define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
 618
 619 #define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
 620 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 621 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 622 #define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 623 #define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
 624 #define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 625 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
 626 /* bits 10:8 in FTLB-only configurations */
 627 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 628 /* bits 12:8 in VTLB-FTLB only configurations */
 629 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 630 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 631 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 632 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
 633 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
 634 #define MIPS_CONF4_KSCREXIST_SHIFT      (16)
 635 #define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
 636 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
 637 #define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 638 #define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
 639 #define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
 640 #define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
 641
 642 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 643 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
 644 #define MIPS_CONF5_MRP          (_ULCAST_(1) << 3)
 645 #define MIPS_CONF5_LLB          (_ULCAST_(1) << 4)
 646 #define MIPS_CONF5_MVH          (_ULCAST_(1) << 5)
 647 #define MIPS_CONF5_VP           (_ULCAST_(1) << 7)
 648 #define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
 649 #define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
 650 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
 651 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
 652 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
 653 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
 654
 655 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
 656 /* proAptiv FTLB on/off bit */
 657 #define MIPS_CONF6_FTLBEN       (_ULCAST_(1) << 15)
 658 /* Loongson-3 FTLB on/off bit */
 659 #define MIPS_CONF6_FTLBDIS      (_ULCAST_(1) << 22)
 660 /* FTLB probability bits */
 661 #define MIPS_CONF6_FTLBP_SHIFT  (16)
 662
 663 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 664
 665 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 666
 667 #define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
 668 #define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
 669
 670 /* WatchLo* register definitions */
 671 #define MIPS_WATCHLO_IRW        (_ULCAST_(0x7) << 0)
 672
 673 /* WatchHi* register definitions */
 674 #define MIPS_WATCHHI_M          (_ULCAST_(1) << 31)
 675 #define MIPS_WATCHHI_G          (_ULCAST_(1) << 30)
 676 #define MIPS_WATCHHI_WM         (_ULCAST_(0x3) << 28)
 677 #define MIPS_WATCHHI_WM_R_RVA   (_ULCAST_(0) << 28)
 678 #define MIPS_WATCHHI_WM_R_GPA   (_ULCAST_(1) << 28)
 679 #define MIPS_WATCHHI_WM_G_GVA   (_ULCAST_(2) << 28)
 680 #define MIPS_WATCHHI_EAS        (_ULCAST_(0x3) << 24)
 681 #define MIPS_WATCHHI_ASID       (_ULCAST_(0xff) << 16)
 682 #define MIPS_WATCHHI_MASK       (_ULCAST_(0x1ff) << 3)
 683 #define MIPS_WATCHHI_I          (_ULCAST_(1) << 2)
 684 #define MIPS_WATCHHI_R          (_ULCAST_(1) << 1)
 685 #define MIPS_WATCHHI_W          (_ULCAST_(1) << 0)
 686 #define MIPS_WATCHHI_IRW        (_ULCAST_(0x7) << 0)
 687
 688 /* PerfCnt control register definitions */
 689 #define MIPS_PERFCTRL_EXL       (_ULCAST_(1) << 0)
 690 #define MIPS_PERFCTRL_K         (_ULCAST_(1) << 1)
 691 #define MIPS_PERFCTRL_S         (_ULCAST_(1) << 2)
 692 #define MIPS_PERFCTRL_U         (_ULCAST_(1) << 3)
 693 #define MIPS_PERFCTRL_IE        (_ULCAST_(1) << 4)
 694 #define MIPS_PERFCTRL_EVENT_S   5
 695 #define MIPS_PERFCTRL_EVENT     (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
 696 #define MIPS_PERFCTRL_PCTD      (_ULCAST_(1) << 15)
 697 #define MIPS_PERFCTRL_EC        (_ULCAST_(0x3) << 23)
 698 #define MIPS_PERFCTRL_EC_R      (_ULCAST_(0) << 23)
 699 #define MIPS_PERFCTRL_EC_RI     (_ULCAST_(1) << 23)
 700 #define MIPS_PERFCTRL_EC_G      (_ULCAST_(2) << 23)
 701 #define MIPS_PERFCTRL_EC_GRI    (_ULCAST_(3) << 23)
 702 #define MIPS_PERFCTRL_W         (_ULCAST_(1) << 30)
 703 #define MIPS_PERFCTRL_M         (_ULCAST_(1) << 31)
 704
 705 /* PerfCnt control register MT extensions used by MIPS cores */
 706 #define MIPS_PERFCTRL_VPEID_S   16
 707 #define MIPS_PERFCTRL_VPEID     (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
 708 #define MIPS_PERFCTRL_TCID_S    22
 709 #define MIPS_PERFCTRL_TCID      (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
 710 #define MIPS_PERFCTRL_MT_EN     (_ULCAST_(0x3) << 20)
 711 #define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
 712 #define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
 713 #define MIPS_PERFCTRL_MT_EN_TC  (_ULCAST_(2) << 20)
 714
 715 /* PerfCnt control register MT extensions used by BMIPS5000 */
 716 #define BRCM_PERFCTRL_TC        (_ULCAST_(1) << 30)
 717
 718 /* PerfCnt control register MT extensions used by Netlogic XLR */
 719 #define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
 720
 721 /* MAAR bit definitions */
 722 #define MIPS_MAAR_ADDR          ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
 723 #define MIPS_MAAR_ADDR_SHIFT    12
 724 #define MIPS_MAAR_S             (_ULCAST_(1) << 1)
 725 #define MIPS_MAAR_V             (_ULCAST_(1) << 0)
 726
 727 /* EBase bit definitions */
 728 #define MIPS_EBASE_CPUNUM_SHIFT 0
 729 #define MIPS_EBASE_CPUNUM       (_ULCAST_(0x3ff) << 0)
 730 #define MIPS_EBASE_WG_SHIFT     11
 731 #define MIPS_EBASE_WG           (_ULCAST_(1) << 11)
 732 #define MIPS_EBASE_BASE_SHIFT   12
 733 #define MIPS_EBASE_BASE         (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
 734
 735 /* CMGCRBase bit definitions */
 736 #define MIPS_CMGCRB_BASE        11
 737 #define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 738
 739 /*
 740  * Bits in the MIPS32 Memory Segmentation registers.
 741  */
 742 #define MIPS_SEGCFG_PA_SHIFT    9
 743 #define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 744 #define MIPS_SEGCFG_AM_SHIFT    4
 745 #define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 746 #define MIPS_SEGCFG_EU_SHIFT    3
 747 #define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 748 #define MIPS_SEGCFG_C_SHIFT     0
 749 #define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 750
 751 #define MIPS_SEGCFG_UUSK        _ULCAST_(7)
 752 #define MIPS_SEGCFG_USK         _ULCAST_(5)
 753 #define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
 754 #define MIPS_SEGCFG_MUSK        _ULCAST_(3)
 755 #define MIPS_SEGCFG_MSK         _ULCAST_(2)
 756 #define MIPS_SEGCFG_MK          _ULCAST_(1)
 757 #define MIPS_SEGCFG_UK          _ULCAST_(0)
 758
 759 #define MIPS_PWFIELD_GDI_SHIFT  24
 760 #define MIPS_PWFIELD_GDI_MASK   0x3f000000
 761 #define MIPS_PWFIELD_UDI_SHIFT  18
 762 #define MIPS_PWFIELD_UDI_MASK   0x00fc0000
 763 #define MIPS_PWFIELD_MDI_SHIFT  12
 764 #define MIPS_PWFIELD_MDI_MASK   0x0003f000
 765 #define MIPS_PWFIELD_PTI_SHIFT  6
 766 #define MIPS_PWFIELD_PTI_MASK   0x00000fc0
 767 #define MIPS_PWFIELD_PTEI_SHIFT 0
 768 #define MIPS_PWFIELD_PTEI_MASK  0x0000003f
 769
 770 #define MIPS_PWSIZE_PS_SHIFT    30
 771 #define MIPS_PWSIZE_PS_MASK     0x40000000
 772 #define MIPS_PWSIZE_GDW_SHIFT   24
 773 #define MIPS_PWSIZE_GDW_MASK    0x3f000000
 774 #define MIPS_PWSIZE_UDW_SHIFT   18
 775 #define MIPS_PWSIZE_UDW_MASK    0x00fc0000
 776 #define MIPS_PWSIZE_MDW_SHIFT   12
 777 #define MIPS_PWSIZE_MDW_MASK    0x0003f000
 778 #define MIPS_PWSIZE_PTW_SHIFT   6
 779 #define MIPS_PWSIZE_PTW_MASK    0x00000fc0
 780 #define MIPS_PWSIZE_PTEW_SHIFT  0
 781 #define MIPS_PWSIZE_PTEW_MASK   0x0000003f
 782
 783 #define MIPS_PWCTL_PWEN_SHIFT   31
 784 #define MIPS_PWCTL_PWEN_MASK    0x80000000
 785 #define MIPS_PWCTL_XK_SHIFT     28
 786 #define MIPS_PWCTL_XK_MASK      0x10000000
 787 #define MIPS_PWCTL_XS_SHIFT     27
 788 #define MIPS_PWCTL_XS_MASK      0x08000000
 789 #define MIPS_PWCTL_XU_SHIFT     26
 790 #define MIPS_PWCTL_XU_MASK      0x04000000
 791 #define MIPS_PWCTL_DPH_SHIFT    7
 792 #define MIPS_PWCTL_DPH_MASK     0x00000080
 793 #define MIPS_PWCTL_HUGEPG_SHIFT 6
 794 #define MIPS_PWCTL_HUGEPG_MASK  0x00000060
 795 #define MIPS_PWCTL_PSN_SHIFT    0
 796 #define MIPS_PWCTL_PSN_MASK     0x0000003f
 797
 798 /* GuestCtl0 fields */
 799 #define MIPS_GCTL0_GM_SHIFT     31
 800 #define MIPS_GCTL0_GM           (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
 801 #define MIPS_GCTL0_RI_SHIFT     30
 802 #define MIPS_GCTL0_RI           (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
 803 #define MIPS_GCTL0_MC_SHIFT     29
 804 #define MIPS_GCTL0_MC           (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
 805 #define MIPS_GCTL0_CP0_SHIFT    28
 806 #define MIPS_GCTL0_CP0          (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
 807 #define MIPS_GCTL0_AT_SHIFT     26
 808 #define MIPS_GCTL0_AT           (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
 809 #define MIPS_GCTL0_GT_SHIFT     25
 810 #define MIPS_GCTL0_GT           (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
 811 #define MIPS_GCTL0_CG_SHIFT     24
 812 #define MIPS_GCTL0_CG           (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
 813 #define MIPS_GCTL0_CF_SHIFT     23
 814 #define MIPS_GCTL0_CF           (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
 815 #define MIPS_GCTL0_G1_SHIFT     22
 816 #define MIPS_GCTL0_G1           (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
 817 #define MIPS_GCTL0_G0E_SHIFT    19
 818 #define MIPS_GCTL0_G0E          (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
 819 #define MIPS_GCTL0_PT_SHIFT     18
 820 #define MIPS_GCTL0_PT           (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
 821 #define MIPS_GCTL0_RAD_SHIFT    9
 822 #define MIPS_GCTL0_RAD          (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
 823 #define MIPS_GCTL0_DRG_SHIFT    8
 824 #define MIPS_GCTL0_DRG          (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
 825 #define MIPS_GCTL0_G2_SHIFT     7
 826 #define MIPS_GCTL0_G2           (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
 827 #define MIPS_GCTL0_GEXC_SHIFT   2
 828 #define MIPS_GCTL0_GEXC         (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
 829 #define MIPS_GCTL0_SFC2_SHIFT   1
 830 #define MIPS_GCTL0_SFC2         (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
 831 #define MIPS_GCTL0_SFC1_SHIFT   0
 832 #define MIPS_GCTL0_SFC1         (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
 833
 834 /* GuestCtl0.AT Guest address translation control */
 835 #define MIPS_GCTL0_AT_ROOT      1  /* Guest MMU under Root control */
 836 #define MIPS_GCTL0_AT_GUEST     3  /* Guest MMU under Guest control */
 837
 838 /* GuestCtl0.GExcCode Hypervisor exception cause codes */
 839 #define MIPS_GCTL0_GEXC_GPSI    0  /* Guest Privileged Sensitive Instruction */
 840 #define MIPS_GCTL0_GEXC_GSFC    1  /* Guest Software Field Change */
 841 #define MIPS_GCTL0_GEXC_HC      2  /* Hypercall */
 842 #define MIPS_GCTL0_GEXC_GRR     3  /* Guest Reserved Instruction Redirect */
 843 #define MIPS_GCTL0_GEXC_GVA     8  /* Guest Virtual Address available */
 844 #define MIPS_GCTL0_GEXC_GHFC    9  /* Guest Hardware Field Change */
 845 #define MIPS_GCTL0_GEXC_GPA     10 /* Guest Physical Address available */
 846
 847 /* GuestCtl0Ext fields */
 848 #define MIPS_GCTL0EXT_RPW_SHIFT 8
 849 #define MIPS_GCTL0EXT_RPW       (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
 850 #define MIPS_GCTL0EXT_NCC_SHIFT 6
 851 #define MIPS_GCTL0EXT_NCC       (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
 852 #define MIPS_GCTL0EXT_CGI_SHIFT 4
 853 #define MIPS_GCTL0EXT_CGI       (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
 854 #define MIPS_GCTL0EXT_FCD_SHIFT 3
 855 #define MIPS_GCTL0EXT_FCD       (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
 856 #define MIPS_GCTL0EXT_OG_SHIFT  2
 857 #define MIPS_GCTL0EXT_OG        (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
 858 #define MIPS_GCTL0EXT_BG_SHIFT  1
 859 #define MIPS_GCTL0EXT_BG        (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
 860 #define MIPS_GCTL0EXT_MG_SHIFT  0
 861 #define MIPS_GCTL0EXT_MG        (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
 862
 863 /* GuestCtl0Ext.RPW Root page walk configuration */
 864 #define MIPS_GCTL0EXT_RPW_BOTH  0  /* Root PW for GPA->RPA and RVA->RPA */
 865 #define MIPS_GCTL0EXT_RPW_GPA   2  /* Root PW for GPA->RPA */
 866 #define MIPS_GCTL0EXT_RPW_RVA   3  /* Root PW for RVA->RPA */
 867
 868 /* GuestCtl0Ext.NCC Nested cache coherency attributes */
 869 #define MIPS_GCTL0EXT_NCC_IND   0  /* Guest CCA independent of Root CCA */
 870 #define MIPS_GCTL0EXT_NCC_MOD   1  /* Guest CCA modified by Root CCA */
 871
 872 /* GuestCtl1 fields */
 873 #define MIPS_GCTL1_ID_SHIFT     0
 874 #define MIPS_GCTL1_ID_WIDTH     8
 875 #define MIPS_GCTL1_ID           (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
 876 #define MIPS_GCTL1_RID_SHIFT    16
 877 #define MIPS_GCTL1_RID_WIDTH    8
 878 #define MIPS_GCTL1_RID          (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
 879 #define MIPS_GCTL1_EID_SHIFT    24
 880 #define MIPS_GCTL1_EID_WIDTH    8
 881 #define MIPS_GCTL1_EID          (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
 882
 883 /* GuestID reserved for root context */
 884 #define MIPS_GCTL1_ROOT_GUESTID 0
 885
 886 /* CDMMBase register bit definitions */
 887 #define MIPS_CDMMBASE_SIZE_SHIFT 0
 888 #define MIPS_CDMMBASE_SIZE      (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
 889 #define MIPS_CDMMBASE_CI        (_ULCAST_(1) << 9)
 890 #define MIPS_CDMMBASE_EN        (_ULCAST_(1) << 10)
 891 #define MIPS_CDMMBASE_ADDR_SHIFT 11
 892 #define MIPS_CDMMBASE_ADDR_START 15
 893
 894 /* RDHWR register numbers */
 895 #define MIPS_HWR_CPUNUM         0       /* CPU number */
 896 #define MIPS_HWR_SYNCISTEP      1       /* SYNCI step size */
 897 #define MIPS_HWR_CC             2       /* Cycle counter */
 898 #define MIPS_HWR_CCRES          3       /* Cycle counter resolution */
 899 #define MIPS_HWR_ULR            29      /* UserLocal */
 900 #define MIPS_HWR_IMPL1          30      /* Implementation dependent */
 901 #define MIPS_HWR_IMPL2          31      /* Implementation dependent */
 902
 903 /* Bits in HWREna register */
 904 #define MIPS_HWRENA_CPUNUM      (_ULCAST_(1) << MIPS_HWR_CPUNUM)
 905 #define MIPS_HWRENA_SYNCISTEP   (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
 906 #define MIPS_HWRENA_CC          (_ULCAST_(1) << MIPS_HWR_CC)
 907 #define MIPS_HWRENA_CCRES       (_ULCAST_(1) << MIPS_HWR_CCRES)
 908 #define MIPS_HWRENA_ULR         (_ULCAST_(1) << MIPS_HWR_ULR)
 909 #define MIPS_HWRENA_IMPL1       (_ULCAST_(1) << MIPS_HWR_IMPL1)
 910 #define MIPS_HWRENA_IMPL2       (_ULCAST_(1) << MIPS_HWR_IMPL2)
 911
 912 /*
 913  * Bitfields in the TX39 family CP0 Configuration Register 3
 914  */
 915 #define TX39_CONF_ICS_SHIFT     19
 916 #define TX39_CONF_ICS_MASK      0x00380000
 917 #define TX39_CONF_ICS_1KB       0x00000000
 918 #define TX39_CONF_ICS_2KB       0x00080000
 919 #define TX39_CONF_ICS_4KB       0x00100000
 920 #define TX39_CONF_ICS_8KB       0x00180000
 921 #define TX39_CONF_ICS_16KB      0x00200000
 922
 923 #define TX39_CONF_DCS_SHIFT     16
 924 #define TX39_CONF_DCS_MASK      0x00070000
 925 #define TX39_CONF_DCS_1KB       0x00000000
 926 #define TX39_CONF_DCS_2KB       0x00010000
 927 #define TX39_CONF_DCS_4KB       0x00020000
 928 #define TX39_CONF_DCS_8KB       0x00030000
 929 #define TX39_CONF_DCS_16KB      0x00040000
 930
 931 #define TX39_CONF_CWFON         0x00004000
 932 #define TX39_CONF_WBON          0x00002000
 933 #define TX39_CONF_RF_SHIFT      10
 934 #define TX39_CONF_RF_MASK       0x00000c00
 935 #define TX39_CONF_DOZE          0x00000200
 936 #define TX39_CONF_HALT          0x00000100
 937 #define TX39_CONF_LOCK          0x00000080
 938 #define TX39_CONF_ICE           0x00000020
 939 #define TX39_CONF_DCE           0x00000010
 940 #define TX39_CONF_IRSIZE_SHIFT  2
 941 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 942 #define TX39_CONF_DRSIZE_SHIFT  0
 943 #define TX39_CONF_DRSIZE_MASK   0x00000003
 944
 945 /*
 946  * Interesting Bits in the R10K CP0 Branch Diagnostic Register
 947  */
 948 /* Disable Branch Target Address Cache */
 949 #define R10K_DIAG_D_BTAC        (_ULCAST_(1) << 27)
 950 /* Enable Branch Prediction Global History */
 951 #define R10K_DIAG_E_GHIST       (_ULCAST_(1) << 26)
 952 /* Disable Branch Return Cache */
 953 #define R10K_DIAG_D_BRC         (_ULCAST_(1) << 22)
 954
 955 /* Flush ITLB */
 956 #define LOONGSON_DIAG_ITLB      (_ULCAST_(1) << 2)
 957 /* Flush DTLB */
 958 #define LOONGSON_DIAG_DTLB      (_ULCAST_(1) << 3)
 959 /* Flush VTLB */
 960 #define LOONGSON_DIAG_VTLB      (_ULCAST_(1) << 12)
 961 /* Flush FTLB */
 962 #define LOONGSON_DIAG_FTLB      (_ULCAST_(1) << 13)
 963
 964 /*
 965  * Coprocessor 1 (FPU) register names
 966  */
 967 #define CP1_REVISION    $0
 968 #define CP1_UFR         $1
 969 #define CP1_UNFR        $4
 970 #define CP1_FCCR        $25
 971 #define CP1_FEXR        $26
 972 #define CP1_FENR        $28
 973 #define CP1_STATUS      $31
 974
 975
 976 /*
 977  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 978  */
 979 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
 980 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
 981 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
 982 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
 983 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
 984 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
 985 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
 986 #define MIPS_FPIR_HAS2008       (_ULCAST_(1) << 23)
 987 #define MIPS_FPIR_UFRP          (_ULCAST_(1) << 28)
 988 #define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
 989
 990 /*
 991  * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
 992  */
 993 #define MIPS_FCCR_CONDX_S       0
 994 #define MIPS_FCCR_CONDX         (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
 995 #define MIPS_FCCR_COND0_S       0
 996 #define MIPS_FCCR_COND0         (_ULCAST_(1) << MIPS_FCCR_COND0_S)
 997 #define MIPS_FCCR_COND1_S       1
 998 #define MIPS_FCCR_COND1         (_ULCAST_(1) << MIPS_FCCR_COND1_S)
 999 #define MIPS_FCCR_COND2_S       2
1000 #define MIPS_FCCR_COND2         (_ULCAST_(1) << MIPS_FCCR_COND2_S)
1001 #define MIPS_FCCR_COND3_S       3
1002 #define MIPS_FCCR_COND3         (_ULCAST_(1) << MIPS_FCCR_COND3_S)
1003 #define MIPS_FCCR_COND4_S       4
1004 #define MIPS_FCCR_COND4         (_ULCAST_(1) << MIPS_FCCR_COND4_S)
1005 #define MIPS_FCCR_COND5_S       5
1006 #define MIPS_FCCR_COND5         (_ULCAST_(1) << MIPS_FCCR_COND5_S)
1007 #define MIPS_FCCR_COND6_S       6
1008 #define MIPS_FCCR_COND6         (_ULCAST_(1) << MIPS_FCCR_COND6_S)
1009 #define MIPS_FCCR_COND7_S       7
1010 #define MIPS_FCCR_COND7         (_ULCAST_(1) << MIPS_FCCR_COND7_S)
1011
1012 /*
1013  * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
1014  */
1015 #define MIPS_FENR_FS_S          2
1016 #define MIPS_FENR_FS            (_ULCAST_(1) << MIPS_FENR_FS_S)
1017
1018 /*
1019  * FPU Status Register Values
1020  */
1021 #define FPU_CSR_COND_S  23                                      /* $fcc0 */
1022 #define FPU_CSR_COND    (_ULCAST_(1) << FPU_CSR_COND_S)
1023
1024 #define FPU_CSR_FS_S    24              /* flush denormalised results to 0 */
1025 #define FPU_CSR_FS      (_ULCAST_(1) << FPU_CSR_FS_S)
1026
1027 #define FPU_CSR_CONDX_S 25                                      /* $fcc[7:1] */
1028 #define FPU_CSR_CONDX   (_ULCAST_(127) << FPU_CSR_CONDX_S)
1029 #define FPU_CSR_COND1_S 25                                      /* $fcc1 */
1030 #define FPU_CSR_COND1   (_ULCAST_(1) << FPU_CSR_COND1_S)
1031 #define FPU_CSR_COND2_S 26                                      /* $fcc2 */
1032 #define FPU_CSR_COND2   (_ULCAST_(1) << FPU_CSR_COND2_S)
1033 #define FPU_CSR_COND3_S 27                                      /* $fcc3 */
1034 #define FPU_CSR_COND3   (_ULCAST_(1) << FPU_CSR_COND3_S)
1035 #define FPU_CSR_COND4_S 28                                      /* $fcc4 */
1036 #define FPU_CSR_COND4   (_ULCAST_(1) << FPU_CSR_COND4_S)
1037 #define FPU_CSR_COND5_S 29                                      /* $fcc5 */
1038 #define FPU_CSR_COND5   (_ULCAST_(1) << FPU_CSR_COND5_S)
1039 #define FPU_CSR_COND6_S 30                                      /* $fcc6 */
1040 #define FPU_CSR_COND6   (_ULCAST_(1) << FPU_CSR_COND6_S)
1041 #define FPU_CSR_COND7_S 31                                      /* $fcc7 */
1042 #define FPU_CSR_COND7   (_ULCAST_(1) << FPU_CSR_COND7_S)
1043
1044 /*
1045  * Bits 22:20 of the FPU Status Register will be read as 0,
1046  * and should be written as zero.
1047  */
1048 #define FPU_CSR_RSVD    (_ULCAST_(7) << 20)
1049
1050 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1051 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1052
1053 /*
1054  * X the exception cause indicator
1055  * E the exception enable
1056  * S the sticky/flag bit
1057 */
1058 #define FPU_CSR_ALL_X   0x0003f000
1059 #define FPU_CSR_UNI_X   0x00020000
1060 #define FPU_CSR_INV_X   0x00010000
1061 #define FPU_CSR_DIV_X   0x00008000
1062 #define FPU_CSR_OVF_X   0x00004000
1063 #define FPU_CSR_UDF_X   0x00002000
1064 #define FPU_CSR_INE_X   0x00001000
1065
1066 #define FPU_CSR_ALL_E   0x00000f80
1067 #define FPU_CSR_INV_E   0x00000800
1068 #define FPU_CSR_DIV_E   0x00000400
1069 #define FPU_CSR_OVF_E   0x00000200
1070 #define FPU_CSR_UDF_E   0x00000100
1071 #define FPU_CSR_INE_E   0x00000080
1072
1073 #define FPU_CSR_ALL_S   0x0000007c
1074 #define FPU_CSR_INV_S   0x00000040
1075 #define FPU_CSR_DIV_S   0x00000020
1076 #define FPU_CSR_OVF_S   0x00000010
1077 #define FPU_CSR_UDF_S   0x00000008
1078 #define FPU_CSR_INE_S   0x00000004
1079
1080 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1081 #define FPU_CSR_RM      0x00000003
1082 #define FPU_CSR_RN      0x0     /* nearest */
1083 #define FPU_CSR_RZ      0x1     /* towards zero */
1084 #define FPU_CSR_RU      0x2     /* towards +Infinity */
1085 #define FPU_CSR_RD      0x3     /* towards -Infinity */
1086
1087
1088 #ifndef __ASSEMBLY__
1089
1090 /*
1091  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1092  */
1093 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1094     defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1095 #define get_isa16_mode(x)               ((x) & 0x1)
1096 #define msk_isa16_mode(x)               ((x) & ~0x1)
1097 #define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
1098 #else
1099 #define get_isa16_mode(x)               0
1100 #define msk_isa16_mode(x)               (x)
1101 #define set_isa16_mode(x)               do { } while(0)
1102 #endif
1103
1104 /*
1105  * microMIPS instructions can be 16-bit or 32-bit in length. This
1106  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1107  */
1108 static inline int mm_insn_16bit(u16 insn)
1109 {
1110         u16 opcode = (insn >> 10) & 0x7;
1111
1112         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1113 }
1114
1115 /*
1116  * Helper macros for generating raw instruction encodings in inline asm.
1117  */
1118 #ifdef CONFIG_CPU_MICROMIPS
1119 #define _ASM_INSN16_IF_MM(_enc)                 \
1120         ".insn\n\t"                             \
1121         ".hword (" #_enc ")\n\t"
1122 #define _ASM_INSN32_IF_MM(_enc)                 \
1123         ".insn\n\t"                             \
1124         ".hword ((" #_enc ") >> 16)\n\t"        \
1125         ".hword ((" #_enc ") & 0xffff)\n\t"
1126 #else
1127 #define _ASM_INSN_IF_MIPS(_enc)                 \
1128         ".insn\n\t"                             \
1129         ".word (" #_enc ")\n\t"
1130 #endif
1131
1132 #ifndef _ASM_INSN16_IF_MM
1133 #define _ASM_INSN16_IF_MM(_enc)
1134 #endif
1135 #ifndef _ASM_INSN32_IF_MM
1136 #define _ASM_INSN32_IF_MM(_enc)
1137 #endif
1138 #ifndef _ASM_INSN_IF_MIPS
1139 #define _ASM_INSN_IF_MIPS(_enc)
1140 #endif
1141
1142 /*
1143  * TLB Invalidate Flush
1144  */
1145 static inline void tlbinvf(void)
1146 {
1147         __asm__ __volatile__(
1148                 ".set push\n\t"
1149                 ".set noreorder\n\t"
1150                 "# tlbinvf\n\t"
1151                 _ASM_INSN_IF_MIPS(0x42000004)
1152                 _ASM_INSN32_IF_MM(0x0000537c)
1153                 ".set pop");
1154 }
1155
1156
1157 /*
1158  * Functions to access the R10000 performance counters.  These are basically
1159  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1160  * performance counter number encoded into bits 1 ... 5 of the instruction.
1161  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1162  * disassembler these will look like an access to sel 0 or 1.
1163  */
1164 #define read_r10k_perf_cntr(counter)                            \
1165 ({                                                              \
1166         unsigned int __res;                                     \
1167         __asm__ __volatile__(                                   \
1168         "mfpc\t%0, %1"                                          \
1169         : "=r" (__res)                                          \
1170         : "i" (counter));                                       \
1171                                                                 \
1172         __res;                                                  \
1173 })
1174
1175 #define write_r10k_perf_cntr(counter,val)                       \
1176 do {                                                            \
1177         __asm__ __volatile__(                                   \
1178         "mtpc\t%0, %1"                                          \
1179         :                                                       \
1180         : "r" (val), "i" (counter));                            \
1181 } while (0)
1182
1183 #define read_r10k_perf_event(counter)                           \
1184 ({                                                              \
1185         unsigned int __res;                                     \
1186         __asm__ __volatile__(                                   \
1187         "mfps\t%0, %1"                                          \
1188         : "=r" (__res)                                          \
1189         : "i" (counter));                                       \
1190                                                                 \
1191         __res;                                                  \
1192 })
1193
1194 #define write_r10k_perf_cntl(counter,val)                       \
1195 do {                                                            \
1196         __asm__ __volatile__(                                   \
1197         "mtps\t%0, %1"                                          \
1198         :                                                       \
1199         : "r" (val), "i" (counter));                            \
1200 } while (0)
1201
1202
1203 /*
1204  * Macros to access the system control coprocessor
1205  */
1206
1207 #define __read_32bit_c0_register(source, sel)                           \
1208 ({ unsigned int __res;                                                  \
1209         if (sel == 0)                                                   \
1210                 __asm__ __volatile__(                                   \
1211                         "mfc0\t%0, " #source "\n\t"                     \
1212                         : "=r" (__res));                                \
1213         else                                                            \
1214                 __asm__ __volatile__(                                   \
1215                         ".set\tmips32\n\t"                              \
1216                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
1217                         ".set\tmips0\n\t"                               \
1218                         : "=r" (__res));                                \
1219         __res;                                                          \
1220 })
1221
1222 #define __read_64bit_c0_register(source, sel)                           \
1223 ({ unsigned long long __res;                                            \
1224         if (sizeof(unsigned long) == 4)                                 \
1225                 __res = __read_64bit_c0_split(source, sel);             \
1226         else if (sel == 0)                                              \
1227                 __asm__ __volatile__(                                   \
1228                         ".set\tmips3\n\t"                               \
1229                         "dmfc0\t%0, " #source "\n\t"                    \
1230                         ".set\tmips0"                                   \
1231                         : "=r" (__res));                                \
1232         else                                                            \
1233                 __asm__ __volatile__(                                   \
1234                         ".set\tmips64\n\t"                              \
1235                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
1236                         ".set\tmips0"                                   \
1237                         : "=r" (__res));                                \
1238         __res;                                                          \
1239 })
1240
1241 #define __write_32bit_c0_register(register, sel, value)                 \
1242 do {                                                                    \
1243         if (sel == 0)                                                   \
1244                 __asm__ __volatile__(                                   \
1245                         "mtc0\t%z0, " #register "\n\t"                  \
1246                         : : "Jr" ((unsigned int)(value)));              \
1247         else                                                            \
1248                 __asm__ __volatile__(                                   \
1249                         ".set\tmips32\n\t"                              \
1250                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
1251                         ".set\tmips0"                                   \
1252                         : : "Jr" ((unsigned int)(value)));              \
1253 } while (0)
1254
1255 #define __write_64bit_c0_register(register, sel, value)                 \
1256 do {                                                                    \
1257         if (sizeof(unsigned long) == 4)                                 \
1258                 __write_64bit_c0_split(register, sel, value);           \
1259         else if (sel == 0)                                              \
1260                 __asm__ __volatile__(                                   \
1261                         ".set\tmips3\n\t"                               \
1262                         "dmtc0\t%z0, " #register "\n\t"                 \
1263                         ".set\tmips0"                                   \
1264                         : : "Jr" (value));                              \
1265         else                                                            \
1266                 __asm__ __volatile__(                                   \
1267                         ".set\tmips64\n\t"                              \
1268                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
1269                         ".set\tmips0"                                   \
1270                         : : "Jr" (value));                              \
1271 } while (0)
1272
1273 #define __read_ulong_c0_register(reg, sel)                              \
1274         ((sizeof(unsigned long) == 4) ?                                 \
1275         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
1276         (unsigned long) __read_64bit_c0_register(reg, sel))
1277
1278 #define __write_ulong_c0_register(reg, sel, val)                        \
1279 do {                                                                    \
1280         if (sizeof(unsigned long) == 4)                                 \
1281                 __write_32bit_c0_register(reg, sel, val);               \
1282         else                                                            \
1283                 __write_64bit_c0_register(reg, sel, val);               \
1284 } while (0)
1285
1286 /*
1287  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1288  */
1289 #define __read_32bit_c0_ctrl_register(source)                           \
1290 ({ unsigned int __res;                                                  \
1291         __asm__ __volatile__(                                           \
1292                 "cfc0\t%0, " #source "\n\t"                             \
1293                 : "=r" (__res));                                        \
1294         __res;                                                          \
1295 })
1296
1297 #define __write_32bit_c0_ctrl_register(register, value)                 \
1298 do {                                                                    \
1299         __asm__ __volatile__(                                           \
1300                 "ctc0\t%z0, " #register "\n\t"                          \
1301                 : : "Jr" ((unsigned int)(value)));                      \
1302 } while (0)
1303
1304 /*
1305  * These versions are only needed for systems with more than 38 bits of
1306  * physical address space running the 32-bit kernel.  That's none atm :-)
1307  */
1308 #define __read_64bit_c0_split(source, sel)                              \
1309 ({                                                                      \
1310         unsigned long long __val;                                       \
1311         unsigned long __flags;                                          \
1312                                                                         \
1313         local_irq_save(__flags);                                        \
1314         if (sel == 0)                                                   \
1315                 __asm__ __volatile__(                                   \
1316                         ".set\tmips64\n\t"                              \
1317                         "dmfc0\t%M0, " #source "\n\t"                   \
1318                         "dsll\t%L0, %M0, 32\n\t"                        \
1319                         "dsra\t%M0, %M0, 32\n\t"                        \
1320                         "dsra\t%L0, %L0, 32\n\t"                        \
1321                         ".set\tmips0"                                   \
1322                         : "=r" (__val));                                \
1323         else                                                            \
1324                 __asm__ __volatile__(                                   \
1325                         ".set\tmips64\n\t"                              \
1326                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
1327                         "dsll\t%L0, %M0, 32\n\t"                        \
1328                         "dsra\t%M0, %M0, 32\n\t"                        \
1329                         "dsra\t%L0, %L0, 32\n\t"                        \
1330                         ".set\tmips0"                                   \
1331                         : "=r" (__val));                                \
1332         local_irq_restore(__flags);                                     \
1333                                                                         \
1334         __val;                                                          \
1335 })
1336
1337 #define __write_64bit_c0_split(source, sel, val)                        \
1338 do {                                                                    \
1339         unsigned long __flags;                                          \
1340                                                                         \
1341         local_irq_save(__flags);                                        \
1342         if (sel == 0)                                                   \
1343                 __asm__ __volatile__(                                   \
1344                         ".set\tmips64\n\t"                              \
1345                         "dsll\t%L0, %L0, 32\n\t"                        \
1346                         "dsrl\t%L0, %L0, 32\n\t"                        \
1347                         "dsll\t%M0, %M0, 32\n\t"                        \
1348                         "or\t%L0, %L0, %M0\n\t"                         \
1349                         "dmtc0\t%L0, " #source "\n\t"                   \
1350                         ".set\tmips0"                                   \
1351                         : : "r" (val));                                 \
1352         else                                                            \
1353                 __asm__ __volatile__(                                   \
1354                         ".set\tmips64\n\t"                              \
1355                         "dsll\t%L0, %L0, 32\n\t"                        \
1356                         "dsrl\t%L0, %L0, 32\n\t"                        \
1357                         "dsll\t%M0, %M0, 32\n\t"                        \
1358                         "or\t%L0, %L0, %M0\n\t"                         \
1359                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
1360                         ".set\tmips0"                                   \
1361                         : : "r" (val));                                 \
1362         local_irq_restore(__flags);                                     \
1363 } while (0)
1364
1365 #define __readx_32bit_c0_register(source)                               \
1366 ({                                                                      \
1367         unsigned int __res;                                             \
1368                                                                         \
1369         __asm__ __volatile__(                                           \
1370         "       .set    push                                    \n"     \
1371         "       .set    noat                                    \n"     \
1372         "       .set    mips32r2                                \n"     \
1373         "       # mfhc0 $1, %1                                  \n"     \
1374         _ASM_INSN_IF_MIPS(0x40410000 | ((%1 & 0x1f) << 11))             \
1375         _ASM_INSN32_IF_MM(0x002000f4 | ((%1 & 0x1f) << 16))             \
1376         "       move    %0, $1                                  \n"     \
1377         "       .set    pop                                     \n"     \
1378         : "=r" (__res)                                                  \
1379         : "i" (source));                                                \
1380         __res;                                                          \
1381 })
1382
1383 #define __writex_32bit_c0_register(register, value)                     \
1384 do {                                                                    \
1385         __asm__ __volatile__(                                           \
1386         "       .set    push                                    \n"     \
1387         "       .set    noat                                    \n"     \
1388         "       .set    mips32r2                                \n"     \
1389         "       move    $1, %0                                  \n"     \
1390         "       # mthc0 $1, %1                                  \n"     \
1391         _ASM_INSN_IF_MIPS(0x40c10000 | ((%1 & 0x1f) << 11))             \
1392         _ASM_INSN32_IF_MM(0x002002f4 | ((%1 & 0x1f) << 16))             \
1393         "       .set    pop                                     \n"     \
1394         :                                                               \
1395         : "r" (value), "i" (register));                                 \
1396 } while (0)
1397
1398 #define read_c0_index()         __read_32bit_c0_register($0, 0)
1399 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
1400
1401 #define read_c0_random()        __read_32bit_c0_register($1, 0)
1402 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
1403
1404 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
1405 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
1406
1407 #define readx_c0_entrylo0()     __readx_32bit_c0_register(2)
1408 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1409
1410 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
1411 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
1412
1413 #define readx_c0_entrylo1()     __readx_32bit_c0_register(3)
1414 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1415
1416 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
1417 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
1418
1419 #define read_c0_context()       __read_ulong_c0_register($4, 0)
1420 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
1421
1422 #define read_c0_contextconfig()         __read_32bit_c0_register($4, 1)
1423 #define write_c0_contextconfig(val)     __write_32bit_c0_register($4, 1, val)
1424
1425 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
1426 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1427
1428 #define read_c0_xcontextconfig()        __read_ulong_c0_register($4, 3)
1429 #define write_c0_xcontextconfig(val)    __write_ulong_c0_register($4, 3, val)
1430
1431 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
1432 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
1433
1434 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
1435 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1436
1437 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
1438 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
1439
1440 #define read_c0_info()          __read_32bit_c0_register($7, 0)
1441
1442 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
1443 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
1444
1445 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
1446 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
1447
1448 #define read_c0_badinstr()      __read_32bit_c0_register($8, 1)
1449 #define read_c0_badinstrp()     __read_32bit_c0_register($8, 2)
1450
1451 #define read_c0_count()         __read_32bit_c0_register($9, 0)
1452 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
1453
1454 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
1455 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
1456
1457 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
1458 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
1459
1460 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
1461 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
1462
1463 #define read_c0_guestctl1()     __read_32bit_c0_register($10, 4)
1464 #define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1465
1466 #define read_c0_guestctl2()     __read_32bit_c0_register($10, 5)
1467 #define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1468
1469 #define read_c0_guestctl3()     __read_32bit_c0_register($10, 6)
1470 #define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1471
1472 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
1473 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
1474
1475 #define read_c0_guestctl0ext()  __read_32bit_c0_register($11, 4)
1476 #define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1477
1478 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
1479 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
1480
1481 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
1482 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
1483
1484 #define read_c0_status()        __read_32bit_c0_register($12, 0)
1485
1486 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
1487
1488 #define read_c0_guestctl0()     __read_32bit_c0_register($12, 6)
1489 #define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1490
1491 #define read_c0_gtoffset()      __read_32bit_c0_register($12, 7)
1492 #define write_c0_gtoffset(val)  __write_32bit_c0_register($12, 7, val)
1493
1494 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
1495 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
1496
1497 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
1498 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
1499
1500 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
1501
1502 #define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
1503
1504 #define read_c0_config()        __read_32bit_c0_register($16, 0)
1505 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
1506 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
1507 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
1508 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
1509 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
1510 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
1511 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
1512 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
1513 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
1514 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
1515 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
1516 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
1517 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
1518 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
1519 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
1520
1521 #define read_c0_lladdr()        __read_ulong_c0_register($17, 0)
1522 #define write_c0_lladdr(val)    __write_ulong_c0_register($17, 0, val)
1523 #define read_c0_maar()          __read_ulong_c0_register($17, 1)
1524 #define write_c0_maar(val)      __write_ulong_c0_register($17, 1, val)
1525 #define read_c0_maari()         __read_32bit_c0_register($17, 2)
1526 #define write_c0_maari(val)     __write_32bit_c0_register($17, 2, val)
1527
1528 /*
1529  * The WatchLo register.  There may be up to 8 of them.
1530  */
1531 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
1532 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
1533 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
1534 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
1535 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
1536 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
1537 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
1538 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
1539 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
1540 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
1541 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
1542 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
1543 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
1544 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
1545 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
1546 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
1547
1548 /*
1549  * The WatchHi register.  There may be up to 8 of them.
1550  */
1551 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
1552 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
1553 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
1554 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
1555 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
1556 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
1557 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
1558 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
1559
1560 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
1561 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
1562 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
1563 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
1564 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
1565 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
1566 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
1567 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
1568
1569 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
1570 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
1571
1572 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
1573 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1574
1575 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
1576 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1577
1578 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1579 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1580
1581 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1582 #define read_c0_r10k_diag()     __read_64bit_c0_register($22, 0)
1583 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1584
1585 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1586 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1587
1588 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1589 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1590
1591 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1592 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1593
1594 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1595 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1596
1597 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1598 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1599
1600 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1601 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1602
1603 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1604 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1605
1606 /*
1607  * MIPS32 / MIPS64 performance counters
1608  */
1609 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1610 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1611 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1612 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1613 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1614 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1615 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1616 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1617 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1618 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1619 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1620 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1621 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1622 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1623 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1624 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1625 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1626 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1627 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1628 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1629 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1630 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1631 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1632 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1633
1634 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1635 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1636
1637 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1638 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1639
1640 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1641
1642 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1643 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1644
1645 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1646 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1647
1648 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1649 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1650
1651 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1652 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1653
1654 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1655 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1656
1657 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1658 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1659
1660 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1661 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1662
1663 /* MIPSR2 */
1664 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1665 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1666
1667 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1668 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1669
1670 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1671 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1672
1673 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1674 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1675
1676 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1677 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1678
1679 #define read_c0_ebase_64()      __read_64bit_c0_register($15, 1)
1680 #define write_c0_ebase_64(val)  __write_64bit_c0_register($15, 1, val)
1681
1682 #define read_c0_cdmmbase()      __read_ulong_c0_register($15, 2)
1683 #define write_c0_cdmmbase(val)  __write_ulong_c0_register($15, 2, val)
1684
1685 /* MIPSR3 */
1686 #define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
1687 #define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
1688
1689 #define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
1690 #define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
1691
1692 #define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
1693 #define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
1694
1695 /* Hardware Page Table Walker */
1696 #define read_c0_pwbase()        __read_ulong_c0_register($5, 5)
1697 #define write_c0_pwbase(val)    __write_ulong_c0_register($5, 5, val)
1698
1699 #define read_c0_pwfield()       __read_ulong_c0_register($5, 6)
1700 #define write_c0_pwfield(val)   __write_ulong_c0_register($5, 6, val)
1701
1702 #define read_c0_pwsize()        __read_ulong_c0_register($5, 7)
1703 #define write_c0_pwsize(val)    __write_ulong_c0_register($5, 7, val)
1704
1705 #define read_c0_pwctl()         __read_32bit_c0_register($6, 6)
1706 #define write_c0_pwctl(val)     __write_32bit_c0_register($6, 6, val)
1707
1708 #define read_c0_pgd()           __read_64bit_c0_register($9, 7)
1709 #define write_c0_pgd(val)       __write_64bit_c0_register($9, 7, val)
1710
1711 #define read_c0_kpgd()          __read_64bit_c0_register($31, 7)
1712 #define write_c0_kpgd(val)      __write_64bit_c0_register($31, 7, val)
1713
1714 /* Cavium OCTEON (cnMIPS) */
1715 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1716 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1717
1718 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1719 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1720
1721 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1722 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1723 /*
1724  * The cacheerr registers are not standardized.  On OCTEON, they are
1725  * 64 bits wide.
1726  */
1727 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1728 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1729
1730 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1731 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1732
1733 /* BMIPS3300 */
1734 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1735 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1736
1737 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1738 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1739
1740 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1741 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
1742
1743 /* BMIPS43xx */
1744 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
1745 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
1746
1747 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
1748 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
1749
1750 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
1751 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
1752
1753 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
1754 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
1755
1756 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
1757 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
1758
1759 /* BMIPS5000 */
1760 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
1761 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
1762
1763 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
1764 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
1765
1766 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
1767 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
1768
1769 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
1770 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
1771
1772 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
1773 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
1774
1775 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
1776 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
1777
1778 /*
1779  * Macros to access the guest system control coprocessor
1780  */
1781
1782 #ifdef TOOLCHAIN_SUPPORTS_VIRT
1783
1784 #define __read_32bit_gc0_register(source, sel)                          \
1785 ({ int __res;                                                           \
1786         __asm__ __volatile__(                                           \
1787                 ".set\tpush\n\t"                                        \
1788                 ".set\tmips32r2\n\t"                                    \
1789                 ".set\tvirt\n\t"                                        \
1790                 "mfgc0\t%0, $%1, %2\n\t"                                \
1791                 ".set\tpop"                                             \
1792                 : "=r" (__res)                                          \
1793                 : "i" (source), "i" (sel));                             \
1794         __res;                                                          \
1795 })
1796
1797 #define __read_64bit_gc0_register(source, sel)                          \
1798 ({ unsigned long long __res;                                            \
1799         __asm__ __volatile__(                                           \
1800                 ".set\tpush\n\t"                                        \
1801                 ".set\tmips64r2\n\t"                                    \
1802                 ".set\tvirt\n\t"                                        \
1803                 "dmfgc0\t%0, $%1, %2\n\t"                       \
1804                 ".set\tpop"                                             \
1805                 : "=r" (__res)                                          \
1806                 : "i" (source), "i" (sel));                             \
1807         __res;                                                          \
1808 })
1809
1810 #define __write_32bit_gc0_register(register, sel, value)                \
1811 do {                                                                    \
1812         __asm__ __volatile__(                                           \
1813                 ".set\tpush\n\t"                                        \
1814                 ".set\tmips32r2\n\t"                                    \
1815                 ".set\tvirt\n\t"                                        \
1816                 "mtgc0\t%z0, $%1, %2\n\t"                               \
1817                 ".set\tpop"                                             \
1818                 : : "Jr" ((unsigned int)(value)),                       \
1819                     "i" (register), "i" (sel));                         \
1820 } while (0)
1821
1822 #define __write_64bit_gc0_register(register, sel, value)                \
1823 do {                                                                    \
1824         __asm__ __volatile__(                                           \
1825                 ".set\tpush\n\t"                                        \
1826                 ".set\tmips64r2\n\t"                                    \
1827                 ".set\tvirt\n\t"                                        \
1828                 "dmtgc0\t%z0, $%1, %2\n\t"                              \
1829                 ".set\tpop"                                             \
1830                 : : "Jr" (value),                                       \
1831                     "i" (register), "i" (sel));                         \
1832 } while (0)
1833
1834 #else   /* TOOLCHAIN_SUPPORTS_VIRT */
1835
1836 #define __read_32bit_gc0_register(source, sel)                          \
1837 ({ int __res;                                                           \
1838         __asm__ __volatile__(                                           \
1839                 ".set\tpush\n\t"                                        \
1840                 ".set\tnoat\n\t"                                        \
1841                 "# mfgc0\t$1, $%1, %2\n\t"                              \
1842                 _ASM_INSN_IF_MIPS(0x40610000 | %1 << 11 | %2)           \
1843                 _ASM_INSN32_IF_MM(0x002004fc | %1 << 16 | %2 << 11)     \
1844                 "move\t%0, $1\n\t"                                      \
1845                 ".set\tpop"                                             \
1846                 : "=r" (__res)                                          \
1847                 : "i" (source), "i" (sel));                             \
1848         __res;                                                          \
1849 })
1850
1851 #define __read_64bit_gc0_register(source, sel)                          \
1852 ({ unsigned long long __res;                                            \
1853         __asm__ __volatile__(                                           \
1854                 ".set\tpush\n\t"                                        \
1855                 ".set\tnoat\n\t"                                        \
1856                 "# dmfgc0\t$1, $%1, %2\n\t"                             \
1857                 _ASM_INSN_IF_MIPS(0x40610100 | %1 << 11 | %2)           \
1858                 _ASM_INSN32_IF_MM(0x582004fc | %1 << 16 | %2 << 11)     \
1859                 "move\t%0, $1\n\t"                                      \
1860                 ".set\tpop"                                             \
1861                 : "=r" (__res)                                          \
1862                 : "i" (source), "i" (sel));                             \
1863         __res;                                                          \
1864 })
1865
1866 #define __write_32bit_gc0_register(register, sel, value)                \
1867 do {                                                                    \
1868         __asm__ __volatile__(                                           \
1869                 ".set\tpush\n\t"                                        \
1870                 ".set\tnoat\n\t"                                        \
1871                 "move\t$1, %z0\n\t"                                     \
1872                 "# mtgc0\t$1, $%1, %2\n\t"                              \
1873                 _ASM_INSN_IF_MIPS(0x40610200 | %1 << 11 | %2)           \
1874                 _ASM_INSN32_IF_MM(0x002006fc | %1 << 16 | %2 << 11)     \
1875                 ".set\tpop"                                             \
1876                 : : "Jr" ((unsigned int)(value)),                       \
1877                     "i" (register), "i" (sel));                         \
1878 } while (0)
1879
1880 #define __write_64bit_gc0_register(register, sel, value)                \
1881 do {                                                                    \
1882         __asm__ __volatile__(                                           \
1883                 ".set\tpush\n\t"                                        \
1884                 ".set\tnoat\n\t"                                        \
1885                 "move\t$1, %z0\n\t"                                     \
1886                 "# dmtgc0\t$1, $%1, %2\n\t"                             \
1887                 _ASM_INSN_IF_MIPS(0x40610300 | %1 << 11 | %2)           \
1888                 _ASM_INSN32_IF_MM(0x582006fc | %1 << 16 | %2 << 11)     \
1889                 ".set\tpop"                                             \
1890                 : : "Jr" (value),                                       \
1891                     "i" (register), "i" (sel));                         \
1892 } while (0)
1893
1894 #endif  /* !TOOLCHAIN_SUPPORTS_VIRT */
1895
1896 #define __read_ulong_gc0_register(reg, sel)                             \
1897         ((sizeof(unsigned long) == 4) ?                                 \
1898         (unsigned long) __read_32bit_gc0_register(reg, sel) :           \
1899         (unsigned long) __read_64bit_gc0_register(reg, sel))
1900
1901 #define __write_ulong_gc0_register(reg, sel, val)                       \
1902 do {                                                                    \
1903         if (sizeof(unsigned long) == 4)                                 \
1904                 __write_32bit_gc0_register(reg, sel, val);              \
1905         else                                                            \
1906                 __write_64bit_gc0_register(reg, sel, val);              \
1907 } while (0)
1908
1909 #define read_gc0_index()                __read_32bit_gc0_register(0, 0)
1910 #define write_gc0_index(val)            __write_32bit_gc0_register(0, 0, val)
1911
1912 #define read_gc0_entrylo0()             __read_ulong_gc0_register(2, 0)
1913 #define write_gc0_entrylo0(val)         __write_ulong_gc0_register(2, 0, val)
1914
1915 #define read_gc0_entrylo1()             __read_ulong_gc0_register(3, 0)
1916 #define write_gc0_entrylo1(val)         __write_ulong_gc0_register(3, 0, val)
1917
1918 #define read_gc0_context()              __read_ulong_gc0_register(4, 0)
1919 #define write_gc0_context(val)          __write_ulong_gc0_register(4, 0, val)
1920
1921 #define read_gc0_contextconfig()        __read_32bit_gc0_register(4, 1)
1922 #define write_gc0_contextconfig(val)    __write_32bit_gc0_register(4, 1, val)
1923
1924 #define read_gc0_userlocal()            __read_ulong_gc0_register(4, 2)
1925 #define write_gc0_userlocal(val)        __write_ulong_gc0_register(4, 2, val)
1926
1927 #define read_gc0_xcontextconfig()       __read_ulong_gc0_register(4, 3)
1928 #define write_gc0_xcontextconfig(val)   __write_ulong_gc0_register(4, 3, val)
1929
1930 #define read_gc0_pagemask()             __read_32bit_gc0_register(5, 0)
1931 #define write_gc0_pagemask(val)         __write_32bit_gc0_register(5, 0, val)
1932
1933 #define read_gc0_pagegrain()            __read_32bit_gc0_register(5, 1)
1934 #define write_gc0_pagegrain(val)        __write_32bit_gc0_register(5, 1, val)
1935
1936 #define read_gc0_segctl0()              __read_ulong_gc0_register(5, 2)
1937 #define write_gc0_segctl0(val)          __write_ulong_gc0_register(5, 2, val)
1938
1939 #define read_gc0_segctl1()              __read_ulong_gc0_register(5, 3)
1940 #define write_gc0_segctl1(val)          __write_ulong_gc0_register(5, 3, val)
1941
1942 #define read_gc0_segctl2()              __read_ulong_gc0_register(5, 4)
1943 #define write_gc0_segctl2(val)          __write_ulong_gc0_register(5, 4, val)
1944
1945 #define read_gc0_pwbase()               __read_ulong_gc0_register(5, 5)
1946 #define write_gc0_pwbase(val)           __write_ulong_gc0_register(5, 5, val)
1947
1948 #define read_gc0_pwfield()              __read_ulong_gc0_register(5, 6)
1949 #define write_gc0_pwfield(val)          __write_ulong_gc0_register(5, 6, val)
1950
1951 #define read_gc0_pwsize()               __read_ulong_gc0_register(5, 7)
1952 #define write_gc0_pwsize(val)           __write_ulong_gc0_register(5, 7, val)
1953
1954 #define read_gc0_wired()                __read_32bit_gc0_register(6, 0)
1955 #define write_gc0_wired(val)            __write_32bit_gc0_register(6, 0, val)
1956
1957 #define read_gc0_pwctl()                __read_32bit_gc0_register(6, 6)
1958 #define write_gc0_pwctl(val)            __write_32bit_gc0_register(6, 6, val)
1959
1960 #define read_gc0_hwrena()               __read_32bit_gc0_register(7, 0)
1961 #define write_gc0_hwrena(val)           __write_32bit_gc0_register(7, 0, val)
1962
1963 #define read_gc0_badvaddr()             __read_ulong_gc0_register(8, 0)
1964 #define write_gc0_badvaddr(val)         __write_ulong_gc0_register(8, 0, val)
1965
1966 #define read_gc0_badinstr()             __read_32bit_gc0_register(8, 1)
1967 #define write_gc0_badinstr(val)         __write_32bit_gc0_register(8, 1, val)
1968
1969 #define read_gc0_badinstrp()            __read_32bit_gc0_register(8, 2)
1970 #define write_gc0_badinstrp(val)        __write_32bit_gc0_register(8, 2, val)
1971
1972 #define read_gc0_count()                __read_32bit_gc0_register(9, 0)
1973
1974 #define read_gc0_entryhi()              __read_ulong_gc0_register(10, 0)
1975 #define write_gc0_entryhi(val)          __write_ulong_gc0_register(10, 0, val)
1976
1977 #define read_gc0_compare()              __read_32bit_gc0_register(11, 0)
1978 #define write_gc0_compare(val)          __write_32bit_gc0_register(11, 0, val)
1979
1980 #define read_gc0_status()               __read_32bit_gc0_register(12, 0)
1981 #define write_gc0_status(val)           __write_32bit_gc0_register(12, 0, val)
1982
1983 #define read_gc0_intctl()               __read_32bit_gc0_register(12, 1)
1984 #define write_gc0_intctl(val)           __write_32bit_gc0_register(12, 1, val)
1985
1986 #define read_gc0_cause()                __read_32bit_gc0_register(13, 0)
1987 #define write_gc0_cause(val)            __write_32bit_gc0_register(13, 0, val)
1988
1989 #define read_gc0_epc()                  __read_ulong_gc0_register(14, 0)
1990 #define write_gc0_epc(val)              __write_ulong_gc0_register(14, 0, val)
1991
1992 #define read_gc0_ebase()                __read_32bit_gc0_register(15, 1)
1993 #define write_gc0_ebase(val)            __write_32bit_gc0_register(15, 1, val)
1994
1995 #define read_gc0_ebase_64()             __read_64bit_gc0_register(15, 1)
1996 #define write_gc0_ebase_64(val)         __write_64bit_gc0_register(15, 1, val)
1997
1998 #define read_gc0_config()               __read_32bit_gc0_register(16, 0)
1999 #define read_gc0_config1()              __read_32bit_gc0_register(16, 1)
2000 #define read_gc0_config2()              __read_32bit_gc0_register(16, 2)
2001 #define read_gc0_config3()              __read_32bit_gc0_register(16, 3)
2002 #define read_gc0_config4()              __read_32bit_gc0_register(16, 4)
2003 #define read_gc0_config5()              __read_32bit_gc0_register(16, 5)
2004 #define read_gc0_config6()              __read_32bit_gc0_register(16, 6)
2005 #define read_gc0_config7()              __read_32bit_gc0_register(16, 7)
2006 #define write_gc0_config(val)           __write_32bit_gc0_register(16, 0, val)
2007 #define write_gc0_config1(val)          __write_32bit_gc0_register(16, 1, val)
2008 #define write_gc0_config2(val)          __write_32bit_gc0_register(16, 2, val)
2009 #define write_gc0_config3(val)          __write_32bit_gc0_register(16, 3, val)
2010 #define write_gc0_config4(val)          __write_32bit_gc0_register(16, 4, val)
2011 #define write_gc0_config5(val)          __write_32bit_gc0_register(16, 5, val)
2012 #define write_gc0_config6(val)          __write_32bit_gc0_register(16, 6, val)
2013 #define write_gc0_config7(val)          __write_32bit_gc0_register(16, 7, val)
2014
2015 #define read_gc0_watchlo0()             __read_ulong_gc0_register(18, 0)
2016 #define read_gc0_watchlo1()             __read_ulong_gc0_register(18, 1)
2017 #define read_gc0_watchlo2()             __read_ulong_gc0_register(18, 2)
2018 #define read_gc0_watchlo3()             __read_ulong_gc0_register(18, 3)
2019 #define read_gc0_watchlo4()             __read_ulong_gc0_register(18, 4)
2020 #define read_gc0_watchlo5()             __read_ulong_gc0_register(18, 5)
2021 #define read_gc0_watchlo6()             __read_ulong_gc0_register(18, 6)
2022 #define read_gc0_watchlo7()             __read_ulong_gc0_register(18, 7)
2023 #define write_gc0_watchlo0(val)         __write_ulong_gc0_register(18, 0, val)
2024 #define write_gc0_watchlo1(val)         __write_ulong_gc0_register(18, 1, val)
2025 #define write_gc0_watchlo2(val)         __write_ulong_gc0_register(18, 2, val)
2026 #define write_gc0_watchlo3(val)         __write_ulong_gc0_register(18, 3, val)
2027 #define write_gc0_watchlo4(val)         __write_ulong_gc0_register(18, 4, val)
2028 #define write_gc0_watchlo5(val)         __write_ulong_gc0_register(18, 5, val)
2029 #define write_gc0_watchlo6(val)         __write_ulong_gc0_register(18, 6, val)
2030 #define write_gc0_watchlo7(val)         __write_ulong_gc0_register(18, 7, val)
2031
2032 #define read_gc0_watchhi0()             __read_32bit_gc0_register(19, 0)
2033 #define read_gc0_watchhi1()             __read_32bit_gc0_register(19, 1)
2034 #define read_gc0_watchhi2()             __read_32bit_gc0_register(19, 2)
2035 #define read_gc0_watchhi3()             __read_32bit_gc0_register(19, 3)
2036 #define read_gc0_watchhi4()             __read_32bit_gc0_register(19, 4)
2037 #define read_gc0_watchhi5()             __read_32bit_gc0_register(19, 5)
2038 #define read_gc0_watchhi6()             __read_32bit_gc0_register(19, 6)
2039 #define read_gc0_watchhi7()             __read_32bit_gc0_register(19, 7)
2040 #define write_gc0_watchhi0(val)         __write_32bit_gc0_register(19, 0, val)
2041 #define write_gc0_watchhi1(val)         __write_32bit_gc0_register(19, 1, val)
2042 #define write_gc0_watchhi2(val)         __write_32bit_gc0_register(19, 2, val)
2043 #define write_gc0_watchhi3(val)         __write_32bit_gc0_register(19, 3, val)
2044 #define write_gc0_watchhi4(val)         __write_32bit_gc0_register(19, 4, val)
2045 #define write_gc0_watchhi5(val)         __write_32bit_gc0_register(19, 5, val)
2046 #define write_gc0_watchhi6(val)         __write_32bit_gc0_register(19, 6, val)
2047 #define write_gc0_watchhi7(val)         __write_32bit_gc0_register(19, 7, val)
2048
2049 #define read_gc0_xcontext()             __read_ulong_gc0_register(20, 0)
2050 #define write_gc0_xcontext(val)         __write_ulong_gc0_register(20, 0, val)
2051
2052 #define read_gc0_perfctrl0()            __read_32bit_gc0_register(25, 0)
2053 #define write_gc0_perfctrl0(val)        __write_32bit_gc0_register(25, 0, val)
2054 #define read_gc0_perfcntr0()            __read_32bit_gc0_register(25, 1)
2055 #define write_gc0_perfcntr0(val)        __write_32bit_gc0_register(25, 1, val)
2056 #define read_gc0_perfcntr0_64()         __read_64bit_gc0_register(25, 1)
2057 #define write_gc0_perfcntr0_64(val)     __write_64bit_gc0_register(25, 1, val)
2058 #define read_gc0_perfctrl1()            __read_32bit_gc0_register(25, 2)
2059 #define write_gc0_perfctrl1(val)        __write_32bit_gc0_register(25, 2, val)
2060 #define read_gc0_perfcntr1()            __read_32bit_gc0_register(25, 3)
2061 #define write_gc0_perfcntr1(val)        __write_32bit_gc0_register(25, 3, val)
2062 #define read_gc0_perfcntr1_64()         __read_64bit_gc0_register(25, 3)
2063 #define write_gc0_perfcntr1_64(val)     __write_64bit_gc0_register(25, 3, val)
2064 #define read_gc0_perfctrl2()            __read_32bit_gc0_register(25, 4)
2065 #define write_gc0_perfctrl2(val)        __write_32bit_gc0_register(25, 4, val)
2066 #define read_gc0_perfcntr2()            __read_32bit_gc0_register(25, 5)
2067 #define write_gc0_perfcntr2(val)        __write_32bit_gc0_register(25, 5, val)
2068 #define read_gc0_perfcntr2_64()         __read_64bit_gc0_register(25, 5)
2069 #define write_gc0_perfcntr2_64(val)     __write_64bit_gc0_register(25, 5, val)
2070 #define read_gc0_perfctrl3()            __read_32bit_gc0_register(25, 6)
2071 #define write_gc0_perfctrl3(val)        __write_32bit_gc0_register(25, 6, val)
2072 #define read_gc0_perfcntr3()            __read_32bit_gc0_register(25, 7)
2073 #define write_gc0_perfcntr3(val)        __write_32bit_gc0_register(25, 7, val)
2074 #define read_gc0_perfcntr3_64()         __read_64bit_gc0_register(25, 7)
2075 #define write_gc0_perfcntr3_64(val)     __write_64bit_gc0_register(25, 7, val)
2076
2077 #define read_gc0_errorepc()             __read_ulong_gc0_register(30, 0)
2078 #define write_gc0_errorepc(val)         __write_ulong_gc0_register(30, 0, val)
2079
2080 #define read_gc0_kscratch1()            __read_ulong_gc0_register(31, 2)
2081 #define read_gc0_kscratch2()            __read_ulong_gc0_register(31, 3)
2082 #define read_gc0_kscratch3()            __read_ulong_gc0_register(31, 4)
2083 #define read_gc0_kscratch4()            __read_ulong_gc0_register(31, 5)
2084 #define read_gc0_kscratch5()            __read_ulong_gc0_register(31, 6)
2085 #define read_gc0_kscratch6()            __read_ulong_gc0_register(31, 7)
2086 #define write_gc0_kscratch1(val)        __write_ulong_gc0_register(31, 2, val)
2087 #define write_gc0_kscratch2(val)        __write_ulong_gc0_register(31, 3, val)
2088 #define write_gc0_kscratch3(val)        __write_ulong_gc0_register(31, 4, val)
2089 #define write_gc0_kscratch4(val)        __write_ulong_gc0_register(31, 5, val)
2090 #define write_gc0_kscratch5(val)        __write_ulong_gc0_register(31, 6, val)
2091 #define write_gc0_kscratch6(val)        __write_ulong_gc0_register(31, 7, val)
2092
2093 /*
2094  * Macros to access the floating point coprocessor control registers
2095  */
2096 #define _read_32bit_cp1_register(source, gas_hardfloat)                 \
2097 ({                                                                      \
2098         unsigned int __res;                                             \
2099                                                                         \
2100         __asm__ __volatile__(                                           \
2101         "       .set    push                                    \n"     \
2102         "       .set    reorder                                 \n"     \
2103         "       # gas fails to assemble cfc1 for some archs,    \n"     \
2104         "       # like Octeon.                                  \n"     \
2105         "       .set    mips1                                   \n"     \
2106         "       "STR(gas_hardfloat)"                            \n"     \
2107         "       cfc1    %0,"STR(source)"                        \n"     \
2108         "       .set    pop                                     \n"     \
2109         : "=r" (__res));                                                \
2110         __res;                                                          \
2111 })
2112
2113 #define _write_32bit_cp1_register(dest, val, gas_hardfloat)             \
2114 do {                                                                    \
2115         __asm__ __volatile__(                                           \
2116         "       .set    push                                    \n"     \
2117         "       .set    reorder                                 \n"     \
2118         "       "STR(gas_hardfloat)"                            \n"     \
2119         "       ctc1    %0,"STR(dest)"                          \n"     \
2120         "       .set    pop                                     \n"     \
2121         : : "r" (val));                                                 \
2122 } while (0)
2123
2124 #ifdef GAS_HAS_SET_HARDFLOAT
2125 #define read_32bit_cp1_register(source)                                 \
2126         _read_32bit_cp1_register(source, .set hardfloat)
2127 #define write_32bit_cp1_register(dest, val)                             \
2128         _write_32bit_cp1_register(dest, val, .set hardfloat)
2129 #else
2130 #define read_32bit_cp1_register(source)                                 \
2131         _read_32bit_cp1_register(source, )
2132 #define write_32bit_cp1_register(dest, val)                             \
2133         _write_32bit_cp1_register(dest, val, )
2134 #endif
2135
2136 #ifdef HAVE_AS_DSP
2137 #define rddsp(mask)                                                     \
2138 ({                                                                      \
2139         unsigned int __dspctl;                                          \
2140                                                                         \
2141         __asm__ __volatile__(                                           \
2142         "       .set push                                       \n"     \
2143         "       .set dsp                                        \n"     \
2144         "       rddsp   %0, %x1                                 \n"     \
2145         "       .set pop                                        \n"     \
2146         : "=r" (__dspctl)                                               \
2147         : "i" (mask));                                                  \
2148         __dspctl;                                                       \
2149 })
2150
2151 #define wrdsp(val, mask)                                                \
2152 do {                                                                    \
2153         __asm__ __volatile__(                                           \
2154         "       .set push                                       \n"     \
2155         "       .set dsp                                        \n"     \
2156         "       wrdsp   %0, %x1                                 \n"     \
2157         "       .set pop                                        \n"     \
2158         :                                                               \
2159         : "r" (val), "i" (mask));                                       \
2160 } while (0)
2161
2162 #define mflo0()                                                         \
2163 ({                                                                      \
2164         long mflo0;                                                     \
2165         __asm__(                                                        \
2166         "       .set push                                       \n"     \
2167         "       .set dsp                                        \n"     \
2168         "       mflo %0, $ac0                                   \n"     \
2169         "       .set pop                                        \n"     \
2170         : "=r" (mflo0));                                                \
2171         mflo0;                                                          \
2172 })
2173
2174 #define mflo1()                                                         \
2175 ({                                                                      \
2176         long mflo1;                                                     \
2177         __asm__(                                                        \
2178         "       .set push                                       \n"     \
2179         "       .set dsp                                        \n"     \
2180         "       mflo %0, $ac1                                   \n"     \
2181         "       .set pop                                        \n"     \
2182         : "=r" (mflo1));                                                \
2183         mflo1;                                                          \
2184 })
2185
2186 #define mflo2()                                                         \
2187 ({                                                                      \
2188         long mflo2;                                                     \
2189         __asm__(                                                        \
2190         "       .set push                                       \n"     \
2191         "       .set dsp                                        \n"     \
2192         "       mflo %0, $ac2                                   \n"     \
2193         "       .set pop                                        \n"     \
2194         : "=r" (mflo2));                                                \
2195         mflo2;                                                          \
2196 })
2197
2198 #define mflo3()                                                         \
2199 ({                                                                      \
2200         long mflo3;                                                     \
2201         __asm__(                                                        \
2202         "       .set push                                       \n"     \
2203         "       .set dsp                                        \n"     \
2204         "       mflo %0, $ac3                                   \n"     \
2205         "       .set pop                                        \n"     \
2206         : "=r" (mflo3));                                                \
2207         mflo3;                                                          \
2208 })
2209
2210 #define mfhi0()                                                         \
2211 ({                                                                      \
2212         long mfhi0;                                                     \
2213         __asm__(                                                        \
2214         "       .set push                                       \n"     \
2215         "       .set dsp                                        \n"     \
2216         "       mfhi %0, $ac0                                   \n"     \
2217         "       .set pop                                        \n"     \
2218         : "=r" (mfhi0));                                                \
2219         mfhi0;                                                          \
2220 })
2221
2222 #define mfhi1()                                                         \
2223 ({                                                                      \
2224         long mfhi1;                                                     \
2225         __asm__(                                                        \
2226         "       .set push                                       \n"     \
2227         "       .set dsp                                        \n"     \
2228         "       mfhi %0, $ac1                                   \n"     \
2229         "       .set pop                                        \n"     \
2230         : "=r" (mfhi1));                                                \
2231         mfhi1;                                                          \
2232 })
2233
2234 #define mfhi2()                                                         \
2235 ({                                                                      \
2236         long mfhi2;                                                     \
2237         __asm__(                                                        \
2238         "       .set push                                       \n"     \
2239         "       .set dsp                                        \n"     \
2240         "       mfhi %0, $ac2                                   \n"     \
2241         "       .set pop                                        \n"     \
2242         : "=r" (mfhi2));                                                \
2243         mfhi2;                                                          \
2244 })
2245
2246 #define mfhi3()                                                         \
2247 ({                                                                      \
2248         long mfhi3;                                                     \
2249         __asm__(                                                        \
2250         "       .set push                                       \n"     \
2251         "       .set dsp                                        \n"     \
2252         "       mfhi %0, $ac3                                   \n"     \
2253         "       .set pop                                        \n"     \
2254         : "=r" (mfhi3));                                                \
2255         mfhi3;                                                          \
2256 })
2257
2258
2259 #define mtlo0(x)                                                        \
2260 ({                                                                      \
2261         __asm__(                                                        \
2262         "       .set push                                       \n"     \
2263         "       .set dsp                                        \n"     \
2264         "       mtlo %0, $ac0                                   \n"     \
2265         "       .set pop                                        \n"     \
2266         :                                                               \
2267         : "r" (x));                                                     \
2268 })
2269
2270 #define mtlo1(x)                                                        \
2271 ({                                                                      \
2272         __asm__(                                                        \
2273         "       .set push                                       \n"     \
2274         "       .set dsp                                        \n"     \
2275         "       mtlo %0, $ac1                                   \n"     \
2276         "       .set pop                                        \n"     \
2277         :                                                               \
2278         : "r" (x));                                                     \
2279 })
2280
2281 #define mtlo2(x)                                                        \
2282 ({                                                                      \
2283         __asm__(                                                        \
2284         "       .set push                                       \n"     \
2285         "       .set dsp                                        \n"     \
2286         "       mtlo %0, $ac2                                   \n"     \
2287         "       .set pop                                        \n"     \
2288         :                                                               \
2289         : "r" (x));                                                     \
2290 })
2291
2292 #define mtlo3(x)                                                        \
2293 ({                                                                      \
2294         __asm__(                                                        \
2295         "       .set push                                       \n"     \
2296         "       .set dsp                                        \n"     \
2297         "       mtlo %0, $ac3                                   \n"     \
2298         "       .set pop                                        \n"     \
2299         :                                                               \
2300         : "r" (x));                                                     \
2301 })
2302
2303 #define mthi0(x)                                                        \
2304 ({                                                                      \
2305         __asm__(                                                        \
2306         "       .set push                                       \n"     \
2307         "       .set dsp                                        \n"     \
2308         "       mthi %0, $ac0                                   \n"     \
2309         "       .set pop                                        \n"     \
2310         :                                                               \
2311         : "r" (x));                                                     \
2312 })
2313
2314 #define mthi1(x)                                                        \
2315 ({                                                                      \
2316         __asm__(                                                        \
2317         "       .set push                                       \n"     \
2318         "       .set dsp                                        \n"     \
2319         "       mthi %0, $ac1                                   \n"     \
2320         "       .set pop                                        \n"     \
2321         :                                                               \
2322         : "r" (x));                                                     \
2323 })
2324
2325 #define mthi2(x)                                                        \
2326 ({                                                                      \
2327         __asm__(                                                        \
2328         "       .set push                                       \n"     \
2329         "       .set dsp                                        \n"     \
2330         "       mthi %0, $ac2                                   \n"     \
2331         "       .set pop                                        \n"     \
2332         :                                                               \
2333         : "r" (x));                                                     \
2334 })
2335
2336 #define mthi3(x)                                                        \
2337 ({                                                                      \
2338         __asm__(                                                        \
2339         "       .set push                                       \n"     \
2340         "       .set dsp                                        \n"     \
2341         "       mthi %0, $ac3                                   \n"     \
2342         "       .set pop                                        \n"     \
2343         :                                                               \
2344         : "r" (x));                                                     \
2345 })
2346
2347 #else
2348
2349 #define rddsp(mask)                                                     \
2350 ({                                                                      \
2351         unsigned int __res;                                             \
2352                                                                         \
2353         __asm__ __volatile__(                                           \
2354         "       .set    push                                    \n"     \
2355         "       .set    noat                                    \n"     \
2356         "       # rddsp $1, %x1                                 \n"     \
2357         _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16))                     \
2358         _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14))                     \
2359         "       move    %0, $1                                  \n"     \
2360         "       .set    pop                                     \n"     \
2361         : "=r" (__res)                                                  \
2362         : "i" (mask));                                                  \
2363         __res;                                                          \
2364 })
2365
2366 #define wrdsp(val, mask)                                                \
2367 do {                                                                    \
2368         __asm__ __volatile__(                                           \
2369         "       .set    push                                    \n"     \
2370         "       .set    noat                                    \n"     \
2371         "       move    $1, %0                                  \n"     \
2372         "       # wrdsp $1, %x1                                 \n"     \
2373         _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11))                     \
2374         _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14))                     \
2375         "       .set    pop                                     \n"     \
2376         :                                                               \
2377         : "r" (val), "i" (mask));                                       \
2378 } while (0)
2379
2380 #define _dsp_mfxxx(ins)                                                 \
2381 ({                                                                      \
2382         unsigned long __treg;                                           \
2383                                                                         \
2384         __asm__ __volatile__(                                           \
2385         "       .set    push                                    \n"     \
2386         "       .set    noat                                    \n"     \
2387         _ASM_INSN_IF_MIPS(0x00000810 | %X1)                             \
2388         _ASM_INSN32_IF_MM(0x0001007c | %x1)                             \
2389         "       move    %0, $1                                  \n"     \
2390         "       .set    pop                                     \n"     \
2391         : "=r" (__treg)                                                 \
2392         : "i" (ins));                                                   \
2393         __treg;                                                         \
2394 })
2395
2396 #define _dsp_mtxxx(val, ins)                                            \
2397 do {                                                                    \
2398         __asm__ __volatile__(                                           \
2399         "       .set    push                                    \n"     \
2400         "       .set    noat                                    \n"     \
2401         "       move    $1, %0                                  \n"     \
2402         _ASM_INSN_IF_MIPS(0x00200011 | %X1)                             \
2403         _ASM_INSN32_IF_MM(0x0001207c | %x1)                             \
2404         "       .set    pop                                     \n"     \
2405         :                                                               \
2406         : "r" (val), "i" (ins));                                        \
2407 } while (0)
2408
2409 #ifdef CONFIG_CPU_MICROMIPS
2410
2411 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2412 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2413
2414 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2415 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2416
2417 #else  /* !CONFIG_CPU_MICROMIPS */
2418
2419 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2420 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2421
2422 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2423 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2424
2425 #endif /* CONFIG_CPU_MICROMIPS */
2426
2427 #define mflo0() _dsp_mflo(0)
2428 #define mflo1() _dsp_mflo(1)
2429 #define mflo2() _dsp_mflo(2)
2430 #define mflo3() _dsp_mflo(3)
2431
2432 #define mfhi0() _dsp_mfhi(0)
2433 #define mfhi1() _dsp_mfhi(1)
2434 #define mfhi2() _dsp_mfhi(2)
2435 #define mfhi3() _dsp_mfhi(3)
2436
2437 #define mtlo0(x) _dsp_mtlo(x, 0)
2438 #define mtlo1(x) _dsp_mtlo(x, 1)
2439 #define mtlo2(x) _dsp_mtlo(x, 2)
2440 #define mtlo3(x) _dsp_mtlo(x, 3)
2441
2442 #define mthi0(x) _dsp_mthi(x, 0)
2443 #define mthi1(x) _dsp_mthi(x, 1)
2444 #define mthi2(x) _dsp_mthi(x, 2)
2445 #define mthi3(x) _dsp_mthi(x, 3)
2446
2447 #endif
2448
2449 /*
2450  * TLB operations.
2451  *
2452  * It is responsibility of the caller to take care of any TLB hazards.
2453  */
2454 static inline void tlb_probe(void)
2455 {
2456         __asm__ __volatile__(
2457                 ".set noreorder\n\t"
2458                 "tlbp\n\t"
2459                 ".set reorder");
2460 }
2461
2462 static inline void tlb_read(void)
2463 {
2464 #if MIPS34K_MISSED_ITLB_WAR
2465         int res = 0;
2466
2467         __asm__ __volatile__(
2468         "       .set    push                                    \n"
2469         "       .set    noreorder                               \n"
2470         "       .set    noat                                    \n"
2471         "       .set    mips32r2                                \n"
2472         "       .word   0x41610001              # dvpe $1       \n"
2473         "       move    %0, $1                                  \n"
2474         "       ehb                                             \n"
2475         "       .set    pop                                     \n"
2476         : "=r" (res));
2477
2478         instruction_hazard();
2479 #endif
2480
2481         __asm__ __volatile__(
2482                 ".set noreorder\n\t"
2483                 "tlbr\n\t"
2484                 ".set reorder");
2485
2486 #if MIPS34K_MISSED_ITLB_WAR
2487         if ((res & _ULCAST_(1)))
2488                 __asm__ __volatile__(
2489                 "       .set    push                            \n"
2490                 "       .set    noreorder                       \n"
2491                 "       .set    noat                            \n"
2492                 "       .set    mips32r2                        \n"
2493                 "       .word   0x41600021      # evpe          \n"
2494                 "       ehb                                     \n"
2495                 "       .set    pop                             \n");
2496 #endif
2497 }
2498
2499 static inline void tlb_write_indexed(void)
2500 {
2501         __asm__ __volatile__(
2502                 ".set noreorder\n\t"
2503                 "tlbwi\n\t"
2504                 ".set reorder");
2505 }
2506
2507 static inline void tlb_write_random(void)
2508 {
2509         __asm__ __volatile__(
2510                 ".set noreorder\n\t"
2511                 "tlbwr\n\t"
2512                 ".set reorder");
2513 }
2514
2515 #ifdef TOOLCHAIN_SUPPORTS_VIRT
2516
2517 /*
2518  * Guest TLB operations.
2519  *
2520  * It is responsibility of the caller to take care of any TLB hazards.
2521  */
2522 static inline void guest_tlb_probe(void)
2523 {
2524         __asm__ __volatile__(
2525                 ".set push\n\t"
2526                 ".set noreorder\n\t"
2527                 ".set virt\n\t"
2528                 "tlbgp\n\t"
2529                 ".set pop");
2530 }
2531
2532 static inline void guest_tlb_read(void)
2533 {
2534         __asm__ __volatile__(
2535                 ".set push\n\t"
2536                 ".set noreorder\n\t"
2537                 ".set virt\n\t"
2538                 "tlbgr\n\t"
2539                 ".set pop");
2540 }
2541
2542 static inline void guest_tlb_write_indexed(void)
2543 {
2544         __asm__ __volatile__(
2545                 ".set push\n\t"
2546                 ".set noreorder\n\t"
2547                 ".set virt\n\t"
2548                 "tlbgwi\n\t"
2549                 ".set pop");
2550 }
2551
2552 static inline void guest_tlb_write_random(void)
2553 {
2554         __asm__ __volatile__(
2555                 ".set push\n\t"
2556                 ".set noreorder\n\t"
2557                 ".set virt\n\t"
2558                 "tlbgwr\n\t"
2559                 ".set pop");
2560 }
2561
2562 /*
2563  * Guest TLB Invalidate Flush
2564  */
2565 static inline void guest_tlbinvf(void)
2566 {
2567         __asm__ __volatile__(
2568                 ".set push\n\t"
2569                 ".set noreorder\n\t"
2570                 ".set virt\n\t"
2571                 "tlbginvf\n\t"
2572                 ".set pop");
2573 }
2574
2575 #else   /* TOOLCHAIN_SUPPORTS_VIRT */
2576
2577 /*
2578  * Guest TLB operations.
2579  *
2580  * It is responsibility of the caller to take care of any TLB hazards.
2581  */
2582 static inline void guest_tlb_probe(void)
2583 {
2584         __asm__ __volatile__(
2585                 "# tlbgp\n\t"
2586                 _ASM_INSN_IF_MIPS(0x42000010)
2587                 _ASM_INSN32_IF_MM(0x0000017c));
2588 }
2589
2590 static inline void guest_tlb_read(void)
2591 {
2592         __asm__ __volatile__(
2593                 "# tlbgr\n\t"
2594                 _ASM_INSN_IF_MIPS(0x42000009)
2595                 _ASM_INSN32_IF_MM(0x0000117c));
2596 }
2597
2598 static inline void guest_tlb_write_indexed(void)
2599 {
2600         __asm__ __volatile__(
2601                 "# tlbgwi\n\t"
2602                 _ASM_INSN_IF_MIPS(0x4200000a)
2603                 _ASM_INSN32_IF_MM(0x0000217c));
2604 }
2605
2606 static inline void guest_tlb_write_random(void)
2607 {
2608         __asm__ __volatile__(
2609                 "# tlbgwr\n\t"
2610                 _ASM_INSN_IF_MIPS(0x4200000e)
2611                 _ASM_INSN32_IF_MM(0x0000317c));
2612 }
2613
2614 /*
2615  * Guest TLB Invalidate Flush
2616  */
2617 static inline void guest_tlbinvf(void)
2618 {
2619         __asm__ __volatile__(
2620                 "# tlbginvf\n\t"
2621                 _ASM_INSN_IF_MIPS(0x4200000c)
2622                 _ASM_INSN32_IF_MM(0x0000517c));
2623 }
2624
2625 #endif  /* !TOOLCHAIN_SUPPORTS_VIRT */
2626
2627 /*
2628  * Manipulate bits in a register.
2629  */
2630 #define __BUILD_SET_COMMON(name)                                \
2631 static inline unsigned int                                      \
2632 set_##name(unsigned int set)                                    \
2633 {                                                               \
2634         unsigned int res, new;                                  \
2635                                                                 \
2636         res = read_##name();                                    \
2637         new = res | set;                                        \
2638         write_##name(new);                                      \
2639                                                                 \
2640         return res;                                             \
2641 }                                                               \
2642                                                                 \
2643 static inline unsigned int                                      \
2644 clear_##name(unsigned int clear)                                \
2645 {                                                               \
2646         unsigned int res, new;                                  \
2647                                                                 \
2648         res = read_##name();                                    \
2649         new = res & ~clear;                                     \
2650         write_##name(new);                                      \
2651                                                                 \
2652         return res;                                             \
2653 }                                                               \
2654                                                                 \
2655 static inline unsigned int                                      \
2656 change_##name(unsigned int change, unsigned int val)            \
2657 {                                                               \
2658         unsigned int res, new;                                  \
2659                                                                 \
2660         res = read_##name();                                    \
2661         new = res & ~change;                                    \
2662         new |= (val & change);                                  \
2663         write_##name(new);                                      \
2664                                                                 \
2665         return res;                                             \
2666 }
2667
2668 /*
2669  * Manipulate bits in a c0 register.
2670  */
2671 #define __BUILD_SET_C0(name)    __BUILD_SET_COMMON(c0_##name)
2672
2673 __BUILD_SET_C0(status)
2674 __BUILD_SET_C0(cause)
2675 __BUILD_SET_C0(config)
2676 __BUILD_SET_C0(config5)
2677 __BUILD_SET_C0(intcontrol)
2678 __BUILD_SET_C0(intctl)
2679 __BUILD_SET_C0(srsmap)
2680 __BUILD_SET_C0(pagegrain)
2681 __BUILD_SET_C0(guestctl0)
2682 __BUILD_SET_C0(guestctl0ext)
2683 __BUILD_SET_C0(guestctl1)
2684 __BUILD_SET_C0(guestctl2)
2685 __BUILD_SET_C0(guestctl3)
2686 __BUILD_SET_C0(brcm_config_0)
2687 __BUILD_SET_C0(brcm_bus_pll)
2688 __BUILD_SET_C0(brcm_reset)
2689 __BUILD_SET_C0(brcm_cmt_intr)
2690 __BUILD_SET_C0(brcm_cmt_ctrl)
2691 __BUILD_SET_C0(brcm_config)
2692 __BUILD_SET_C0(brcm_mode)
2693
2694 /*
2695  * Manipulate bits in a guest c0 register.
2696  */
2697 #define __BUILD_SET_GC0(name)   __BUILD_SET_COMMON(gc0_##name)
2698
2699 __BUILD_SET_GC0(status)
2700 __BUILD_SET_GC0(cause)
2701 __BUILD_SET_GC0(ebase)
2702
2703 /*
2704  * Return low 10 bits of ebase.
2705  * Note that under KVM (MIPSVZ) this returns vcpu id.
2706  */
2707 static inline unsigned int get_ebase_cpunum(void)
2708 {
2709         return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2710 }
2711
2712 #endif /* !__ASSEMBLY__ */
2713
2714 #endif /* _ASM_MIPSREGS_H */