2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
14 * This file essentially defines the interface between board
15 * specific PCI code and MIPS common PCI code. Should potentially put
16 * into include/asm/pci.h file.
19 #include <linux/ioport.h>
20 #include <linux/list.h>
24 * Each pci channel is a top-level PCI bus seem by CPU. A machine with
25 * multiple PCI channels may have multiple PCI host controllers or a
26 * single controller supporting multiple channels.
28 struct pci_controller {
29 struct list_head list;
31 struct device_node *of_node;
33 struct pci_ops *pci_ops;
34 struct resource *mem_resource;
35 unsigned long mem_offset;
36 struct resource *io_resource;
37 unsigned long io_offset;
38 unsigned long io_map_base;
39 struct resource *busn_resource;
40 unsigned long busn_offset;
42 #ifndef CONFIG_PCI_DOMAINS_GENERIC
44 /* For compatibility with current (as of July 2003) pciutils
45 and XFree86. Eventually will be removed. */
46 unsigned int need_domain_info;
49 /* Optional access methods for reading/writing the bus number
50 of the PCI controller */
51 int (*get_busno)(void);
52 void (*set_busno)(int busno);
56 * Used by boards to register their PCI busses before the actual scanning.
58 extern void register_pci_controller(struct pci_controller *hose);
61 * board supplied pci irq fixup routine
63 extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
66 /* Can be used to override the logic in pci_scan_bus for skipping
67 already-configured bus numbers - to be used for buggy BIOSes
68 or architectures with incomplete PCI setup by the loader */
70 extern unsigned int pcibios_assign_all_busses(void);
72 extern unsigned long PCIBIOS_MIN_IO;
73 extern unsigned long PCIBIOS_MIN_MEM;
75 #define PCIBIOS_MIN_CARDBUS_IO 0x4000
77 extern void pcibios_set_master(struct pci_dev *dev);
81 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
82 enum pci_mmap_state mmap_state, int write_combine);
84 #define HAVE_ARCH_PCI_RESOURCE_TO_USER
87 * Dynamic DMA mapping stuff.
88 * MIPS has everything mapped statically.
91 #include <linux/types.h>
92 #include <linux/slab.h>
93 #include <linux/scatterlist.h>
94 #include <linux/string.h>
100 * The PCI address space does equal the physical memory address space.
101 * The networking and block device layers use this boolean for bounce
104 #define PCI_DMA_BUS_IS_PHYS (1)
106 #ifdef CONFIG_PCI_DOMAINS_GENERIC
107 static inline int pci_proc_domain(struct pci_bus *bus)
109 return pci_domain_nr(bus);
112 static inline void set_pci_need_domain_info(struct pci_controller *hose,
113 int need_domain_info)
117 #elif defined(CONFIG_PCI_DOMAINS)
118 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
120 static inline int pci_proc_domain(struct pci_bus *bus)
122 struct pci_controller *hose = bus->sysdata;
123 return hose->need_domain_info;
126 static inline void set_pci_need_domain_info(struct pci_controller *hose,
127 int need_domain_info)
129 hose->need_domain_info = need_domain_info;
131 #endif /* CONFIG_PCI_DOMAINS */
133 #endif /* __KERNEL__ */
135 /* Do platform specific device initialization at pci_enable_device() time */
136 extern int pcibios_plat_dev_init(struct pci_dev *dev);
138 /* Chances are this interrupt is wired PC-style ... */
139 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
141 return channel ? 15 : 14;
144 extern char * (*pcibios_plat_setup)(char *str);
147 /* this function parses memory ranges from a device node */
148 extern void pci_load_of_ranges(struct pci_controller *hose,
149 struct device_node *node);
151 static inline void pci_load_of_ranges(struct pci_controller *hose,
152 struct device_node *node) {}
155 #endif /* _ASM_PCI_H */