2 * Copyright (C) 2013 Imagination Technologies
3 * Author: Paul Burton <paul.burton@imgtec.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
11 #include <asm/addrspace.h>
13 #include <asm/asm-offsets.h>
14 #include <asm/asmmacro.h>
15 #include <asm/cacheops.h>
17 #include <asm/mipsregs.h>
18 #include <asm/mipsmtregs.h>
21 #define GCR_CL_COHERENCE_OFS 0x2008
22 #define GCR_CL_ID_OFS 0x2028
29 # define STATUS_BITDEPS ST0_KX
31 # define STATUS_BITDEPS 0
34 #ifdef CONFIG_MIPS_CPS_NS16550
36 #define DUMP_EXCEP(name) \
38 jal mips_cps_bev_dump; \
42 #else /* !CONFIG_MIPS_CPS_NS16550 */
44 #define DUMP_EXCEP(name)
46 #endif /* !CONFIG_MIPS_CPS_NS16550 */
49 * Set dest to non-zero if the core supports the MT ASE, else zero. If
50 * MT is not supported then branch to nomt.
52 .macro has_mt dest, nomt
53 mfc0 \dest, CP0_CONFIG, 1
55 mfc0 \dest, CP0_CONFIG, 2
57 mfc0 \dest, CP0_CONFIG, 3
58 andi \dest, \dest, MIPS_CONF3_MT
63 .section .text.cps-vec
66 LEAF(mips_cps_core_entry)
68 * These first 4 bytes will be patched by cps_smp_setup to load the
69 * CCA to use into register s0.
73 /* Check whether we're here due to an NMI */
80 PTR_LA k0, nmi_handler
90 li t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS
94 * Clear the bits used to index the caches. Note that the architecture
95 * dictates that writing to any of TagLo or TagHi selects 0 or 2 should
96 * be valid for all MIPS32 CPUs, even those for which said writes are
99 mtc0 zero, CP0_TAGLO, 0
100 mtc0 zero, CP0_TAGHI, 0
101 mtc0 zero, CP0_TAGLO, 2
102 mtc0 zero, CP0_TAGHI, 2
105 /* Primary cache configuration is indicated by Config1 */
106 mfc0 v0, CP0_CONFIG, 1
108 /* Detect I-cache line size */
109 _EXT t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
114 /* Detect I-cache size */
115 _EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
121 1: /* At this point t1 == I-cache sets per way */
122 _EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
129 1: cache Index_Store_Tag_I, 0(a0)
135 /* Detect D-cache line size */
136 _EXT t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ
141 /* Detect D-cache size */
142 _EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
148 1: /* At this point t1 == D-cache sets per way */
149 _EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
157 1: cache Index_Store_Tag_D, 0(a0)
162 /* Set Kseg0 CCA to that in s0 */
170 /* Calculate an uncached address for the CM GCRs */
171 MFC0 v1, CP0_CMGCRBASE
173 PTR_LI t0, UNCAC_BASE
176 /* Enter the coherent domain */
178 sw t0, GCR_CL_COHERENCE_OFS(v1)
187 * We're up, cached & coherent. Perform any further required core-level
190 1: jal mips_cps_core_init
193 /* Do any EVA initialization if necessary */
197 * Boot any other VPEs within this core that should be online, and
198 * deactivate this VPE if it should be offline.
200 jal mips_cps_boot_vpes
204 PTR_L t1, VPEBOOTCFG_PC(v0)
205 PTR_L gp, VPEBOOTCFG_GP(v0)
206 PTR_L sp, VPEBOOTCFG_SP(v0)
209 END(mips_cps_core_entry)
213 DUMP_EXCEP("TLB Fill")
220 DUMP_EXCEP("XTLB Fill")
234 DUMP_EXCEP("General")
241 DUMP_EXCEP("Interrupt")
249 PTR_LA k0, ejtag_debug_handler
254 LEAF(mips_cps_core_init)
255 #ifdef CONFIG_MIPS_MT_SMP
256 /* Check that the core implements the MT ASE */
263 /* Only allow 1 TC per VPE to execute... */
266 /* ...and for the moment only 1 VPE */
272 /* Enter VPE configuration state */
273 1: mfc0 t0, CP0_MVPCONTROL
274 ori t0, t0, MVPCONTROL_VPC
275 mtc0 t0, CP0_MVPCONTROL
277 /* Retrieve the number of VPEs within the core */
278 mfc0 t0, CP0_MVPCONF0
279 srl t0, t0, MVPCONF0_PVPE_SHIFT
280 andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
283 /* If there's only 1, we're done */
287 /* Loop through each VPE within this core */
290 1: /* Operate on the appropriate TC */
291 mtc0 ta1, CP0_VPECONTROL
294 /* Bind TC to VPE (1:1 TC:VPE mapping) */
295 mttc0 ta1, CP0_TCBIND
297 /* Set exclusive TC, non-active, master */
299 sll t1, ta1, VPECONF0_XTC_SHIFT
301 mttc0 t0, CP0_VPECONF0
303 /* Set TC non-active, non-allocatable */
304 mttc0 zero, CP0_TCSTATUS
316 /* Leave VPE configuration state */
317 2: mfc0 t0, CP0_MVPCONTROL
318 xori t0, t0, MVPCONTROL_VPC
319 mtc0 t0, CP0_MVPCONTROL
325 END(mips_cps_core_init)
327 LEAF(mips_cps_boot_vpes)
328 /* Retrieve CM base address */
329 PTR_LA t0, mips_cm_base
332 /* Calculate a pointer to this cores struct core_boot_config */
333 lw t0, GCR_CL_ID_OFS(t0)
334 li t1, COREBOOTCFG_SIZE
336 PTR_LA t1, mips_cps_core_bootcfg
340 /* Calculate this VPEs ID. If the core doesn't support MT use 0 */
342 #ifdef CONFIG_MIPS_MT_SMP
345 /* Find the number of VPEs present in the core */
346 mfc0 t1, CP0_MVPCONF0
347 srl t1, t1, MVPCONF0_PVPE_SHIFT
348 andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
351 /* Calculate a mask for the VPE ID from EBase.CPUNum */
359 /* Retrieve the VPE ID from EBase.CPUNum */
364 1: /* Calculate a pointer to this VPEs struct vpe_boot_config */
365 li t1, VPEBOOTCFG_SIZE
367 PTR_L ta3, COREBOOTCFG_VPECONFIG(t0)
370 #ifdef CONFIG_MIPS_MT_SMP
372 /* If the core doesn't support MT then return */
382 1: /* Enter VPE configuration state */
387 1: mfc0 t1, CP0_MVPCONTROL
388 ori t1, t1, MVPCONTROL_VPC
389 mtc0 t1, CP0_MVPCONTROL
392 /* Loop through each VPE */
393 PTR_L ta2, COREBOOTCFG_VPEMASK(t0)
397 /* Check whether the VPE should be running. If not, skip it */
402 /* Operate on the appropriate TC */
403 mfc0 t0, CP0_VPECONTROL
404 ori t0, t0, VPECONTROL_TARGTC
405 xori t0, t0, VPECONTROL_TARGTC
407 mtc0 t0, CP0_VPECONTROL
410 /* Skip the VPE if its TC is not halted */
415 /* Calculate a pointer to the VPEs struct vpe_boot_config */
416 li t0, VPEBOOTCFG_SIZE
420 /* Set the TC restart PC */
421 lw t1, VPEBOOTCFG_PC(t0)
422 mttc0 t1, CP0_TCRESTART
424 /* Set the TC stack pointer */
425 lw t1, VPEBOOTCFG_SP(t0)
428 /* Set the TC global pointer */
429 lw t1, VPEBOOTCFG_GP(t0)
432 /* Copy config from this VPE */
436 /* Ensure no software interrupts are pending */
437 mttc0 zero, CP0_CAUSE
438 mttc0 zero, CP0_STATUS
440 /* Set TC active, not interrupt exempt */
441 mftc0 t0, CP0_TCSTATUS
442 li t1, ~TCSTATUS_IXMT
444 ori t0, t0, TCSTATUS_A
445 mttc0 t0, CP0_TCSTATUS
447 /* Clear the TC halt bit */
448 mttc0 zero, CP0_TCHALT
451 mftc0 t0, CP0_VPECONF0
452 ori t0, t0, VPECONF0_VPA
453 mttc0 t0, CP0_VPECONF0
461 /* Leave VPE configuration state */
462 mfc0 t1, CP0_MVPCONTROL
463 xori t1, t1, MVPCONTROL_VPC
464 mtc0 t1, CP0_MVPCONTROL
468 /* Check whether this VPE is meant to be running */
475 /* This VPE should be offline, halt the TC */
484 #endif /* CONFIG_MIPS_MT_SMP */
489 END(mips_cps_boot_vpes)
491 #if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM)
493 /* Calculate a pointer to this CPUs struct mips_static_suspend_state */
499 PTR_LA \dest, __per_cpu_offset
502 PTR_LA \dest, cps_cpu_state
503 addu \dest, \dest, $1
507 LEAF(mips_cps_pm_save)
514 END(mips_cps_pm_save)
516 LEAF(mips_cps_pm_restore)
517 /* Restore CPU state */
519 RESUME_RESTORE_STATIC
520 RESUME_RESTORE_REGS_RETURN
521 END(mips_cps_pm_restore)
523 #endif /* CONFIG_MIPS_CPS_PM && CONFIG_CPU_PM */