2 * Copyright (C) 2013 Imagination Technologies
3 * Author: Paul Burton <paul.burton@imgtec.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
11 #include <asm/addrspace.h>
13 #include <asm/asm-offsets.h>
14 #include <asm/asmmacro.h>
15 #include <asm/cacheops.h>
17 #include <asm/mipsregs.h>
18 #include <asm/mipsmtregs.h>
21 #define GCR_CL_COHERENCE_OFS 0x2008
22 #define GCR_CL_ID_OFS 0x2028
29 * Set dest to non-zero if the core supports the MT ASE, else zero. If
30 * MT is not supported then branch to nomt.
32 .macro has_mt dest, nomt
33 mfc0 \dest, CP0_CONFIG
35 mfc0 \dest, CP0_CONFIG, 1
37 mfc0 \dest, CP0_CONFIG, 2
39 mfc0 \dest, CP0_CONFIG, 3
40 andi \dest, \dest, MIPS_CONF3_MT
45 .section .text.cps-vec
48 LEAF(mips_cps_core_entry)
50 * These first 12 bytes will be patched by cps_smp_setup to load the
51 * base address of the CM GCRs into register v1 and the CCA to use into
57 /* Check whether we're here due to an NMI */
64 PTR_LA k0, nmi_handler
74 li t0, ST0_CU1 | ST0_CU0
78 * Clear the bits used to index the caches. Note that the architecture
79 * dictates that writing to any of TagLo or TagHi selects 0 or 2 should
80 * be valid for all MIPS32 CPUs, even those for which said writes are
83 mtc0 zero, CP0_TAGLO, 0
84 mtc0 zero, CP0_TAGHI, 0
85 mtc0 zero, CP0_TAGLO, 2
86 mtc0 zero, CP0_TAGHI, 2
89 /* Primary cache configuration is indicated by Config1 */
90 mfc0 v0, CP0_CONFIG, 1
92 /* Detect I-cache line size */
93 _EXT t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
98 /* Detect I-cache size */
99 _EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
105 1: /* At this point t1 == I-cache sets per way */
106 _EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
113 1: cache Index_Store_Tag_I, 0(a0)
119 /* Detect D-cache line size */
120 _EXT t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ
125 /* Detect D-cache size */
126 _EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
132 1: /* At this point t1 == D-cache sets per way */
133 _EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
141 1: cache Index_Store_Tag_D, 0(a0)
146 /* Set Kseg0 CCA to that in s0 */
154 /* Enter the coherent domain */
156 sw t0, GCR_CL_COHERENCE_OFS(v1)
165 * We're up, cached & coherent. Perform any further required core-level
168 1: jal mips_cps_core_init
171 /* Do any EVA initialization if necessary */
175 * Boot any other VPEs within this core that should be online, and
176 * deactivate this VPE if it should be offline.
178 jal mips_cps_boot_vpes
182 PTR_L t1, VPEBOOTCFG_PC(v0)
183 PTR_L gp, VPEBOOTCFG_GP(v0)
184 PTR_L sp, VPEBOOTCFG_SP(v0)
187 END(mips_cps_core_entry)
221 PTR_LA k0, ejtag_debug_handler
226 LEAF(mips_cps_core_init)
227 #ifdef CONFIG_MIPS_MT_SMP
228 /* Check that the core implements the MT ASE */
235 /* Only allow 1 TC per VPE to execute... */
238 /* ...and for the moment only 1 VPE */
244 /* Enter VPE configuration state */
245 1: mfc0 t0, CP0_MVPCONTROL
246 ori t0, t0, MVPCONTROL_VPC
247 mtc0 t0, CP0_MVPCONTROL
249 /* Retrieve the number of VPEs within the core */
250 mfc0 t0, CP0_MVPCONF0
251 srl t0, t0, MVPCONF0_PVPE_SHIFT
252 andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
255 /* If there's only 1, we're done */
259 /* Loop through each VPE within this core */
262 1: /* Operate on the appropriate TC */
263 mtc0 ta1, CP0_VPECONTROL
266 /* Bind TC to VPE (1:1 TC:VPE mapping) */
267 mttc0 ta1, CP0_TCBIND
269 /* Set exclusive TC, non-active, master */
271 sll t1, ta1, VPECONF0_XTC_SHIFT
273 mttc0 t0, CP0_VPECONF0
275 /* Set TC non-active, non-allocatable */
276 mttc0 zero, CP0_TCSTATUS
288 /* Leave VPE configuration state */
289 2: mfc0 t0, CP0_MVPCONTROL
290 xori t0, t0, MVPCONTROL_VPC
291 mtc0 t0, CP0_MVPCONTROL
297 END(mips_cps_core_init)
299 LEAF(mips_cps_boot_vpes)
300 /* Retrieve CM base address */
301 PTR_LA t0, mips_cm_base
304 /* Calculate a pointer to this cores struct core_boot_config */
305 lw t0, GCR_CL_ID_OFS(t0)
306 li t1, COREBOOTCFG_SIZE
308 PTR_LA t1, mips_cps_core_bootcfg
312 /* Calculate this VPEs ID. If the core doesn't support MT use 0 */
314 #ifdef CONFIG_MIPS_MT_SMP
317 /* Find the number of VPEs present in the core */
318 mfc0 t1, CP0_MVPCONF0
319 srl t1, t1, MVPCONF0_PVPE_SHIFT
320 andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
323 /* Calculate a mask for the VPE ID from EBase.CPUNum */
331 /* Retrieve the VPE ID from EBase.CPUNum */
336 1: /* Calculate a pointer to this VPEs struct vpe_boot_config */
337 li t1, VPEBOOTCFG_SIZE
339 PTR_L ta3, COREBOOTCFG_VPECONFIG(t0)
342 #ifdef CONFIG_MIPS_MT_SMP
344 /* If the core doesn't support MT then return */
354 1: /* Enter VPE configuration state */
359 1: mfc0 t1, CP0_MVPCONTROL
360 ori t1, t1, MVPCONTROL_VPC
361 mtc0 t1, CP0_MVPCONTROL
364 /* Loop through each VPE */
365 PTR_L ta2, COREBOOTCFG_VPEMASK(t0)
369 /* Check whether the VPE should be running. If not, skip it */
374 /* Operate on the appropriate TC */
375 mfc0 t0, CP0_VPECONTROL
376 ori t0, t0, VPECONTROL_TARGTC
377 xori t0, t0, VPECONTROL_TARGTC
379 mtc0 t0, CP0_VPECONTROL
382 /* Skip the VPE if its TC is not halted */
387 /* Calculate a pointer to the VPEs struct vpe_boot_config */
388 li t0, VPEBOOTCFG_SIZE
392 /* Set the TC restart PC */
393 lw t1, VPEBOOTCFG_PC(t0)
394 mttc0 t1, CP0_TCRESTART
396 /* Set the TC stack pointer */
397 lw t1, VPEBOOTCFG_SP(t0)
400 /* Set the TC global pointer */
401 lw t1, VPEBOOTCFG_GP(t0)
404 /* Copy config from this VPE */
408 /* Ensure no software interrupts are pending */
409 mttc0 zero, CP0_CAUSE
410 mttc0 zero, CP0_STATUS
412 /* Set TC active, not interrupt exempt */
413 mftc0 t0, CP0_TCSTATUS
414 li t1, ~TCSTATUS_IXMT
416 ori t0, t0, TCSTATUS_A
417 mttc0 t0, CP0_TCSTATUS
419 /* Clear the TC halt bit */
420 mttc0 zero, CP0_TCHALT
423 mftc0 t0, CP0_VPECONF0
424 ori t0, t0, VPECONF0_VPA
425 mttc0 t0, CP0_VPECONF0
433 /* Leave VPE configuration state */
434 mfc0 t1, CP0_MVPCONTROL
435 xori t1, t1, MVPCONTROL_VPC
436 mtc0 t1, CP0_MVPCONTROL
440 /* Check whether this VPE is meant to be running */
447 /* This VPE should be offline, halt the TC */
456 #endif /* CONFIG_MIPS_MT_SMP */
461 END(mips_cps_boot_vpes)
463 #if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM)
465 /* Calculate a pointer to this CPUs struct mips_static_suspend_state */
471 PTR_LA \dest, __per_cpu_offset
474 PTR_LA \dest, cps_cpu_state
475 addu \dest, \dest, $1
479 LEAF(mips_cps_pm_save)
486 END(mips_cps_pm_save)
488 LEAF(mips_cps_pm_restore)
489 /* Restore CPU state */
491 RESUME_RESTORE_STATIC
492 RESUME_RESTORE_REGS_RETURN
493 END(mips_cps_pm_restore)
495 #endif /* CONFIG_MIPS_CPS_PM && CONFIG_CPU_PM */