1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2003, 2004, 2007 Maciej W. Rozycki
5 #include <linux/context_tracking.h>
6 #include <linux/init.h>
7 #include <linux/kernel.h>
8 #include <linux/ptrace.h>
9 #include <linux/stddef.h>
12 #include <asm/compiler.h>
15 #include <asm/mipsregs.h>
16 #include <asm/setup.h>
18 static char bug64hit[] __initdata =
19 "reliable operation impossible!\n%s";
20 static char nowar[] __initdata =
21 "Please report to <linux-mips@linux-mips.org>.";
22 static char r4kwar[] __initdata =
23 "Enable CPU_R4000_WORKAROUNDS to rectify.";
24 static char daddiwar[] __initdata =
25 "Enable CPU_DADDI_WORKAROUNDS to rectify.";
27 static inline void align_mod(const int align, const int mod)
38 : "n"(align), "n"(mod));
41 static __always_inline void mult_sh_align_mod(long *v1, long *v2, long *w,
42 const int align, const int mod)
46 long p, s, lv1, lv2, lw;
49 * We want the multiply and the shift to be isolated from the
50 * rest of the code to disable gcc optimizations. Hence the
51 * asm statements that execute nothing, but make gcc not know
52 * what the values of m1, m2 and s are and what lv2 and p are
56 local_irq_save(flags);
58 * The following code leads to a wrong result of the first
59 * dsll32 when executed on R4000 rev. 2.2 or 3.0 (PRId
60 * 00000422 or 00000430, respectively).
62 * See "MIPS R4000PC/SC Errata, Processor Revision 2.2 and
63 * 3.0" by MIPS Technologies, Inc., errata #16 and #28 for
64 * details. I got no permission to duplicate them here,
69 : "=r" (m1), "=r" (m2), "=r" (s)
70 : "0" (5), "1" (8), "2" (5));
71 align_mod(align, mod);
73 * The trailing nop is needed to fulfill the two-instruction
74 * requirement between reading hi/lo and staring a mult/div.
75 * Leaving it out may cause gas insert a nop itself breaking
76 * the desired alignment of the next chunk.
84 "dsll32 %0, %4, %5\n\t"
86 "dsll32 %1, %4, %5\n\t"
89 : "=&r" (lv1), "=r" (lw)
90 : "r" (m1), "r" (m2), "r" (s), "I" (0)
92 /* We have to use single integers for m1 and m2 and a double
93 * one for p to be sure the mulsidi3 gcc's RTL multiplication
94 * instruction has the workaround applied. Older versions of
95 * gcc have correct umulsi3 and mulsi3, but other
96 * multiplication variants lack the workaround.
100 : "=r" (m1), "=r" (m2), "=r" (s)
101 : "0" (m1), "1" (m2), "2" (s));
102 align_mod(align, mod);
108 : "0" (lv2), "r" (p));
109 local_irq_restore(flags);
116 static inline void check_mult_sh(void)
118 long v1[8], v2[8], w[8];
121 printk("Checking for the multiply/shift bug... ");
124 * Testing discovered false negatives for certain code offsets
125 * into cache lines. Hence we test all possible offsets for
126 * the worst assumption of an R4000 I-cache line width of 32
129 * We can't use a loop as alignment directives need to be
132 mult_sh_align_mod(&v1[0], &v2[0], &w[0], 32, 0);
133 mult_sh_align_mod(&v1[1], &v2[1], &w[1], 32, 1);
134 mult_sh_align_mod(&v1[2], &v2[2], &w[2], 32, 2);
135 mult_sh_align_mod(&v1[3], &v2[3], &w[3], 32, 3);
136 mult_sh_align_mod(&v1[4], &v2[4], &w[4], 32, 4);
137 mult_sh_align_mod(&v1[5], &v2[5], &w[5], 32, 5);
138 mult_sh_align_mod(&v1[6], &v2[6], &w[6], 32, 6);
139 mult_sh_align_mod(&v1[7], &v2[7], &w[7], 32, 7);
142 for (i = 0; i < 8; i++)
151 pr_cont("yes, workaround... ");
154 for (i = 0; i < 8; i++)
164 panic(bug64hit, !R4000_WAR ? r4kwar : nowar);
167 static volatile int daddi_ov;
169 asmlinkage void __init do_daddi_ov(struct pt_regs *regs)
171 enum ctx_state prev_state;
173 prev_state = exception_enter();
176 exception_exit(prev_state);
179 static inline void check_daddi(void)
181 extern asmlinkage void handle_daddi_ov(void);
186 printk("Checking for the daddi bug... ");
188 local_irq_save(flags);
189 handler = set_except_vector(EXCCODE_OV, handle_daddi_ov);
191 * The following code fails to trigger an overflow exception
192 * when executed on R4000 rev. 2.2 or 3.0 (PRId 00000422 or
193 * 00000430, respectively).
195 * See "MIPS R4000PC/SC Errata, Processor Revision 2.2 and
196 * 3.0" by MIPS Technologies, Inc., erratum #23 for details.
197 * I got no permission to duplicate it here, sigh... --macro
204 "addiu %1, $0, %2\n\t"
206 #ifdef HAVE_AS_SET_DADDI
209 "daddi %0, %1, %3\n\t"
211 : "=r" (v), "=&r" (tmp)
212 : "I" (0xffffffffffffdb9aUL), "I" (0x1234));
213 set_except_vector(EXCCODE_OV, handler);
214 local_irq_restore(flags);
221 pr_cont("yes, workaround... ");
223 local_irq_save(flags);
224 handler = set_except_vector(EXCCODE_OV, handle_daddi_ov);
226 "addiu %1, $0, %2\n\t"
229 : "=r" (v), "=&r" (tmp)
230 : "I" (0xffffffffffffdb9aUL), "I" (0x1234));
231 set_except_vector(EXCCODE_OV, handler);
232 local_irq_restore(flags);
240 panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
243 int daddiu_bug = IS_ENABLED(CONFIG_CPU_MIPSR6) ? 0 : -1;
245 static inline void check_daddiu(void)
249 printk("Checking for the daddiu bug... ");
252 * The following code leads to a wrong result of daddiu when
253 * executed on R4400 rev. 1.0 (PRId 00000440).
255 * See "MIPS R4400PC/SC Errata, Processor Revision 1.0" by
256 * MIPS Technologies, Inc., erratum #7 for details.
258 * According to "MIPS R4000PC/SC Errata, Processor Revision
259 * 2.2 and 3.0" by MIPS Technologies, Inc., erratum #41 this
260 * problem affects R4000 rev. 2.2 and 3.0 (PRId 00000422 and
261 * 00000430, respectively), too. Testing failed to trigger it
264 * I got no permission to duplicate the errata here, sigh...
272 "addiu %2, $0, %3\n\t"
274 #ifdef HAVE_AS_SET_DADDI
277 "daddiu %0, %2, %4\n\t"
278 "addiu %1, $0, %4\n\t"
281 : "=&r" (v), "=&r" (w), "=&r" (tmp)
282 : "I" (0xffffffffffffdb9aUL), "I" (0x1234));
291 pr_cont("yes, workaround... ");
294 "addiu %2, $0, %3\n\t"
296 "daddiu %0, %2, %4\n\t"
297 "addiu %1, $0, %4\n\t"
299 : "=&r" (v), "=&r" (w), "=&r" (tmp)
300 : "I" (0xffffffffffffdb9aUL), "I" (0x1234));
308 panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
311 void __init check_bugs64_early(void)
313 if (!IS_ENABLED(CONFIG_CPU_MIPSR6)) {
319 void __init check_bugs64(void)
321 if (!IS_ENABLED(CONFIG_CPU_MIPSR6))