arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/smp.h>
  18 #include <linux/stddef.h>
  19 #include <linux/export.h>
  20
  21 #include <asm/bugs.h>
  22 #include <asm/cpu.h>
  23 #include <asm/cpu-features.h>
  24 #include <asm/cpu-type.h>
  25 #include <asm/fpu.h>
  26 #include <asm/mipsregs.h>
  27 #include <asm/mipsmtregs.h>
  28 #include <asm/msa.h>
  29 #include <asm/watch.h>
  30 #include <asm/elf.h>
  31 #include <asm/pgtable-bits.h>
  32 #include <asm/spram.h>
  33 #include <asm/uaccess.h>
  34
  35 /* Hardware capabilities */
  36 unsigned int elf_hwcap __read_mostly;
  37
  38 /*
  39  * Get the FPU Implementation/Revision.
  40  */
  41 static inline unsigned long cpu_get_fpu_id(void)
  42 {
  43         unsigned long tmp, fpu_id;
  44
  45         tmp = read_c0_status();
  46         __enable_fpu(FPU_AS_IS);
  47         fpu_id = read_32bit_cp1_register(CP1_REVISION);
  48         write_c0_status(tmp);
  49         return fpu_id;
  50 }
  51
  52 /*
  53  * Check if the CPU has an external FPU.
  54  */
  55 static inline int __cpu_has_fpu(void)
  56 {
  57         return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
  58 }
  59
  60 static inline unsigned long cpu_get_msa_id(void)
  61 {
  62         unsigned long status, msa_id;
  63
  64         status = read_c0_status();
  65         __enable_fpu(FPU_64BIT);
  66         enable_msa();
  67         msa_id = read_msa_ir();
  68         disable_msa();
  69         write_c0_status(status);
  70         return msa_id;
  71 }
  72
  73 /*
  74  * Determine the FCSR mask for FPU hardware.
  75  */
  76 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
  77 {
  78         unsigned long sr, mask, fcsr, fcsr0, fcsr1;
  79
  80         fcsr = c->fpu_csr31;
  81         mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
  82
  83         sr = read_c0_status();
  84         __enable_fpu(FPU_AS_IS);
  85
  86         fcsr0 = fcsr & mask;
  87         write_32bit_cp1_register(CP1_STATUS, fcsr0);
  88         fcsr0 = read_32bit_cp1_register(CP1_STATUS);
  89
  90         fcsr1 = fcsr | ~mask;
  91         write_32bit_cp1_register(CP1_STATUS, fcsr1);
  92         fcsr1 = read_32bit_cp1_register(CP1_STATUS);
  93
  94         write_32bit_cp1_register(CP1_STATUS, fcsr);
  95
  96         write_c0_status(sr);
  97
  98         c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
  99 }
 100
 101 /*
 102  * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
 103  * supported by FPU hardware.
 104  */
 105 static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
 106 {
 107         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 108                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 109                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
 110                 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
 111
 112                 sr = read_c0_status();
 113                 __enable_fpu(FPU_AS_IS);
 114
 115                 fir = read_32bit_cp1_register(CP1_REVISION);
 116                 if (fir & MIPS_FPIR_HAS2008) {
 117                         fcsr = read_32bit_cp1_register(CP1_STATUS);
 118
 119                         fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
 120                         write_32bit_cp1_register(CP1_STATUS, fcsr0);
 121                         fcsr0 = read_32bit_cp1_register(CP1_STATUS);
 122
 123                         fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
 124                         write_32bit_cp1_register(CP1_STATUS, fcsr1);
 125                         fcsr1 = read_32bit_cp1_register(CP1_STATUS);
 126
 127                         write_32bit_cp1_register(CP1_STATUS, fcsr);
 128
 129                         if (!(fcsr0 & FPU_CSR_NAN2008))
 130                                 c->options |= MIPS_CPU_NAN_LEGACY;
 131                         if (fcsr1 & FPU_CSR_NAN2008)
 132                                 c->options |= MIPS_CPU_NAN_2008;
 133
 134                         if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
 135                                 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
 136                         else
 137                                 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
 138
 139                         if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
 140                                 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
 141                         else
 142                                 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
 143                 } else {
 144                         c->options |= MIPS_CPU_NAN_LEGACY;
 145                 }
 146
 147                 write_c0_status(sr);
 148         } else {
 149                 c->options |= MIPS_CPU_NAN_LEGACY;
 150         }
 151 }
 152
 153 /*
 154  * IEEE 754 conformance mode to use.  Affects the NaN encoding and the
 155  * ABS.fmt/NEG.fmt execution mode.
 156  */
 157 static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
 158
 159 /*
 160  * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
 161  * to support by the FPU emulator according to the IEEE 754 conformance
 162  * mode selected.  Note that "relaxed" straps the emulator so that it
 163  * allows 2008-NaN binaries even for legacy processors.
 164  */
 165 static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
 166 {
 167         c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
 168         c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
 169         c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
 170
 171         switch (ieee754) {
 172         case STRICT:
 173                 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 174                                     MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 175                                     MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
 176                         c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
 177                 } else {
 178                         c->options |= MIPS_CPU_NAN_LEGACY;
 179                         c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
 180                 }
 181                 break;
 182         case LEGACY:
 183                 c->options |= MIPS_CPU_NAN_LEGACY;
 184                 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
 185                 break;
 186         case STD2008:
 187                 c->options |= MIPS_CPU_NAN_2008;
 188                 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
 189                 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
 190                 break;
 191         case RELAXED:
 192                 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
 193                 break;
 194         }
 195 }
 196
 197 /*
 198  * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
 199  * according to the "ieee754=" parameter.
 200  */
 201 static void cpu_set_nan_2008(struct cpuinfo_mips *c)
 202 {
 203         switch (ieee754) {
 204         case STRICT:
 205                 mips_use_nan_legacy = !!cpu_has_nan_legacy;
 206                 mips_use_nan_2008 = !!cpu_has_nan_2008;
 207                 break;
 208         case LEGACY:
 209                 mips_use_nan_legacy = !!cpu_has_nan_legacy;
 210                 mips_use_nan_2008 = !cpu_has_nan_legacy;
 211                 break;
 212         case STD2008:
 213                 mips_use_nan_legacy = !cpu_has_nan_2008;
 214                 mips_use_nan_2008 = !!cpu_has_nan_2008;
 215                 break;
 216         case RELAXED:
 217                 mips_use_nan_legacy = true;
 218                 mips_use_nan_2008 = true;
 219                 break;
 220         }
 221 }
 222
 223 /*
 224  * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
 225  * settings:
 226  *
 227  * strict:  accept binaries that request a NaN encoding supported by the FPU
 228  * legacy:  only accept legacy-NaN binaries
 229  * 2008:    only accept 2008-NaN binaries
 230  * relaxed: accept any binaries regardless of whether supported by the FPU
 231  */
 232 static int __init ieee754_setup(char *s)
 233 {
 234         if (!s)
 235                 return -1;
 236         else if (!strcmp(s, "strict"))
 237                 ieee754 = STRICT;
 238         else if (!strcmp(s, "legacy"))
 239                 ieee754 = LEGACY;
 240         else if (!strcmp(s, "2008"))
 241                 ieee754 = STD2008;
 242         else if (!strcmp(s, "relaxed"))
 243                 ieee754 = RELAXED;
 244         else
 245                 return -1;
 246
 247         if (!(boot_cpu_data.options & MIPS_CPU_FPU))
 248                 cpu_set_nofpu_2008(&boot_cpu_data);
 249         cpu_set_nan_2008(&boot_cpu_data);
 250
 251         return 0;
 252 }
 253
 254 early_param("ieee754", ieee754_setup);
 255
 256 /*
 257  * Set the FIR feature flags for the FPU emulator.
 258  */
 259 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
 260 {
 261         u32 value;
 262
 263         value = 0;
 264         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 265                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 266                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
 267                 value |= MIPS_FPIR_D | MIPS_FPIR_S;
 268         if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 269                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
 270                 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
 271         if (c->options & MIPS_CPU_NAN_2008)
 272                 value |= MIPS_FPIR_HAS2008;
 273         c->fpu_id = value;
 274 }
 275
 276 /* Determined FPU emulator mask to use for the boot CPU with "nofpu".  */
 277 static unsigned int mips_nofpu_msk31;
 278
 279 /*
 280  * Set options for FPU hardware.
 281  */
 282 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
 283 {
 284         c->fpu_id = cpu_get_fpu_id();
 285         mips_nofpu_msk31 = c->fpu_msk31;
 286
 287         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 288                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 289                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
 290                 if (c->fpu_id & MIPS_FPIR_3D)
 291                         c->ases |= MIPS_ASE_MIPS3D;
 292                 if (c->fpu_id & MIPS_FPIR_FREP)
 293                         c->options |= MIPS_CPU_FRE;
 294         }
 295
 296         cpu_set_fpu_fcsr_mask(c);
 297         cpu_set_fpu_2008(c);
 298         cpu_set_nan_2008(c);
 299 }
 300
 301 /*
 302  * Set options for the FPU emulator.
 303  */
 304 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
 305 {
 306         c->options &= ~MIPS_CPU_FPU;
 307         c->fpu_msk31 = mips_nofpu_msk31;
 308
 309         cpu_set_nofpu_2008(c);
 310         cpu_set_nan_2008(c);
 311         cpu_set_nofpu_id(c);
 312 }
 313
 314 static int mips_fpu_disabled;
 315
 316 static int __init fpu_disable(char *s)
 317 {
 318         cpu_set_nofpu_opts(&boot_cpu_data);
 319         mips_fpu_disabled = 1;
 320
 321         return 1;
 322 }
 323
 324 __setup("nofpu", fpu_disable);
 325
 326 int mips_dsp_disabled;
 327
 328 static int __init dsp_disable(char *s)
 329 {
 330         cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
 331         mips_dsp_disabled = 1;
 332
 333         return 1;
 334 }
 335
 336 __setup("nodsp", dsp_disable);
 337
 338 static int mips_htw_disabled;
 339
 340 static int __init htw_disable(char *s)
 341 {
 342         mips_htw_disabled = 1;
 343         cpu_data[0].options &= ~MIPS_CPU_HTW;
 344         write_c0_pwctl(read_c0_pwctl() &
 345                        ~(1 << MIPS_PWCTL_PWEN_SHIFT));
 346
 347         return 1;
 348 }
 349
 350 __setup("nohtw", htw_disable);
 351
 352 static int mips_ftlb_disabled;
 353 static int mips_has_ftlb_configured;
 354
 355 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
 356
 357 static int __init ftlb_disable(char *s)
 358 {
 359         unsigned int config4, mmuextdef;
 360
 361         /*
 362          * If the core hasn't done any FTLB configuration, there is nothing
 363          * for us to do here.
 364          */
 365         if (!mips_has_ftlb_configured)
 366                 return 1;
 367
 368         /* Disable it in the boot cpu */
 369         if (set_ftlb_enable(&cpu_data[0], 0)) {
 370                 pr_warn("Can't turn FTLB off\n");
 371                 return 1;
 372         }
 373
 374         back_to_back_c0_hazard();
 375
 376         config4 = read_c0_config4();
 377
 378         /* Check that FTLB has been disabled */
 379         mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 380         /* MMUSIZEEXT == VTLB ON, FTLB OFF */
 381         if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
 382                 /* This should never happen */
 383                 pr_warn("FTLB could not be disabled!\n");
 384                 return 1;
 385         }
 386
 387         mips_ftlb_disabled = 1;
 388         mips_has_ftlb_configured = 0;
 389
 390         /*
 391          * noftlb is mainly used for debug purposes so print
 392          * an informative message instead of using pr_debug()
 393          */
 394         pr_info("FTLB has been disabled\n");
 395
 396         /*
 397          * Some of these bits are duplicated in the decode_config4.
 398          * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
 399          * once FTLB has been disabled so undo what decode_config4 did.
 400          */
 401         cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
 402                                cpu_data[0].tlbsizeftlbsets;
 403         cpu_data[0].tlbsizeftlbsets = 0;
 404         cpu_data[0].tlbsizeftlbways = 0;
 405
 406         return 1;
 407 }
 408
 409 __setup("noftlb", ftlb_disable);
 410
 411
 412 static inline void check_errata(void)
 413 {
 414         struct cpuinfo_mips *c = &current_cpu_data;
 415
 416         switch (current_cpu_type()) {
 417         case CPU_34K:
 418                 /*
 419                  * Erratum "RPS May Cause Incorrect Instruction Execution"
 420                  * This code only handles VPE0, any SMP/RTOS code
 421                  * making use of VPE1 will be responsable for that VPE.
 422                  */
 423                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
 424                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
 425                 break;
 426         default:
 427                 break;
 428         }
 429 }
 430
 431 void __init check_bugs32(void)
 432 {
 433         check_errata();
 434 }
 435
 436 /*
 437  * Probe whether cpu has config register by trying to play with
 438  * alternate cache bit and see whether it matters.
 439  * It's used by cpu_probe to distinguish between R3000A and R3081.
 440  */
 441 static inline int cpu_has_confreg(void)
 442 {
 443 #ifdef CONFIG_CPU_R3000
 444         extern unsigned long r3k_cache_size(unsigned long);
 445         unsigned long size1, size2;
 446         unsigned long cfg = read_c0_conf();
 447
 448         size1 = r3k_cache_size(ST0_ISC);
 449         write_c0_conf(cfg ^ R30XX_CONF_AC);
 450         size2 = r3k_cache_size(ST0_ISC);
 451         write_c0_conf(cfg);
 452         return size1 != size2;
 453 #else
 454         return 0;
 455 #endif
 456 }
 457
 458 static inline void set_elf_platform(int cpu, const char *plat)
 459 {
 460         if (cpu == 0)
 461                 __elf_platform = plat;
 462 }
 463
 464 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 465 {
 466 #ifdef __NEED_VMBITS_PROBE
 467         write_c0_entryhi(0x3fffffffffffe000ULL);
 468         back_to_back_c0_hazard();
 469         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 470 #endif
 471 }
 472
 473 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
 474 {
 475         switch (isa) {
 476         case MIPS_CPU_ISA_M64R2:
 477                 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
 478         case MIPS_CPU_ISA_M64R1:
 479                 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
 480         case MIPS_CPU_ISA_V:
 481                 c->isa_level |= MIPS_CPU_ISA_V;
 482         case MIPS_CPU_ISA_IV:
 483                 c->isa_level |= MIPS_CPU_ISA_IV;
 484         case MIPS_CPU_ISA_III:
 485                 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
 486                 break;
 487
 488         /* R6 incompatible with everything else */
 489         case MIPS_CPU_ISA_M64R6:
 490                 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
 491         case MIPS_CPU_ISA_M32R6:
 492                 c->isa_level |= MIPS_CPU_ISA_M32R6;
 493                 /* Break here so we don't add incompatible ISAs */
 494                 break;
 495         case MIPS_CPU_ISA_M32R2:
 496                 c->isa_level |= MIPS_CPU_ISA_M32R2;
 497         case MIPS_CPU_ISA_M32R1:
 498                 c->isa_level |= MIPS_CPU_ISA_M32R1;
 499         case MIPS_CPU_ISA_II:
 500                 c->isa_level |= MIPS_CPU_ISA_II;
 501                 break;
 502         }
 503 }
 504
 505 static char unknown_isa[] = KERN_ERR \
 506         "Unsupported ISA type, c0.config0: %d.";
 507
 508 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
 509 {
 510
 511         unsigned int probability = c->tlbsize / c->tlbsizevtlb;
 512
 513         /*
 514          * 0 = All TLBWR instructions go to FTLB
 515          * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
 516          * FTLB and 1 goes to the VTLB.
 517          * 2 = 7:1: As above with 7:1 ratio.
 518          * 3 = 3:1: As above with 3:1 ratio.
 519          *
 520          * Use the linear midpoint as the probability threshold.
 521          */
 522         if (probability >= 12)
 523                 return 1;
 524         else if (probability >= 6)
 525                 return 2;
 526         else
 527                 /*
 528                  * So FTLB is less than 4 times bigger than VTLB.
 529                  * A 3:1 ratio can still be useful though.
 530                  */
 531                 return 3;
 532 }
 533
 534 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
 535 {
 536         unsigned int config;
 537
 538         /* It's implementation dependent how the FTLB can be enabled */
 539         switch (c->cputype) {
 540         case CPU_PROAPTIV:
 541         case CPU_P5600:
 542         case CPU_P6600:
 543                 /* proAptiv & related cores use Config6 to enable the FTLB */
 544                 config = read_c0_config6();
 545                 /* Clear the old probability value */
 546                 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
 547                 if (enable)
 548                         /* Enable FTLB */
 549                         write_c0_config6(config |
 550                                          (calculate_ftlb_probability(c)
 551                                           << MIPS_CONF6_FTLBP_SHIFT)
 552                                          | MIPS_CONF6_FTLBEN);
 553                 else
 554                         /* Disable FTLB */
 555                         write_c0_config6(config &  ~MIPS_CONF6_FTLBEN);
 556                 break;
 557         case CPU_I6400:
 558                 /* There's no way to disable the FTLB */
 559                 return !enable;
 560         case CPU_LOONGSON3:
 561                 /* Flush ITLB, DTLB, VTLB and FTLB */
 562                 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
 563                               LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
 564                 /* Loongson-3 cores use Config6 to enable the FTLB */
 565                 config = read_c0_config6();
 566                 if (enable)
 567                         /* Enable FTLB */
 568                         write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
 569                 else
 570                         /* Disable FTLB */
 571                         write_c0_config6(config | MIPS_CONF6_FTLBDIS);
 572                 break;
 573         default:
 574                 return 1;
 575         }
 576
 577         return 0;
 578 }
 579
 580 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 581 {
 582         unsigned int config0;
 583         int isa, mt;
 584
 585         config0 = read_c0_config();
 586
 587         /*
 588          * Look for Standard TLB or Dual VTLB and FTLB
 589          */
 590         mt = config0 & MIPS_CONF_MT;
 591         if (mt == MIPS_CONF_MT_TLB)
 592                 c->options |= MIPS_CPU_TLB;
 593         else if (mt == MIPS_CONF_MT_FTLB)
 594                 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
 595
 596         isa = (config0 & MIPS_CONF_AT) >> 13;
 597         switch (isa) {
 598         case 0:
 599                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 600                 case 0:
 601                         set_isa(c, MIPS_CPU_ISA_M32R1);
 602                         break;
 603                 case 1:
 604                         set_isa(c, MIPS_CPU_ISA_M32R2);
 605                         break;
 606                 case 2:
 607                         set_isa(c, MIPS_CPU_ISA_M32R6);
 608                         break;
 609                 default:
 610                         goto unknown;
 611                 }
 612                 break;
 613         case 2:
 614                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 615                 case 0:
 616                         set_isa(c, MIPS_CPU_ISA_M64R1);
 617                         break;
 618                 case 1:
 619                         set_isa(c, MIPS_CPU_ISA_M64R2);
 620                         break;
 621                 case 2:
 622                         set_isa(c, MIPS_CPU_ISA_M64R6);
 623                         break;
 624                 default:
 625                         goto unknown;
 626                 }
 627                 break;
 628         default:
 629                 goto unknown;
 630         }
 631
 632         return config0 & MIPS_CONF_M;
 633
 634 unknown:
 635         panic(unknown_isa, config0);
 636 }
 637
 638 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 639 {
 640         unsigned int config1;
 641
 642         config1 = read_c0_config1();
 643
 644         if (config1 & MIPS_CONF1_MD)
 645                 c->ases |= MIPS_ASE_MDMX;
 646         if (config1 & MIPS_CONF1_PC)
 647                 c->options |= MIPS_CPU_PERF;
 648         if (config1 & MIPS_CONF1_WR)
 649                 c->options |= MIPS_CPU_WATCH;
 650         if (config1 & MIPS_CONF1_CA)
 651                 c->ases |= MIPS_ASE_MIPS16;
 652         if (config1 & MIPS_CONF1_EP)
 653                 c->options |= MIPS_CPU_EJTAG;
 654         if (config1 & MIPS_CONF1_FP) {
 655                 c->options |= MIPS_CPU_FPU;
 656                 c->options |= MIPS_CPU_32FPR;
 657         }
 658         if (cpu_has_tlb) {
 659                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 660                 c->tlbsizevtlb = c->tlbsize;
 661                 c->tlbsizeftlbsets = 0;
 662         }
 663
 664         return config1 & MIPS_CONF_M;
 665 }
 666
 667 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 668 {
 669         unsigned int config2;
 670
 671         config2 = read_c0_config2();
 672
 673         if (config2 & MIPS_CONF2_SL)
 674                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 675
 676         return config2 & MIPS_CONF_M;
 677 }
 678
 679 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 680 {
 681         unsigned int config3;
 682
 683         config3 = read_c0_config3();
 684
 685         if (config3 & MIPS_CONF3_SM) {
 686                 c->ases |= MIPS_ASE_SMARTMIPS;
 687                 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
 688         }
 689         if (config3 & MIPS_CONF3_RXI)
 690                 c->options |= MIPS_CPU_RIXI;
 691         if (config3 & MIPS_CONF3_CTXTC)
 692                 c->options |= MIPS_CPU_CTXTC;
 693         if (config3 & MIPS_CONF3_DSP)
 694                 c->ases |= MIPS_ASE_DSP;
 695         if (config3 & MIPS_CONF3_DSP2P) {
 696                 c->ases |= MIPS_ASE_DSP2P;
 697                 if (cpu_has_mips_r6)
 698                         c->ases |= MIPS_ASE_DSP3;
 699         }
 700         if (config3 & MIPS_CONF3_VINT)
 701                 c->options |= MIPS_CPU_VINT;
 702         if (config3 & MIPS_CONF3_VEIC)
 703                 c->options |= MIPS_CPU_VEIC;
 704         if (config3 & MIPS_CONF3_LPA)
 705                 c->options |= MIPS_CPU_LPA;
 706         if (config3 & MIPS_CONF3_MT)
 707                 c->ases |= MIPS_ASE_MIPSMT;
 708         if (config3 & MIPS_CONF3_ULRI)
 709                 c->options |= MIPS_CPU_ULRI;
 710         if (config3 & MIPS_CONF3_ISA)
 711                 c->options |= MIPS_CPU_MICROMIPS;
 712         if (config3 & MIPS_CONF3_VZ)
 713                 c->ases |= MIPS_ASE_VZ;
 714         if (config3 & MIPS_CONF3_SC)
 715                 c->options |= MIPS_CPU_SEGMENTS;
 716         if (config3 & MIPS_CONF3_BI)
 717                 c->options |= MIPS_CPU_BADINSTR;
 718         if (config3 & MIPS_CONF3_BP)
 719                 c->options |= MIPS_CPU_BADINSTRP;
 720         if (config3 & MIPS_CONF3_MSA)
 721                 c->ases |= MIPS_ASE_MSA;
 722         if (config3 & MIPS_CONF3_PW) {
 723                 c->htw_seq = 0;
 724                 c->options |= MIPS_CPU_HTW;
 725         }
 726         if (config3 & MIPS_CONF3_CDMM)
 727                 c->options |= MIPS_CPU_CDMM;
 728         if (config3 & MIPS_CONF3_SP)
 729                 c->options |= MIPS_CPU_SP;
 730
 731         return config3 & MIPS_CONF_M;
 732 }
 733
 734 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 735 {
 736         unsigned int config4;
 737         unsigned int newcf4;
 738         unsigned int mmuextdef;
 739         unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
 740         unsigned long asid_mask;
 741
 742         config4 = read_c0_config4();
 743
 744         if (cpu_has_tlb) {
 745                 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
 746                         c->options |= MIPS_CPU_TLBINV;
 747
 748                 /*
 749                  * R6 has dropped the MMUExtDef field from config4.
 750                  * On R6 the fields always describe the FTLB, and only if it is
 751                  * present according to Config.MT.
 752                  */
 753                 if (!cpu_has_mips_r6)
 754                         mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 755                 else if (cpu_has_ftlb)
 756                         mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
 757                 else
 758                         mmuextdef = 0;
 759
 760                 switch (mmuextdef) {
 761                 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
 762                         c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 763                         c->tlbsizevtlb = c->tlbsize;
 764                         break;
 765                 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
 766                         c->tlbsizevtlb +=
 767                                 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
 768                                   MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
 769                         c->tlbsize = c->tlbsizevtlb;
 770                         ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
 771                         /* fall through */
 772                 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
 773                         if (mips_ftlb_disabled)
 774                                 break;
 775                         newcf4 = (config4 & ~ftlb_page) |
 776                                 (page_size_ftlb(mmuextdef) <<
 777                                  MIPS_CONF4_FTLBPAGESIZE_SHIFT);
 778                         write_c0_config4(newcf4);
 779                         back_to_back_c0_hazard();
 780                         config4 = read_c0_config4();
 781                         if (config4 != newcf4) {
 782                                 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
 783                                        PAGE_SIZE, config4);
 784                                 /* Switch FTLB off */
 785                                 set_ftlb_enable(c, 0);
 786                                 break;
 787                         }
 788                         c->tlbsizeftlbsets = 1 <<
 789                                 ((config4 & MIPS_CONF4_FTLBSETS) >>
 790                                  MIPS_CONF4_FTLBSETS_SHIFT);
 791                         c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
 792                                               MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
 793                         c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
 794                         mips_has_ftlb_configured = 1;
 795                         break;
 796                 }
 797         }
 798
 799         c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
 800                                 >> MIPS_CONF4_KSCREXIST_SHIFT;
 801
 802         asid_mask = MIPS_ENTRYHI_ASID;
 803         if (config4 & MIPS_CONF4_AE)
 804                 asid_mask |= MIPS_ENTRYHI_ASIDX;
 805         set_cpu_asid_mask(c, asid_mask);
 806
 807         /*
 808          * Warn if the computed ASID mask doesn't match the mask the kernel
 809          * is built for. This may indicate either a serious problem or an
 810          * easy optimisation opportunity, but either way should be addressed.
 811          */
 812         WARN_ON(asid_mask != cpu_asid_mask(c));
 813
 814         return config4 & MIPS_CONF_M;
 815 }
 816
 817 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
 818 {
 819         unsigned int config5;
 820
 821         config5 = read_c0_config5();
 822         config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
 823         write_c0_config5(config5);
 824
 825         if (config5 & MIPS_CONF5_EVA)
 826                 c->options |= MIPS_CPU_EVA;
 827         if (config5 & MIPS_CONF5_MRP)
 828                 c->options |= MIPS_CPU_MAAR;
 829         if (config5 & MIPS_CONF5_LLB)
 830                 c->options |= MIPS_CPU_RW_LLB;
 831         if (config5 & MIPS_CONF5_MVH)
 832                 c->options |= MIPS_CPU_MVH;
 833         if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
 834                 c->options |= MIPS_CPU_VP;
 835
 836         return config5 & MIPS_CONF_M;
 837 }
 838
 839 static void decode_configs(struct cpuinfo_mips *c)
 840 {
 841         int ok;
 842
 843         /* MIPS32 or MIPS64 compliant CPU.  */
 844         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 845                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 846
 847         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 848
 849         /* Enable FTLB if present and not disabled */
 850         set_ftlb_enable(c, !mips_ftlb_disabled);
 851
 852         ok = decode_config0(c);                 /* Read Config registers.  */
 853         BUG_ON(!ok);                            /* Arch spec violation!  */
 854         if (ok)
 855                 ok = decode_config1(c);
 856         if (ok)
 857                 ok = decode_config2(c);
 858         if (ok)
 859                 ok = decode_config3(c);
 860         if (ok)
 861                 ok = decode_config4(c);
 862         if (ok)
 863                 ok = decode_config5(c);
 864
 865         /* Probe the EBase.WG bit */
 866         if (cpu_has_mips_r2_r6) {
 867                 u64 ebase;
 868                 unsigned int status;
 869
 870                 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
 871                 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
 872                                          : (s32)read_c0_ebase();
 873                 if (ebase & MIPS_EBASE_WG) {
 874                         /* WG bit already set, we can avoid the clumsy probe */
 875                         c->options |= MIPS_CPU_EBASE_WG;
 876                 } else {
 877                         /* Its UNDEFINED to change EBase while BEV=0 */
 878                         status = read_c0_status();
 879                         write_c0_status(status | ST0_BEV);
 880                         irq_enable_hazard();
 881                         /*
 882                          * On pre-r6 cores, this may well clobber the upper bits
 883                          * of EBase. This is hard to avoid without potentially
 884                          * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
 885                          */
 886                         if (cpu_has_mips64r6)
 887                                 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
 888                         else
 889                                 write_c0_ebase(ebase | MIPS_EBASE_WG);
 890                         back_to_back_c0_hazard();
 891                         /* Restore BEV */
 892                         write_c0_status(status);
 893                         if (read_c0_ebase() & MIPS_EBASE_WG) {
 894                                 c->options |= MIPS_CPU_EBASE_WG;
 895                                 write_c0_ebase(ebase);
 896                         }
 897                 }
 898         }
 899
 900         mips_probe_watch_registers(c);
 901
 902 #ifndef CONFIG_MIPS_CPS
 903         if (cpu_has_mips_r2_r6) {
 904                 c->core = get_ebase_cpunum();
 905                 if (cpu_has_mipsmt)
 906                         c->core >>= fls(core_nvpes()) - 1;
 907         }
 908 #endif
 909 }
 910
 911 /*
 912  * Probe for certain guest capabilities by writing config bits and reading back.
 913  * Finally write back the original value.
 914  */
 915 #define probe_gc0_config(name, maxconf, bits)                           \
 916 do {                                                                    \
 917         unsigned int tmp;                                               \
 918         tmp = read_gc0_##name();                                        \
 919         write_gc0_##name(tmp | (bits));                                 \
 920         back_to_back_c0_hazard();                                       \
 921         maxconf = read_gc0_##name();                                    \
 922         write_gc0_##name(tmp);                                          \
 923 } while (0)
 924
 925 /*
 926  * Probe for dynamic guest capabilities by changing certain config bits and
 927  * reading back to see if they change. Finally write back the original value.
 928  */
 929 #define probe_gc0_config_dyn(name, maxconf, dynconf, bits)              \
 930 do {                                                                    \
 931         maxconf = read_gc0_##name();                                    \
 932         write_gc0_##name(maxconf ^ (bits));                             \
 933         back_to_back_c0_hazard();                                       \
 934         dynconf = maxconf ^ read_gc0_##name();                          \
 935         write_gc0_##name(maxconf);                                      \
 936         maxconf |= dynconf;                                             \
 937 } while (0)
 938
 939 static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
 940 {
 941         unsigned int config0;
 942
 943         probe_gc0_config(config, config0, MIPS_CONF_M);
 944
 945         if (config0 & MIPS_CONF_M)
 946                 c->guest.conf |= BIT(1);
 947         return config0 & MIPS_CONF_M;
 948 }
 949
 950 static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
 951 {
 952         unsigned int config1, config1_dyn;
 953
 954         probe_gc0_config_dyn(config1, config1, config1_dyn,
 955                              MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
 956                              MIPS_CONF1_FP);
 957
 958         if (config1 & MIPS_CONF1_FP)
 959                 c->guest.options |= MIPS_CPU_FPU;
 960         if (config1_dyn & MIPS_CONF1_FP)
 961                 c->guest.options_dyn |= MIPS_CPU_FPU;
 962
 963         if (config1 & MIPS_CONF1_WR)
 964                 c->guest.options |= MIPS_CPU_WATCH;
 965         if (config1_dyn & MIPS_CONF1_WR)
 966                 c->guest.options_dyn |= MIPS_CPU_WATCH;
 967
 968         if (config1 & MIPS_CONF1_PC)
 969                 c->guest.options |= MIPS_CPU_PERF;
 970         if (config1_dyn & MIPS_CONF1_PC)
 971                 c->guest.options_dyn |= MIPS_CPU_PERF;
 972
 973         if (config1 & MIPS_CONF_M)
 974                 c->guest.conf |= BIT(2);
 975         return config1 & MIPS_CONF_M;
 976 }
 977
 978 static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
 979 {
 980         unsigned int config2;
 981
 982         probe_gc0_config(config2, config2, MIPS_CONF_M);
 983
 984         if (config2 & MIPS_CONF_M)
 985                 c->guest.conf |= BIT(3);
 986         return config2 & MIPS_CONF_M;
 987 }
 988
 989 static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
 990 {
 991         unsigned int config3, config3_dyn;
 992
 993         probe_gc0_config_dyn(config3, config3, config3_dyn,
 994                              MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_CTXTC);
 995
 996         if (config3 & MIPS_CONF3_CTXTC)
 997                 c->guest.options |= MIPS_CPU_CTXTC;
 998         if (config3_dyn & MIPS_CONF3_CTXTC)
 999                 c->guest.options_dyn |= MIPS_CPU_CTXTC;
1000
1001         if (config3 & MIPS_CONF3_PW)
1002                 c->guest.options |= MIPS_CPU_HTW;
1003
1004         if (config3 & MIPS_CONF3_SC)
1005                 c->guest.options |= MIPS_CPU_SEGMENTS;
1006
1007         if (config3 & MIPS_CONF3_BI)
1008                 c->guest.options |= MIPS_CPU_BADINSTR;
1009         if (config3 & MIPS_CONF3_BP)
1010                 c->guest.options |= MIPS_CPU_BADINSTRP;
1011
1012         if (config3 & MIPS_CONF3_MSA)
1013                 c->guest.ases |= MIPS_ASE_MSA;
1014         if (config3_dyn & MIPS_CONF3_MSA)
1015                 c->guest.ases_dyn |= MIPS_ASE_MSA;
1016
1017         if (config3 & MIPS_CONF_M)
1018                 c->guest.conf |= BIT(4);
1019         return config3 & MIPS_CONF_M;
1020 }
1021
1022 static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
1023 {
1024         unsigned int config4;
1025
1026         probe_gc0_config(config4, config4,
1027                          MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
1028
1029         c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
1030                                 >> MIPS_CONF4_KSCREXIST_SHIFT;
1031
1032         if (config4 & MIPS_CONF_M)
1033                 c->guest.conf |= BIT(5);
1034         return config4 & MIPS_CONF_M;
1035 }
1036
1037 static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
1038 {
1039         unsigned int config5, config5_dyn;
1040
1041         probe_gc0_config_dyn(config5, config5, config5_dyn,
1042                          MIPS_CONF_M | MIPS_CONF5_MRP);
1043
1044         if (config5 & MIPS_CONF5_MRP)
1045                 c->guest.options |= MIPS_CPU_MAAR;
1046         if (config5_dyn & MIPS_CONF5_MRP)
1047                 c->guest.options_dyn |= MIPS_CPU_MAAR;
1048
1049         if (config5 & MIPS_CONF5_LLB)
1050                 c->guest.options |= MIPS_CPU_RW_LLB;
1051
1052         if (config5 & MIPS_CONF_M)
1053                 c->guest.conf |= BIT(6);
1054         return config5 & MIPS_CONF_M;
1055 }
1056
1057 static inline void decode_guest_configs(struct cpuinfo_mips *c)
1058 {
1059         unsigned int ok;
1060
1061         ok = decode_guest_config0(c);
1062         if (ok)
1063                 ok = decode_guest_config1(c);
1064         if (ok)
1065                 ok = decode_guest_config2(c);
1066         if (ok)
1067                 ok = decode_guest_config3(c);
1068         if (ok)
1069                 ok = decode_guest_config4(c);
1070         if (ok)
1071                 decode_guest_config5(c);
1072 }
1073
1074 static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
1075 {
1076         unsigned int guestctl0, temp;
1077
1078         guestctl0 = read_c0_guestctl0();
1079
1080         if (guestctl0 & MIPS_GCTL0_G0E)
1081                 c->options |= MIPS_CPU_GUESTCTL0EXT;
1082         if (guestctl0 & MIPS_GCTL0_G1)
1083                 c->options |= MIPS_CPU_GUESTCTL1;
1084         if (guestctl0 & MIPS_GCTL0_G2)
1085                 c->options |= MIPS_CPU_GUESTCTL2;
1086         if (!(guestctl0 & MIPS_GCTL0_RAD)) {
1087                 c->options |= MIPS_CPU_GUESTID;
1088
1089                 /*
1090                  * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
1091                  * first, otherwise all data accesses will be fully virtualised
1092                  * as if they were performed by guest mode.
1093                  */
1094                 write_c0_guestctl1(0);
1095                 tlbw_use_hazard();
1096
1097                 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
1098                 back_to_back_c0_hazard();
1099                 temp = read_c0_guestctl0();
1100
1101                 if (temp & MIPS_GCTL0_DRG) {
1102                         write_c0_guestctl0(guestctl0);
1103                         c->options |= MIPS_CPU_DRG;
1104                 }
1105         }
1106 }
1107
1108 static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1109 {
1110         if (cpu_has_guestid) {
1111                 /* determine the number of bits of GuestID available */
1112                 write_c0_guestctl1(MIPS_GCTL1_ID);
1113                 back_to_back_c0_hazard();
1114                 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1115                                                 >> MIPS_GCTL1_ID_SHIFT;
1116                 write_c0_guestctl1(0);
1117         }
1118 }
1119
1120 static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1121 {
1122         /* determine the number of bits of GTOffset available */
1123         write_c0_gtoffset(0xffffffff);
1124         back_to_back_c0_hazard();
1125         c->gtoffset_mask = read_c0_gtoffset();
1126         write_c0_gtoffset(0);
1127 }
1128
1129 static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1130 {
1131         cpu_probe_guestctl0(c);
1132         if (cpu_has_guestctl1)
1133                 cpu_probe_guestctl1(c);
1134
1135         cpu_probe_gtoffset(c);
1136
1137         decode_guest_configs(c);
1138 }
1139
1140 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1141                 | MIPS_CPU_COUNTER)
1142
1143 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1144 {
1145         switch (c->processor_id & PRID_IMP_MASK) {
1146         case PRID_IMP_R2000:
1147                 c->cputype = CPU_R2000;
1148                 __cpu_name[cpu] = "R2000";
1149                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1150                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1151                              MIPS_CPU_NOFPUEX;
1152                 if (__cpu_has_fpu())
1153                         c->options |= MIPS_CPU_FPU;
1154                 c->tlbsize = 64;
1155                 break;
1156         case PRID_IMP_R3000:
1157                 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
1158                         if (cpu_has_confreg()) {
1159                                 c->cputype = CPU_R3081E;
1160                                 __cpu_name[cpu] = "R3081";
1161                         } else {
1162                                 c->cputype = CPU_R3000A;
1163                                 __cpu_name[cpu] = "R3000A";
1164                         }
1165                 } else {
1166                         c->cputype = CPU_R3000;
1167                         __cpu_name[cpu] = "R3000";
1168                 }
1169                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1170                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1171                              MIPS_CPU_NOFPUEX;
1172                 if (__cpu_has_fpu())
1173                         c->options |= MIPS_CPU_FPU;
1174                 c->tlbsize = 64;
1175                 break;
1176         case PRID_IMP_R4000:
1177                 if (read_c0_config() & CONF_SC) {
1178                         if ((c->processor_id & PRID_REV_MASK) >=
1179                             PRID_REV_R4400) {
1180                                 c->cputype = CPU_R4400PC;
1181                                 __cpu_name[cpu] = "R4400PC";
1182                         } else {
1183                                 c->cputype = CPU_R4000PC;
1184                                 __cpu_name[cpu] = "R4000PC";
1185                         }
1186                 } else {
1187                         int cca = read_c0_config() & CONF_CM_CMASK;
1188                         int mc;
1189
1190                         /*
1191                          * SC and MC versions can't be reliably told apart,
1192                          * but only the latter support coherent caching
1193                          * modes so assume the firmware has set the KSEG0
1194                          * coherency attribute reasonably (if uncached, we
1195                          * assume SC).
1196                          */
1197                         switch (cca) {
1198                         case CONF_CM_CACHABLE_CE:
1199                         case CONF_CM_CACHABLE_COW:
1200                         case CONF_CM_CACHABLE_CUW:
1201                                 mc = 1;
1202                                 break;
1203                         default:
1204                                 mc = 0;
1205                                 break;
1206                         }
1207                         if ((c->processor_id & PRID_REV_MASK) >=
1208                             PRID_REV_R4400) {
1209                                 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1210                                 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
1211                         } else {
1212                                 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1213                                 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
1214                         }
1215                 }
1216
1217                 set_isa(c, MIPS_CPU_ISA_III);
1218                 c->fpu_msk31 |= FPU_CSR_CONDX;
1219                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1220                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
1221                              MIPS_CPU_LLSC;
1222                 c->tlbsize = 48;
1223                 break;
1224         case PRID_IMP_VR41XX:
1225                 set_isa(c, MIPS_CPU_ISA_III);
1226                 c->fpu_msk31 |= FPU_CSR_CONDX;
1227                 c->options = R4K_OPTS;
1228                 c->tlbsize = 32;
1229                 switch (c->processor_id & 0xf0) {
1230                 case PRID_REV_VR4111:
1231                         c->cputype = CPU_VR4111;
1232                         __cpu_name[cpu] = "NEC VR4111";
1233                         break;
1234                 case PRID_REV_VR4121:
1235                         c->cputype = CPU_VR4121;
1236                         __cpu_name[cpu] = "NEC VR4121";
1237                         break;
1238                 case PRID_REV_VR4122:
1239                         if ((c->processor_id & 0xf) < 0x3) {
1240                                 c->cputype = CPU_VR4122;
1241                                 __cpu_name[cpu] = "NEC VR4122";
1242                         } else {
1243                                 c->cputype = CPU_VR4181A;
1244                                 __cpu_name[cpu] = "NEC VR4181A";
1245                         }
1246                         break;
1247                 case PRID_REV_VR4130:
1248                         if ((c->processor_id & 0xf) < 0x4) {
1249                                 c->cputype = CPU_VR4131;
1250                                 __cpu_name[cpu] = "NEC VR4131";
1251                         } else {
1252                                 c->cputype = CPU_VR4133;
1253                                 c->options |= MIPS_CPU_LLSC;
1254                                 __cpu_name[cpu] = "NEC VR4133";
1255                         }
1256                         break;
1257                 default:
1258                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1259                         c->cputype = CPU_VR41XX;
1260                         __cpu_name[cpu] = "NEC Vr41xx";
1261                         break;
1262                 }
1263                 break;
1264         case PRID_IMP_R4300:
1265                 c->cputype = CPU_R4300;
1266                 __cpu_name[cpu] = "R4300";
1267                 set_isa(c, MIPS_CPU_ISA_III);
1268                 c->fpu_msk31 |= FPU_CSR_CONDX;
1269                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1270                              MIPS_CPU_LLSC;
1271                 c->tlbsize = 32;
1272                 break;
1273         case PRID_IMP_R4600:
1274                 c->cputype = CPU_R4600;
1275                 __cpu_name[cpu] = "R4600";
1276                 set_isa(c, MIPS_CPU_ISA_III);
1277                 c->fpu_msk31 |= FPU_CSR_CONDX;
1278                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1279                              MIPS_CPU_LLSC;
1280                 c->tlbsize = 48;
1281                 break;
1282         #if 0
1283         case PRID_IMP_R4650:
1284                 /*
1285                  * This processor doesn't have an MMU, so it's not
1286                  * "real easy" to run Linux on it. It is left purely
1287                  * for documentation.  Commented out because it shares
1288                  * it's c0_prid id number with the TX3900.
1289                  */
1290                 c->cputype = CPU_R4650;
1291                 __cpu_name[cpu] = "R4650";
1292                 set_isa(c, MIPS_CPU_ISA_III);
1293                 c->fpu_msk31 |= FPU_CSR_CONDX;
1294                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1295                 c->tlbsize = 48;
1296                 break;
1297         #endif
1298         case PRID_IMP_TX39:
1299                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1300                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1301
1302                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1303                         c->cputype = CPU_TX3927;
1304                         __cpu_name[cpu] = "TX3927";
1305                         c->tlbsize = 64;
1306                 } else {
1307                         switch (c->processor_id & PRID_REV_MASK) {
1308                         case PRID_REV_TX3912:
1309                                 c->cputype = CPU_TX3912;
1310                                 __cpu_name[cpu] = "TX3912";
1311                                 c->tlbsize = 32;
1312                                 break;
1313                         case PRID_REV_TX3922:
1314                                 c->cputype = CPU_TX3922;
1315                                 __cpu_name[cpu] = "TX3922";
1316                                 c->tlbsize = 64;
1317                                 break;
1318                         }
1319                 }
1320                 break;
1321         case PRID_IMP_R4700:
1322                 c->cputype = CPU_R4700;
1323                 __cpu_name[cpu] = "R4700";
1324                 set_isa(c, MIPS_CPU_ISA_III);
1325                 c->fpu_msk31 |= FPU_CSR_CONDX;
1326                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1327                              MIPS_CPU_LLSC;
1328                 c->tlbsize = 48;
1329                 break;
1330         case PRID_IMP_TX49:
1331                 c->cputype = CPU_TX49XX;
1332                 __cpu_name[cpu] = "R49XX";
1333                 set_isa(c, MIPS_CPU_ISA_III);
1334                 c->fpu_msk31 |= FPU_CSR_CONDX;
1335                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1336                 if (!(c->processor_id & 0x08))
1337                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1338                 c->tlbsize = 48;
1339                 break;
1340         case PRID_IMP_R5000:
1341                 c->cputype = CPU_R5000;
1342                 __cpu_name[cpu] = "R5000";
1343                 set_isa(c, MIPS_CPU_ISA_IV);
1344                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1345                              MIPS_CPU_LLSC;
1346                 c->tlbsize = 48;
1347                 break;
1348         case PRID_IMP_R5432:
1349                 c->cputype = CPU_R5432;
1350                 __cpu_name[cpu] = "R5432";
1351                 set_isa(c, MIPS_CPU_ISA_IV);
1352                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1353                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1354                 c->tlbsize = 48;
1355                 break;
1356         case PRID_IMP_R5500:
1357                 c->cputype = CPU_R5500;
1358                 __cpu_name[cpu] = "R5500";
1359                 set_isa(c, MIPS_CPU_ISA_IV);
1360                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1361                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1362                 c->tlbsize = 48;
1363                 break;
1364         case PRID_IMP_NEVADA:
1365                 c->cputype = CPU_NEVADA;
1366                 __cpu_name[cpu] = "Nevada";
1367                 set_isa(c, MIPS_CPU_ISA_IV);
1368                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1369                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1370                 c->tlbsize = 48;
1371                 break;
1372         case PRID_IMP_R6000:
1373                 c->cputype = CPU_R6000;
1374                 __cpu_name[cpu] = "R6000";
1375                 set_isa(c, MIPS_CPU_ISA_II);
1376                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1377                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
1378                              MIPS_CPU_LLSC;
1379                 c->tlbsize = 32;
1380                 break;
1381         case PRID_IMP_R6000A:
1382                 c->cputype = CPU_R6000A;
1383                 __cpu_name[cpu] = "R6000A";
1384                 set_isa(c, MIPS_CPU_ISA_II);
1385                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1386                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
1387                              MIPS_CPU_LLSC;
1388                 c->tlbsize = 32;
1389                 break;
1390         case PRID_IMP_RM7000:
1391                 c->cputype = CPU_RM7000;
1392                 __cpu_name[cpu] = "RM7000";
1393                 set_isa(c, MIPS_CPU_ISA_IV);
1394                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1395                              MIPS_CPU_LLSC;
1396                 /*
1397                  * Undocumented RM7000:  Bit 29 in the info register of
1398                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
1399                  * entries.
1400                  *
1401                  * 29      1 =>    64 entry JTLB
1402                  *         0 =>    48 entry JTLB
1403                  */
1404                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1405                 break;
1406         case PRID_IMP_R8000:
1407                 c->cputype = CPU_R8000;
1408                 __cpu_name[cpu] = "RM8000";
1409                 set_isa(c, MIPS_CPU_ISA_IV);
1410                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
1411                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
1412                              MIPS_CPU_LLSC;
1413                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
1414                 break;
1415         case PRID_IMP_R10000:
1416                 c->cputype = CPU_R10000;
1417                 __cpu_name[cpu] = "R10000";
1418                 set_isa(c, MIPS_CPU_ISA_IV);
1419                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1420                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
1421                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1422                              MIPS_CPU_LLSC;
1423                 c->tlbsize = 64;
1424                 break;
1425         case PRID_IMP_R12000:
1426                 c->cputype = CPU_R12000;
1427                 __cpu_name[cpu] = "R12000";
1428                 set_isa(c, MIPS_CPU_ISA_IV);
1429                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1430                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
1431                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1432                              MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1433                 c->tlbsize = 64;
1434                 break;
1435         case PRID_IMP_R14000:
1436                 if (((c->processor_id >> 4) & 0x0f) > 2) {
1437                         c->cputype = CPU_R16000;
1438                         __cpu_name[cpu] = "R16000";
1439                 } else {
1440                         c->cputype = CPU_R14000;
1441                         __cpu_name[cpu] = "R14000";
1442                 }
1443                 set_isa(c, MIPS_CPU_ISA_IV);
1444                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1445                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
1446                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1447                              MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1448                 c->tlbsize = 64;
1449                 break;
1450         case PRID_IMP_LOONGSON_64:  /* Loongson-2/3 */
1451                 switch (c->processor_id & PRID_REV_MASK) {
1452                 case PRID_REV_LOONGSON2E:
1453                         c->cputype = CPU_LOONGSON2;
1454                         __cpu_name[cpu] = "ICT Loongson-2";
1455                         set_elf_platform(cpu, "loongson2e");
1456                         set_isa(c, MIPS_CPU_ISA_III);
1457                         c->fpu_msk31 |= FPU_CSR_CONDX;
1458                         break;
1459                 case PRID_REV_LOONGSON2F:
1460                         c->cputype = CPU_LOONGSON2;
1461                         __cpu_name[cpu] = "ICT Loongson-2";
1462                         set_elf_platform(cpu, "loongson2f");
1463                         set_isa(c, MIPS_CPU_ISA_III);
1464                         c->fpu_msk31 |= FPU_CSR_CONDX;
1465                         break;
1466                 case PRID_REV_LOONGSON3A_R1:
1467                         c->cputype = CPU_LOONGSON3;
1468                         __cpu_name[cpu] = "ICT Loongson-3";
1469                         set_elf_platform(cpu, "loongson3a");
1470                         set_isa(c, MIPS_CPU_ISA_M64R1);
1471                         break;
1472                 case PRID_REV_LOONGSON3B_R1:
1473                 case PRID_REV_LOONGSON3B_R2:
1474                         c->cputype = CPU_LOONGSON3;
1475                         __cpu_name[cpu] = "ICT Loongson-3";
1476                         set_elf_platform(cpu, "loongson3b");
1477                         set_isa(c, MIPS_CPU_ISA_M64R1);
1478                         break;
1479                 }
1480
1481                 c->options = R4K_OPTS |
1482                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
1483                              MIPS_CPU_32FPR;
1484                 c->tlbsize = 64;
1485                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1486                 break;
1487         case PRID_IMP_LOONGSON_32:  /* Loongson-1 */
1488                 decode_configs(c);
1489
1490                 c->cputype = CPU_LOONGSON1;
1491
1492                 switch (c->processor_id & PRID_REV_MASK) {
1493                 case PRID_REV_LOONGSON1B:
1494                         __cpu_name[cpu] = "Loongson 1B";
1495                         break;
1496                 }
1497
1498                 break;
1499         }
1500 }
1501
1502 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1503 {
1504         c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1505         switch (c->processor_id & PRID_IMP_MASK) {
1506         case PRID_IMP_QEMU_GENERIC:
1507                 c->writecombine = _CACHE_UNCACHED;
1508                 c->cputype = CPU_QEMU_GENERIC;
1509                 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1510                 break;
1511         case PRID_IMP_4KC:
1512                 c->cputype = CPU_4KC;
1513                 c->writecombine = _CACHE_UNCACHED;
1514                 __cpu_name[cpu] = "MIPS 4Kc";
1515                 break;
1516         case PRID_IMP_4KEC:
1517         case PRID_IMP_4KECR2:
1518                 c->cputype = CPU_4KEC;
1519                 c->writecombine = _CACHE_UNCACHED;
1520                 __cpu_name[cpu] = "MIPS 4KEc";
1521                 break;
1522         case PRID_IMP_4KSC:
1523         case PRID_IMP_4KSD:
1524                 c->cputype = CPU_4KSC;
1525                 c->writecombine = _CACHE_UNCACHED;
1526                 __cpu_name[cpu] = "MIPS 4KSc";
1527                 break;
1528         case PRID_IMP_5KC:
1529                 c->cputype = CPU_5KC;
1530                 c->writecombine = _CACHE_UNCACHED;
1531                 __cpu_name[cpu] = "MIPS 5Kc";
1532                 break;
1533         case PRID_IMP_5KE:
1534                 c->cputype = CPU_5KE;
1535                 c->writecombine = _CACHE_UNCACHED;
1536                 __cpu_name[cpu] = "MIPS 5KE";
1537                 break;
1538         case PRID_IMP_20KC:
1539                 c->cputype = CPU_20KC;
1540                 c->writecombine = _CACHE_UNCACHED;
1541                 __cpu_name[cpu] = "MIPS 20Kc";
1542                 break;
1543         case PRID_IMP_24K:
1544                 c->cputype = CPU_24K;
1545                 c->writecombine = _CACHE_UNCACHED;
1546                 __cpu_name[cpu] = "MIPS 24Kc";
1547                 break;
1548         case PRID_IMP_24KE:
1549                 c->cputype = CPU_24K;
1550                 c->writecombine = _CACHE_UNCACHED;
1551                 __cpu_name[cpu] = "MIPS 24KEc";
1552                 break;
1553         case PRID_IMP_25KF:
1554                 c->cputype = CPU_25KF;
1555                 c->writecombine = _CACHE_UNCACHED;
1556                 __cpu_name[cpu] = "MIPS 25Kc";
1557                 break;
1558         case PRID_IMP_34K:
1559                 c->cputype = CPU_34K;
1560                 c->writecombine = _CACHE_UNCACHED;
1561                 __cpu_name[cpu] = "MIPS 34Kc";
1562                 break;
1563         case PRID_IMP_74K:
1564                 c->cputype = CPU_74K;
1565                 c->writecombine = _CACHE_UNCACHED;
1566                 __cpu_name[cpu] = "MIPS 74Kc";
1567                 break;
1568         case PRID_IMP_M14KC:
1569                 c->cputype = CPU_M14KC;
1570                 c->writecombine = _CACHE_UNCACHED;
1571                 __cpu_name[cpu] = "MIPS M14Kc";
1572                 break;
1573         case PRID_IMP_M14KEC:
1574                 c->cputype = CPU_M14KEC;
1575                 c->writecombine = _CACHE_UNCACHED;
1576                 __cpu_name[cpu] = "MIPS M14KEc";
1577                 break;
1578         case PRID_IMP_1004K:
1579                 c->cputype = CPU_1004K;
1580                 c->writecombine = _CACHE_UNCACHED;
1581                 __cpu_name[cpu] = "MIPS 1004Kc";
1582                 break;
1583         case PRID_IMP_1074K:
1584                 c->cputype = CPU_1074K;
1585                 c->writecombine = _CACHE_UNCACHED;
1586                 __cpu_name[cpu] = "MIPS 1074Kc";
1587                 break;
1588         case PRID_IMP_INTERAPTIV_UP:
1589                 c->cputype = CPU_INTERAPTIV;
1590                 __cpu_name[cpu] = "MIPS interAptiv";
1591                 break;
1592         case PRID_IMP_INTERAPTIV_MP:
1593                 c->cputype = CPU_INTERAPTIV;
1594                 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1595                 break;
1596         case PRID_IMP_PROAPTIV_UP:
1597                 c->cputype = CPU_PROAPTIV;
1598                 __cpu_name[cpu] = "MIPS proAptiv";
1599                 break;
1600         case PRID_IMP_PROAPTIV_MP:
1601                 c->cputype = CPU_PROAPTIV;
1602                 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1603                 break;
1604         case PRID_IMP_P5600:
1605                 c->cputype = CPU_P5600;
1606                 __cpu_name[cpu] = "MIPS P5600";
1607                 break;
1608         case PRID_IMP_P6600:
1609                 c->cputype = CPU_P6600;
1610                 __cpu_name[cpu] = "MIPS P6600";
1611                 break;
1612         case PRID_IMP_I6400:
1613                 c->cputype = CPU_I6400;
1614                 __cpu_name[cpu] = "MIPS I6400";
1615                 break;
1616         case PRID_IMP_M5150:
1617                 c->cputype = CPU_M5150;
1618                 __cpu_name[cpu] = "MIPS M5150";
1619                 break;
1620         case PRID_IMP_M6250:
1621                 c->cputype = CPU_M6250;
1622                 __cpu_name[cpu] = "MIPS M6250";
1623                 break;
1624         }
1625
1626         decode_configs(c);
1627
1628         spram_config();
1629 }
1630
1631 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1632 {
1633         decode_configs(c);
1634         switch (c->processor_id & PRID_IMP_MASK) {
1635         case PRID_IMP_AU1_REV1:
1636         case PRID_IMP_AU1_REV2:
1637                 c->cputype = CPU_ALCHEMY;
1638                 switch ((c->processor_id >> 24) & 0xff) {
1639                 case 0:
1640                         __cpu_name[cpu] = "Au1000";
1641                         break;
1642                 case 1:
1643                         __cpu_name[cpu] = "Au1500";
1644                         break;
1645                 case 2:
1646                         __cpu_name[cpu] = "Au1100";
1647                         break;
1648                 case 3:
1649                         __cpu_name[cpu] = "Au1550";
1650                         break;
1651                 case 4:
1652                         __cpu_name[cpu] = "Au1200";
1653                         if ((c->processor_id & PRID_REV_MASK) == 2)
1654                                 __cpu_name[cpu] = "Au1250";
1655                         break;
1656                 case 5:
1657                         __cpu_name[cpu] = "Au1210";
1658                         break;
1659                 default:
1660                         __cpu_name[cpu] = "Au1xxx";
1661                         break;
1662                 }
1663                 break;
1664         }
1665 }
1666
1667 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1668 {
1669         decode_configs(c);
1670
1671         c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1672         switch (c->processor_id & PRID_IMP_MASK) {
1673         case PRID_IMP_SB1:
1674                 c->cputype = CPU_SB1;
1675                 __cpu_name[cpu] = "SiByte SB1";
1676                 /* FPU in pass1 is known to have issues. */
1677                 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1678                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1679                 break;
1680         case PRID_IMP_SB1A:
1681                 c->cputype = CPU_SB1A;
1682                 __cpu_name[cpu] = "SiByte SB1A";
1683                 break;
1684         }
1685 }
1686
1687 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1688 {
1689         decode_configs(c);
1690         switch (c->processor_id & PRID_IMP_MASK) {
1691         case PRID_IMP_SR71000:
1692                 c->cputype = CPU_SR71000;
1693                 __cpu_name[cpu] = "Sandcraft SR71000";
1694                 c->scache.ways = 8;
1695                 c->tlbsize = 64;
1696                 break;
1697         }
1698 }
1699
1700 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1701 {
1702         decode_configs(c);
1703         switch (c->processor_id & PRID_IMP_MASK) {
1704         case PRID_IMP_PR4450:
1705                 c->cputype = CPU_PR4450;
1706                 __cpu_name[cpu] = "Philips PR4450";
1707                 set_isa(c, MIPS_CPU_ISA_M32R1);
1708                 break;
1709         }
1710 }
1711
1712 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1713 {
1714         decode_configs(c);
1715         switch (c->processor_id & PRID_IMP_MASK) {
1716         case PRID_IMP_BMIPS32_REV4:
1717         case PRID_IMP_BMIPS32_REV8:
1718                 c->cputype = CPU_BMIPS32;
1719                 __cpu_name[cpu] = "Broadcom BMIPS32";
1720                 set_elf_platform(cpu, "bmips32");
1721                 break;
1722         case PRID_IMP_BMIPS3300:
1723         case PRID_IMP_BMIPS3300_ALT:
1724         case PRID_IMP_BMIPS3300_BUG:
1725                 c->cputype = CPU_BMIPS3300;
1726                 __cpu_name[cpu] = "Broadcom BMIPS3300";
1727                 set_elf_platform(cpu, "bmips3300");
1728                 break;
1729         case PRID_IMP_BMIPS43XX: {
1730                 int rev = c->processor_id & PRID_REV_MASK;
1731
1732                 if (rev >= PRID_REV_BMIPS4380_LO &&
1733                                 rev <= PRID_REV_BMIPS4380_HI) {
1734                         c->cputype = CPU_BMIPS4380;
1735                         __cpu_name[cpu] = "Broadcom BMIPS4380";
1736                         set_elf_platform(cpu, "bmips4380");
1737                         c->options |= MIPS_CPU_RIXI;
1738                 } else {
1739                         c->cputype = CPU_BMIPS4350;
1740                         __cpu_name[cpu] = "Broadcom BMIPS4350";
1741                         set_elf_platform(cpu, "bmips4350");
1742                 }
1743                 break;
1744         }
1745         case PRID_IMP_BMIPS5000:
1746         case PRID_IMP_BMIPS5200:
1747                 c->cputype = CPU_BMIPS5000;
1748                 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1749                         __cpu_name[cpu] = "Broadcom BMIPS5200";
1750                 else
1751                         __cpu_name[cpu] = "Broadcom BMIPS5000";
1752                 set_elf_platform(cpu, "bmips5000");
1753                 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
1754                 break;
1755         }
1756 }
1757
1758 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1759 {
1760         decode_configs(c);
1761         switch (c->processor_id & PRID_IMP_MASK) {
1762         case PRID_IMP_CAVIUM_CN38XX:
1763         case PRID_IMP_CAVIUM_CN31XX:
1764         case PRID_IMP_CAVIUM_CN30XX:
1765                 c->cputype = CPU_CAVIUM_OCTEON;
1766                 __cpu_name[cpu] = "Cavium Octeon";
1767                 goto platform;
1768         case PRID_IMP_CAVIUM_CN58XX:
1769         case PRID_IMP_CAVIUM_CN56XX:
1770         case PRID_IMP_CAVIUM_CN50XX:
1771         case PRID_IMP_CAVIUM_CN52XX:
1772                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1773                 __cpu_name[cpu] = "Cavium Octeon+";
1774 platform:
1775                 set_elf_platform(cpu, "octeon");
1776                 break;
1777         case PRID_IMP_CAVIUM_CN61XX:
1778         case PRID_IMP_CAVIUM_CN63XX:
1779         case PRID_IMP_CAVIUM_CN66XX:
1780         case PRID_IMP_CAVIUM_CN68XX:
1781         case PRID_IMP_CAVIUM_CNF71XX:
1782                 c->cputype = CPU_CAVIUM_OCTEON2;
1783                 __cpu_name[cpu] = "Cavium Octeon II";
1784                 set_elf_platform(cpu, "octeon2");
1785                 break;
1786         case PRID_IMP_CAVIUM_CN70XX:
1787         case PRID_IMP_CAVIUM_CN73XX:
1788         case PRID_IMP_CAVIUM_CNF75XX:
1789         case PRID_IMP_CAVIUM_CN78XX:
1790                 c->cputype = CPU_CAVIUM_OCTEON3;
1791                 __cpu_name[cpu] = "Cavium Octeon III";
1792                 set_elf_platform(cpu, "octeon3");
1793                 break;
1794         default:
1795                 printk(KERN_INFO "Unknown Octeon chip!\n");
1796                 c->cputype = CPU_UNKNOWN;
1797                 break;
1798         }
1799 }
1800
1801 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1802 {
1803         switch (c->processor_id & PRID_IMP_MASK) {
1804         case PRID_IMP_LOONGSON_64:  /* Loongson-2/3 */
1805                 switch (c->processor_id & PRID_REV_MASK) {
1806                 case PRID_REV_LOONGSON3A_R2:
1807                         c->cputype = CPU_LOONGSON3;
1808                         __cpu_name[cpu] = "ICT Loongson-3";
1809                         set_elf_platform(cpu, "loongson3a");
1810                         set_isa(c, MIPS_CPU_ISA_M64R2);
1811                         break;
1812                 }
1813
1814                 decode_configs(c);
1815                 c->options |= MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
1816                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1817                 break;
1818         default:
1819                 panic("Unknown Loongson Processor ID!");
1820                 break;
1821         }
1822 }
1823
1824 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1825 {
1826         decode_configs(c);
1827         /* JZRISC does not implement the CP0 counter. */
1828         c->options &= ~MIPS_CPU_COUNTER;
1829         BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1830         switch (c->processor_id & PRID_IMP_MASK) {
1831         case PRID_IMP_JZRISC:
1832                 c->cputype = CPU_JZRISC;
1833                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1834                 __cpu_name[cpu] = "Ingenic JZRISC";
1835                 break;
1836         default:
1837                 panic("Unknown Ingenic Processor ID!");
1838                 break;
1839         }
1840 }
1841
1842 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1843 {
1844         decode_configs(c);
1845
1846         if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1847                 c->cputype = CPU_ALCHEMY;
1848                 __cpu_name[cpu] = "Au1300";
1849                 /* following stuff is not for Alchemy */
1850                 return;
1851         }
1852
1853         c->options = (MIPS_CPU_TLB       |
1854                         MIPS_CPU_4KEX    |
1855                         MIPS_CPU_COUNTER |
1856                         MIPS_CPU_DIVEC   |
1857                         MIPS_CPU_WATCH   |
1858                         MIPS_CPU_EJTAG   |
1859                         MIPS_CPU_LLSC);
1860
1861         switch (c->processor_id & PRID_IMP_MASK) {
1862         case PRID_IMP_NETLOGIC_XLP2XX:
1863         case PRID_IMP_NETLOGIC_XLP9XX:
1864         case PRID_IMP_NETLOGIC_XLP5XX:
1865                 c->cputype = CPU_XLP;
1866                 __cpu_name[cpu] = "Broadcom XLPII";
1867                 break;
1868
1869         case PRID_IMP_NETLOGIC_XLP8XX:
1870         case PRID_IMP_NETLOGIC_XLP3XX:
1871                 c->cputype = CPU_XLP;
1872                 __cpu_name[cpu] = "Netlogic XLP";
1873                 break;
1874
1875         case PRID_IMP_NETLOGIC_XLR732:
1876         case PRID_IMP_NETLOGIC_XLR716:
1877         case PRID_IMP_NETLOGIC_XLR532:
1878         case PRID_IMP_NETLOGIC_XLR308:
1879         case PRID_IMP_NETLOGIC_XLR532C:
1880         case PRID_IMP_NETLOGIC_XLR516C:
1881         case PRID_IMP_NETLOGIC_XLR508C:
1882         case PRID_IMP_NETLOGIC_XLR308C:
1883                 c->cputype = CPU_XLR;
1884                 __cpu_name[cpu] = "Netlogic XLR";
1885                 break;
1886
1887         case PRID_IMP_NETLOGIC_XLS608:
1888         case PRID_IMP_NETLOGIC_XLS408:
1889         case PRID_IMP_NETLOGIC_XLS404:
1890         case PRID_IMP_NETLOGIC_XLS208:
1891         case PRID_IMP_NETLOGIC_XLS204:
1892         case PRID_IMP_NETLOGIC_XLS108:
1893         case PRID_IMP_NETLOGIC_XLS104:
1894         case PRID_IMP_NETLOGIC_XLS616B:
1895         case PRID_IMP_NETLOGIC_XLS608B:
1896         case PRID_IMP_NETLOGIC_XLS416B:
1897         case PRID_IMP_NETLOGIC_XLS412B:
1898         case PRID_IMP_NETLOGIC_XLS408B:
1899         case PRID_IMP_NETLOGIC_XLS404B:
1900                 c->cputype = CPU_XLR;
1901                 __cpu_name[cpu] = "Netlogic XLS";
1902                 break;
1903
1904         default:
1905                 pr_info("Unknown Netlogic chip id [%02x]!\n",
1906                        c->processor_id);
1907                 c->cputype = CPU_XLR;
1908                 break;
1909         }
1910
1911         if (c->cputype == CPU_XLP) {
1912                 set_isa(c, MIPS_CPU_ISA_M64R2);
1913                 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1914                 /* This will be updated again after all threads are woken up */
1915                 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1916         } else {
1917                 set_isa(c, MIPS_CPU_ISA_M64R1);
1918                 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1919         }
1920         c->kscratch_mask = 0xf;
1921 }
1922
1923 #ifdef CONFIG_64BIT
1924 /* For use by uaccess.h */
1925 u64 __ua_limit;
1926 EXPORT_SYMBOL(__ua_limit);
1927 #endif
1928
1929 const char *__cpu_name[NR_CPUS];
1930 const char *__elf_platform;
1931
1932 void cpu_probe(void)
1933 {
1934         struct cpuinfo_mips *c = &current_cpu_data;
1935         unsigned int cpu = smp_processor_id();
1936
1937         c->processor_id = PRID_IMP_UNKNOWN;
1938         c->fpu_id       = FPIR_IMP_NONE;
1939         c->cputype      = CPU_UNKNOWN;
1940         c->writecombine = _CACHE_UNCACHED;
1941
1942         c->fpu_csr31    = FPU_CSR_RN;
1943         c->fpu_msk31    = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1944
1945         c->processor_id = read_c0_prid();
1946         switch (c->processor_id & PRID_COMP_MASK) {
1947         case PRID_COMP_LEGACY:
1948                 cpu_probe_legacy(c, cpu);
1949                 break;
1950         case PRID_COMP_MIPS:
1951                 cpu_probe_mips(c, cpu);
1952                 break;
1953         case PRID_COMP_ALCHEMY:
1954                 cpu_probe_alchemy(c, cpu);
1955                 break;
1956         case PRID_COMP_SIBYTE:
1957                 cpu_probe_sibyte(c, cpu);
1958                 break;
1959         case PRID_COMP_BROADCOM:
1960                 cpu_probe_broadcom(c, cpu);
1961                 break;
1962         case PRID_COMP_SANDCRAFT:
1963                 cpu_probe_sandcraft(c, cpu);
1964                 break;
1965         case PRID_COMP_NXP:
1966                 cpu_probe_nxp(c, cpu);
1967                 break;
1968         case PRID_COMP_CAVIUM:
1969                 cpu_probe_cavium(c, cpu);
1970                 break;
1971         case PRID_COMP_LOONGSON:
1972                 cpu_probe_loongson(c, cpu);
1973                 break;
1974         case PRID_COMP_INGENIC_D0:
1975         case PRID_COMP_INGENIC_D1:
1976         case PRID_COMP_INGENIC_E1:
1977                 cpu_probe_ingenic(c, cpu);
1978                 break;
1979         case PRID_COMP_NETLOGIC:
1980                 cpu_probe_netlogic(c, cpu);
1981                 break;
1982         }
1983
1984         BUG_ON(!__cpu_name[cpu]);
1985         BUG_ON(c->cputype == CPU_UNKNOWN);
1986
1987         /*
1988          * Platform code can force the cpu type to optimize code
1989          * generation. In that case be sure the cpu type is correctly
1990          * manually setup otherwise it could trigger some nasty bugs.
1991          */
1992         BUG_ON(current_cpu_type() != c->cputype);
1993
1994         if (cpu_has_rixi) {
1995                 /* Enable the RIXI exceptions */
1996                 set_c0_pagegrain(PG_IEC);
1997                 back_to_back_c0_hazard();
1998                 /* Verify the IEC bit is set */
1999                 if (read_c0_pagegrain() & PG_IEC)
2000                         c->options |= MIPS_CPU_RIXIEX;
2001         }
2002
2003         if (mips_fpu_disabled)
2004                 c->options &= ~MIPS_CPU_FPU;
2005
2006         if (mips_dsp_disabled)
2007                 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
2008
2009         if (mips_htw_disabled) {
2010                 c->options &= ~MIPS_CPU_HTW;
2011                 write_c0_pwctl(read_c0_pwctl() &
2012                                ~(1 << MIPS_PWCTL_PWEN_SHIFT));
2013         }
2014
2015         if (c->options & MIPS_CPU_FPU)
2016                 cpu_set_fpu_opts(c);
2017         else
2018                 cpu_set_nofpu_opts(c);
2019
2020         if (cpu_has_bp_ghist)
2021                 write_c0_r10k_diag(read_c0_r10k_diag() |
2022                                    R10K_DIAG_E_GHIST);
2023
2024         if (cpu_has_mips_r2_r6) {
2025                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
2026                 /* R2 has Performance Counter Interrupt indicator */
2027                 c->options |= MIPS_CPU_PCI;
2028         }
2029         else
2030                 c->srsets = 1;
2031
2032         if (cpu_has_mips_r6)
2033                 elf_hwcap |= HWCAP_MIPS_R6;
2034
2035         if (cpu_has_msa) {
2036                 c->msa_id = cpu_get_msa_id();
2037                 WARN(c->msa_id & MSA_IR_WRPF,
2038                      "Vector register partitioning unimplemented!");
2039                 elf_hwcap |= HWCAP_MIPS_MSA;
2040         }
2041
2042         if (cpu_has_vz)
2043                 cpu_probe_vz(c);
2044
2045         cpu_probe_vmbits(c);
2046
2047 #ifdef CONFIG_64BIT
2048         if (cpu == 0)
2049                 __ua_limit = ~((1ull << cpu_vmbits) - 1);
2050 #endif
2051 }
2052
2053 void cpu_report(void)
2054 {
2055         struct cpuinfo_mips *c = &current_cpu_data;
2056
2057         pr_info("CPU%d revision is: %08x (%s)\n",
2058                 smp_processor_id(), c->processor_id, cpu_name_string());
2059         if (c->options & MIPS_CPU_FPU)
2060                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
2061         if (cpu_has_msa)
2062                 pr_info("MSA revision is: %08x\n", c->msa_id);
2063 }