2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
23 #include <asm/cpu-features.h>
24 #include <asm/cpu-type.h>
26 #include <asm/mipsregs.h>
27 #include <asm/mipsmtregs.h>
29 #include <asm/watch.h>
31 #include <asm/pgtable-bits.h>
32 #include <asm/spram.h>
33 #include <asm/uaccess.h>
35 /* Hardware capabilities */
36 unsigned int elf_hwcap __read_mostly;
39 * Get the FPU Implementation/Revision.
41 static inline unsigned long cpu_get_fpu_id(void)
43 unsigned long tmp, fpu_id;
45 tmp = read_c0_status();
46 __enable_fpu(FPU_AS_IS);
47 fpu_id = read_32bit_cp1_register(CP1_REVISION);
53 * Check if the CPU has an external FPU.
55 static inline int __cpu_has_fpu(void)
57 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
60 static inline unsigned long cpu_get_msa_id(void)
62 unsigned long status, msa_id;
64 status = read_c0_status();
65 __enable_fpu(FPU_64BIT);
67 msa_id = read_msa_ir();
69 write_c0_status(status);
74 * Determine the FCSR mask for FPU hardware.
76 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
78 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
81 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
83 sr = read_c0_status();
84 __enable_fpu(FPU_AS_IS);
87 write_32bit_cp1_register(CP1_STATUS, fcsr0);
88 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
91 write_32bit_cp1_register(CP1_STATUS, fcsr1);
92 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
94 write_32bit_cp1_register(CP1_STATUS, fcsr);
98 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
102 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
103 * supported by FPU hardware.
105 static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
107 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
108 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
109 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
110 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
112 sr = read_c0_status();
113 __enable_fpu(FPU_AS_IS);
115 fir = read_32bit_cp1_register(CP1_REVISION);
116 if (fir & MIPS_FPIR_HAS2008) {
117 fcsr = read_32bit_cp1_register(CP1_STATUS);
119 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
120 write_32bit_cp1_register(CP1_STATUS, fcsr0);
121 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
123 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
124 write_32bit_cp1_register(CP1_STATUS, fcsr1);
125 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
127 write_32bit_cp1_register(CP1_STATUS, fcsr);
129 if (!(fcsr0 & FPU_CSR_NAN2008))
130 c->options |= MIPS_CPU_NAN_LEGACY;
131 if (fcsr1 & FPU_CSR_NAN2008)
132 c->options |= MIPS_CPU_NAN_2008;
134 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
135 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
137 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
139 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
140 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
142 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
144 c->options |= MIPS_CPU_NAN_LEGACY;
149 c->options |= MIPS_CPU_NAN_LEGACY;
154 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
155 * ABS.fmt/NEG.fmt execution mode.
157 static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
160 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
161 * to support by the FPU emulator according to the IEEE 754 conformance
162 * mode selected. Note that "relaxed" straps the emulator so that it
163 * allows 2008-NaN binaries even for legacy processors.
165 static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
167 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
168 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
169 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
173 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
174 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
175 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
176 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
178 c->options |= MIPS_CPU_NAN_LEGACY;
179 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
183 c->options |= MIPS_CPU_NAN_LEGACY;
184 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
187 c->options |= MIPS_CPU_NAN_2008;
188 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
189 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
192 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
198 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
199 * according to the "ieee754=" parameter.
201 static void cpu_set_nan_2008(struct cpuinfo_mips *c)
205 mips_use_nan_legacy = !!cpu_has_nan_legacy;
206 mips_use_nan_2008 = !!cpu_has_nan_2008;
209 mips_use_nan_legacy = !!cpu_has_nan_legacy;
210 mips_use_nan_2008 = !cpu_has_nan_legacy;
213 mips_use_nan_legacy = !cpu_has_nan_2008;
214 mips_use_nan_2008 = !!cpu_has_nan_2008;
217 mips_use_nan_legacy = true;
218 mips_use_nan_2008 = true;
224 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
227 * strict: accept binaries that request a NaN encoding supported by the FPU
228 * legacy: only accept legacy-NaN binaries
229 * 2008: only accept 2008-NaN binaries
230 * relaxed: accept any binaries regardless of whether supported by the FPU
232 static int __init ieee754_setup(char *s)
236 else if (!strcmp(s, "strict"))
238 else if (!strcmp(s, "legacy"))
240 else if (!strcmp(s, "2008"))
242 else if (!strcmp(s, "relaxed"))
247 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
248 cpu_set_nofpu_2008(&boot_cpu_data);
249 cpu_set_nan_2008(&boot_cpu_data);
254 early_param("ieee754", ieee754_setup);
257 * Set the FIR feature flags for the FPU emulator.
259 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
264 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
265 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
266 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
267 value |= MIPS_FPIR_D | MIPS_FPIR_S;
268 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
269 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
270 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
271 if (c->options & MIPS_CPU_NAN_2008)
272 value |= MIPS_FPIR_HAS2008;
276 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
277 static unsigned int mips_nofpu_msk31;
280 * Set options for FPU hardware.
282 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
284 c->fpu_id = cpu_get_fpu_id();
285 mips_nofpu_msk31 = c->fpu_msk31;
287 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
288 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
289 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
290 if (c->fpu_id & MIPS_FPIR_3D)
291 c->ases |= MIPS_ASE_MIPS3D;
292 if (c->fpu_id & MIPS_FPIR_FREP)
293 c->options |= MIPS_CPU_FRE;
296 cpu_set_fpu_fcsr_mask(c);
302 * Set options for the FPU emulator.
304 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
306 c->options &= ~MIPS_CPU_FPU;
307 c->fpu_msk31 = mips_nofpu_msk31;
309 cpu_set_nofpu_2008(c);
314 static int mips_fpu_disabled;
316 static int __init fpu_disable(char *s)
318 cpu_set_nofpu_opts(&boot_cpu_data);
319 mips_fpu_disabled = 1;
324 __setup("nofpu", fpu_disable);
326 int mips_dsp_disabled;
328 static int __init dsp_disable(char *s)
330 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
331 mips_dsp_disabled = 1;
336 __setup("nodsp", dsp_disable);
338 static int mips_htw_disabled;
340 static int __init htw_disable(char *s)
342 mips_htw_disabled = 1;
343 cpu_data[0].options &= ~MIPS_CPU_HTW;
344 write_c0_pwctl(read_c0_pwctl() &
345 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
350 __setup("nohtw", htw_disable);
352 static int mips_ftlb_disabled;
353 static int mips_has_ftlb_configured;
355 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
357 static int __init ftlb_disable(char *s)
359 unsigned int config4, mmuextdef;
362 * If the core hasn't done any FTLB configuration, there is nothing
365 if (!mips_has_ftlb_configured)
368 /* Disable it in the boot cpu */
369 if (set_ftlb_enable(&cpu_data[0], 0)) {
370 pr_warn("Can't turn FTLB off\n");
374 back_to_back_c0_hazard();
376 config4 = read_c0_config4();
378 /* Check that FTLB has been disabled */
379 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
380 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
381 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
382 /* This should never happen */
383 pr_warn("FTLB could not be disabled!\n");
387 mips_ftlb_disabled = 1;
388 mips_has_ftlb_configured = 0;
391 * noftlb is mainly used for debug purposes so print
392 * an informative message instead of using pr_debug()
394 pr_info("FTLB has been disabled\n");
397 * Some of these bits are duplicated in the decode_config4.
398 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
399 * once FTLB has been disabled so undo what decode_config4 did.
401 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
402 cpu_data[0].tlbsizeftlbsets;
403 cpu_data[0].tlbsizeftlbsets = 0;
404 cpu_data[0].tlbsizeftlbways = 0;
409 __setup("noftlb", ftlb_disable);
412 static inline void check_errata(void)
414 struct cpuinfo_mips *c = ¤t_cpu_data;
416 switch (current_cpu_type()) {
419 * Erratum "RPS May Cause Incorrect Instruction Execution"
420 * This code only handles VPE0, any SMP/RTOS code
421 * making use of VPE1 will be responsable for that VPE.
423 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
424 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
431 void __init check_bugs32(void)
437 * Probe whether cpu has config register by trying to play with
438 * alternate cache bit and see whether it matters.
439 * It's used by cpu_probe to distinguish between R3000A and R3081.
441 static inline int cpu_has_confreg(void)
443 #ifdef CONFIG_CPU_R3000
444 extern unsigned long r3k_cache_size(unsigned long);
445 unsigned long size1, size2;
446 unsigned long cfg = read_c0_conf();
448 size1 = r3k_cache_size(ST0_ISC);
449 write_c0_conf(cfg ^ R30XX_CONF_AC);
450 size2 = r3k_cache_size(ST0_ISC);
452 return size1 != size2;
458 static inline void set_elf_platform(int cpu, const char *plat)
461 __elf_platform = plat;
464 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
466 #ifdef __NEED_VMBITS_PROBE
467 write_c0_entryhi(0x3fffffffffffe000ULL);
468 back_to_back_c0_hazard();
469 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
473 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
476 case MIPS_CPU_ISA_M64R2:
477 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
478 case MIPS_CPU_ISA_M64R1:
479 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
481 c->isa_level |= MIPS_CPU_ISA_V;
482 case MIPS_CPU_ISA_IV:
483 c->isa_level |= MIPS_CPU_ISA_IV;
484 case MIPS_CPU_ISA_III:
485 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
488 /* R6 incompatible with everything else */
489 case MIPS_CPU_ISA_M64R6:
490 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
491 case MIPS_CPU_ISA_M32R6:
492 c->isa_level |= MIPS_CPU_ISA_M32R6;
493 /* Break here so we don't add incompatible ISAs */
495 case MIPS_CPU_ISA_M32R2:
496 c->isa_level |= MIPS_CPU_ISA_M32R2;
497 case MIPS_CPU_ISA_M32R1:
498 c->isa_level |= MIPS_CPU_ISA_M32R1;
499 case MIPS_CPU_ISA_II:
500 c->isa_level |= MIPS_CPU_ISA_II;
505 static char unknown_isa[] = KERN_ERR \
506 "Unsupported ISA type, c0.config0: %d.";
508 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
511 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
514 * 0 = All TLBWR instructions go to FTLB
515 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
516 * FTLB and 1 goes to the VTLB.
517 * 2 = 7:1: As above with 7:1 ratio.
518 * 3 = 3:1: As above with 3:1 ratio.
520 * Use the linear midpoint as the probability threshold.
522 if (probability >= 12)
524 else if (probability >= 6)
528 * So FTLB is less than 4 times bigger than VTLB.
529 * A 3:1 ratio can still be useful though.
534 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
538 /* It's implementation dependent how the FTLB can be enabled */
539 switch (c->cputype) {
543 /* proAptiv & related cores use Config6 to enable the FTLB */
544 config = read_c0_config6();
545 /* Clear the old probability value */
546 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
549 write_c0_config6(config |
550 (calculate_ftlb_probability(c)
551 << MIPS_CONF6_FTLBP_SHIFT)
552 | MIPS_CONF6_FTLBEN);
555 write_c0_config6(config & ~MIPS_CONF6_FTLBEN);
558 /* I6400 & related cores use Config7 to configure FTLB */
559 config = read_c0_config7();
560 /* Clear the old probability value */
561 config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT);
562 write_c0_config7(config | (calculate_ftlb_probability(c)
563 << MIPS_CONF7_FTLBP_SHIFT));
566 /* Flush ITLB, DTLB, VTLB and FTLB */
567 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
568 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
569 /* Loongson-3 cores use Config6 to enable the FTLB */
570 config = read_c0_config6();
573 write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
576 write_c0_config6(config | MIPS_CONF6_FTLBDIS);
585 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
587 unsigned int config0;
590 config0 = read_c0_config();
593 * Look for Standard TLB or Dual VTLB and FTLB
595 mt = config0 & MIPS_CONF_MT;
596 if (mt == MIPS_CONF_MT_TLB)
597 c->options |= MIPS_CPU_TLB;
598 else if (mt == MIPS_CONF_MT_FTLB)
599 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
601 isa = (config0 & MIPS_CONF_AT) >> 13;
604 switch ((config0 & MIPS_CONF_AR) >> 10) {
606 set_isa(c, MIPS_CPU_ISA_M32R1);
609 set_isa(c, MIPS_CPU_ISA_M32R2);
612 set_isa(c, MIPS_CPU_ISA_M32R6);
619 switch ((config0 & MIPS_CONF_AR) >> 10) {
621 set_isa(c, MIPS_CPU_ISA_M64R1);
624 set_isa(c, MIPS_CPU_ISA_M64R2);
627 set_isa(c, MIPS_CPU_ISA_M64R6);
637 return config0 & MIPS_CONF_M;
640 panic(unknown_isa, config0);
643 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
645 unsigned int config1;
647 config1 = read_c0_config1();
649 if (config1 & MIPS_CONF1_MD)
650 c->ases |= MIPS_ASE_MDMX;
651 if (config1 & MIPS_CONF1_PC)
652 c->options |= MIPS_CPU_PERF;
653 if (config1 & MIPS_CONF1_WR)
654 c->options |= MIPS_CPU_WATCH;
655 if (config1 & MIPS_CONF1_CA)
656 c->ases |= MIPS_ASE_MIPS16;
657 if (config1 & MIPS_CONF1_EP)
658 c->options |= MIPS_CPU_EJTAG;
659 if (config1 & MIPS_CONF1_FP) {
660 c->options |= MIPS_CPU_FPU;
661 c->options |= MIPS_CPU_32FPR;
664 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
665 c->tlbsizevtlb = c->tlbsize;
666 c->tlbsizeftlbsets = 0;
669 return config1 & MIPS_CONF_M;
672 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
674 unsigned int config2;
676 config2 = read_c0_config2();
678 if (config2 & MIPS_CONF2_SL)
679 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
681 return config2 & MIPS_CONF_M;
684 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
686 unsigned int config3;
688 config3 = read_c0_config3();
690 if (config3 & MIPS_CONF3_SM) {
691 c->ases |= MIPS_ASE_SMARTMIPS;
692 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
694 if (config3 & MIPS_CONF3_RXI)
695 c->options |= MIPS_CPU_RIXI;
696 if (config3 & MIPS_CONF3_CTXTC)
697 c->options |= MIPS_CPU_CTXTC;
698 if (config3 & MIPS_CONF3_DSP)
699 c->ases |= MIPS_ASE_DSP;
700 if (config3 & MIPS_CONF3_DSP2P) {
701 c->ases |= MIPS_ASE_DSP2P;
703 c->ases |= MIPS_ASE_DSP3;
705 if (config3 & MIPS_CONF3_VINT)
706 c->options |= MIPS_CPU_VINT;
707 if (config3 & MIPS_CONF3_VEIC)
708 c->options |= MIPS_CPU_VEIC;
709 if (config3 & MIPS_CONF3_LPA)
710 c->options |= MIPS_CPU_LPA;
711 if (config3 & MIPS_CONF3_MT)
712 c->ases |= MIPS_ASE_MIPSMT;
713 if (config3 & MIPS_CONF3_ULRI)
714 c->options |= MIPS_CPU_ULRI;
715 if (config3 & MIPS_CONF3_ISA)
716 c->options |= MIPS_CPU_MICROMIPS;
717 if (config3 & MIPS_CONF3_VZ)
718 c->ases |= MIPS_ASE_VZ;
719 if (config3 & MIPS_CONF3_SC)
720 c->options |= MIPS_CPU_SEGMENTS;
721 if (config3 & MIPS_CONF3_BI)
722 c->options |= MIPS_CPU_BADINSTR;
723 if (config3 & MIPS_CONF3_BP)
724 c->options |= MIPS_CPU_BADINSTRP;
725 if (config3 & MIPS_CONF3_MSA)
726 c->ases |= MIPS_ASE_MSA;
727 if (config3 & MIPS_CONF3_PW) {
729 c->options |= MIPS_CPU_HTW;
731 if (config3 & MIPS_CONF3_CDMM)
732 c->options |= MIPS_CPU_CDMM;
733 if (config3 & MIPS_CONF3_SP)
734 c->options |= MIPS_CPU_SP;
736 return config3 & MIPS_CONF_M;
739 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
741 unsigned int config4;
743 unsigned int mmuextdef;
744 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
745 unsigned long asid_mask;
747 config4 = read_c0_config4();
750 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
751 c->options |= MIPS_CPU_TLBINV;
754 * R6 has dropped the MMUExtDef field from config4.
755 * On R6 the fields always describe the FTLB, and only if it is
756 * present according to Config.MT.
758 if (!cpu_has_mips_r6)
759 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
760 else if (cpu_has_ftlb)
761 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
766 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
767 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
768 c->tlbsizevtlb = c->tlbsize;
770 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
772 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
773 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
774 c->tlbsize = c->tlbsizevtlb;
775 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
777 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
778 if (mips_ftlb_disabled)
780 newcf4 = (config4 & ~ftlb_page) |
781 (page_size_ftlb(mmuextdef) <<
782 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
783 write_c0_config4(newcf4);
784 back_to_back_c0_hazard();
785 config4 = read_c0_config4();
786 if (config4 != newcf4) {
787 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
789 /* Switch FTLB off */
790 set_ftlb_enable(c, 0);
793 c->tlbsizeftlbsets = 1 <<
794 ((config4 & MIPS_CONF4_FTLBSETS) >>
795 MIPS_CONF4_FTLBSETS_SHIFT);
796 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
797 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
798 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
799 mips_has_ftlb_configured = 1;
804 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
805 >> MIPS_CONF4_KSCREXIST_SHIFT;
807 asid_mask = MIPS_ENTRYHI_ASID;
808 if (config4 & MIPS_CONF4_AE)
809 asid_mask |= MIPS_ENTRYHI_ASIDX;
810 set_cpu_asid_mask(c, asid_mask);
813 * Warn if the computed ASID mask doesn't match the mask the kernel
814 * is built for. This may indicate either a serious problem or an
815 * easy optimisation opportunity, but either way should be addressed.
817 WARN_ON(asid_mask != cpu_asid_mask(c));
819 return config4 & MIPS_CONF_M;
822 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
824 unsigned int config5;
826 config5 = read_c0_config5();
827 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
828 write_c0_config5(config5);
830 if (config5 & MIPS_CONF5_EVA)
831 c->options |= MIPS_CPU_EVA;
832 if (config5 & MIPS_CONF5_MRP)
833 c->options |= MIPS_CPU_MAAR;
834 if (config5 & MIPS_CONF5_LLB)
835 c->options |= MIPS_CPU_RW_LLB;
836 if (config5 & MIPS_CONF5_MVH)
837 c->options |= MIPS_CPU_MVH;
838 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
839 c->options |= MIPS_CPU_VP;
841 return config5 & MIPS_CONF_M;
844 static void decode_configs(struct cpuinfo_mips *c)
848 /* MIPS32 or MIPS64 compliant CPU. */
849 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
850 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
852 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
854 /* Enable FTLB if present and not disabled */
855 set_ftlb_enable(c, !mips_ftlb_disabled);
857 ok = decode_config0(c); /* Read Config registers. */
858 BUG_ON(!ok); /* Arch spec violation! */
860 ok = decode_config1(c);
862 ok = decode_config2(c);
864 ok = decode_config3(c);
866 ok = decode_config4(c);
868 ok = decode_config5(c);
870 /* Probe the EBase.WG bit */
871 if (cpu_has_mips_r2_r6) {
875 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
876 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
877 : (s32)read_c0_ebase();
878 if (ebase & MIPS_EBASE_WG) {
879 /* WG bit already set, we can avoid the clumsy probe */
880 c->options |= MIPS_CPU_EBASE_WG;
882 /* Its UNDEFINED to change EBase while BEV=0 */
883 status = read_c0_status();
884 write_c0_status(status | ST0_BEV);
887 * On pre-r6 cores, this may well clobber the upper bits
888 * of EBase. This is hard to avoid without potentially
889 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
891 if (cpu_has_mips64r6)
892 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
894 write_c0_ebase(ebase | MIPS_EBASE_WG);
895 back_to_back_c0_hazard();
897 write_c0_status(status);
898 if (read_c0_ebase() & MIPS_EBASE_WG) {
899 c->options |= MIPS_CPU_EBASE_WG;
900 write_c0_ebase(ebase);
905 mips_probe_watch_registers(c);
907 #ifndef CONFIG_MIPS_CPS
908 if (cpu_has_mips_r2_r6) {
909 c->core = get_ebase_cpunum();
911 c->core >>= fls(core_nvpes()) - 1;
917 * Probe for certain guest capabilities by writing config bits and reading back.
918 * Finally write back the original value.
920 #define probe_gc0_config(name, maxconf, bits) \
923 tmp = read_gc0_##name(); \
924 write_gc0_##name(tmp | (bits)); \
925 back_to_back_c0_hazard(); \
926 maxconf = read_gc0_##name(); \
927 write_gc0_##name(tmp); \
931 * Probe for dynamic guest capabilities by changing certain config bits and
932 * reading back to see if they change. Finally write back the original value.
934 #define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \
936 maxconf = read_gc0_##name(); \
937 write_gc0_##name(maxconf ^ (bits)); \
938 back_to_back_c0_hazard(); \
939 dynconf = maxconf ^ read_gc0_##name(); \
940 write_gc0_##name(maxconf); \
941 maxconf |= dynconf; \
944 static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
946 unsigned int config0;
948 probe_gc0_config(config, config0, MIPS_CONF_M);
950 if (config0 & MIPS_CONF_M)
951 c->guest.conf |= BIT(1);
952 return config0 & MIPS_CONF_M;
955 static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
957 unsigned int config1, config1_dyn;
959 probe_gc0_config_dyn(config1, config1, config1_dyn,
960 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
963 if (config1 & MIPS_CONF1_FP)
964 c->guest.options |= MIPS_CPU_FPU;
965 if (config1_dyn & MIPS_CONF1_FP)
966 c->guest.options_dyn |= MIPS_CPU_FPU;
968 if (config1 & MIPS_CONF1_WR)
969 c->guest.options |= MIPS_CPU_WATCH;
970 if (config1_dyn & MIPS_CONF1_WR)
971 c->guest.options_dyn |= MIPS_CPU_WATCH;
973 if (config1 & MIPS_CONF1_PC)
974 c->guest.options |= MIPS_CPU_PERF;
975 if (config1_dyn & MIPS_CONF1_PC)
976 c->guest.options_dyn |= MIPS_CPU_PERF;
978 if (config1 & MIPS_CONF_M)
979 c->guest.conf |= BIT(2);
980 return config1 & MIPS_CONF_M;
983 static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
985 unsigned int config2;
987 probe_gc0_config(config2, config2, MIPS_CONF_M);
989 if (config2 & MIPS_CONF_M)
990 c->guest.conf |= BIT(3);
991 return config2 & MIPS_CONF_M;
994 static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
996 unsigned int config3, config3_dyn;
998 probe_gc0_config_dyn(config3, config3, config3_dyn,
999 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_CTXTC);
1001 if (config3 & MIPS_CONF3_CTXTC)
1002 c->guest.options |= MIPS_CPU_CTXTC;
1003 if (config3_dyn & MIPS_CONF3_CTXTC)
1004 c->guest.options_dyn |= MIPS_CPU_CTXTC;
1006 if (config3 & MIPS_CONF3_PW)
1007 c->guest.options |= MIPS_CPU_HTW;
1009 if (config3 & MIPS_CONF3_SC)
1010 c->guest.options |= MIPS_CPU_SEGMENTS;
1012 if (config3 & MIPS_CONF3_BI)
1013 c->guest.options |= MIPS_CPU_BADINSTR;
1014 if (config3 & MIPS_CONF3_BP)
1015 c->guest.options |= MIPS_CPU_BADINSTRP;
1017 if (config3 & MIPS_CONF3_MSA)
1018 c->guest.ases |= MIPS_ASE_MSA;
1019 if (config3_dyn & MIPS_CONF3_MSA)
1020 c->guest.ases_dyn |= MIPS_ASE_MSA;
1022 if (config3 & MIPS_CONF_M)
1023 c->guest.conf |= BIT(4);
1024 return config3 & MIPS_CONF_M;
1027 static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
1029 unsigned int config4;
1031 probe_gc0_config(config4, config4,
1032 MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
1034 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
1035 >> MIPS_CONF4_KSCREXIST_SHIFT;
1037 if (config4 & MIPS_CONF_M)
1038 c->guest.conf |= BIT(5);
1039 return config4 & MIPS_CONF_M;
1042 static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
1044 unsigned int config5, config5_dyn;
1046 probe_gc0_config_dyn(config5, config5, config5_dyn,
1047 MIPS_CONF_M | MIPS_CONF5_MRP);
1049 if (config5 & MIPS_CONF5_MRP)
1050 c->guest.options |= MIPS_CPU_MAAR;
1051 if (config5_dyn & MIPS_CONF5_MRP)
1052 c->guest.options_dyn |= MIPS_CPU_MAAR;
1054 if (config5 & MIPS_CONF5_LLB)
1055 c->guest.options |= MIPS_CPU_RW_LLB;
1057 if (config5 & MIPS_CONF_M)
1058 c->guest.conf |= BIT(6);
1059 return config5 & MIPS_CONF_M;
1062 static inline void decode_guest_configs(struct cpuinfo_mips *c)
1066 ok = decode_guest_config0(c);
1068 ok = decode_guest_config1(c);
1070 ok = decode_guest_config2(c);
1072 ok = decode_guest_config3(c);
1074 ok = decode_guest_config4(c);
1076 decode_guest_config5(c);
1079 static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
1081 unsigned int guestctl0, temp;
1083 guestctl0 = read_c0_guestctl0();
1085 if (guestctl0 & MIPS_GCTL0_G0E)
1086 c->options |= MIPS_CPU_GUESTCTL0EXT;
1087 if (guestctl0 & MIPS_GCTL0_G1)
1088 c->options |= MIPS_CPU_GUESTCTL1;
1089 if (guestctl0 & MIPS_GCTL0_G2)
1090 c->options |= MIPS_CPU_GUESTCTL2;
1091 if (!(guestctl0 & MIPS_GCTL0_RAD)) {
1092 c->options |= MIPS_CPU_GUESTID;
1095 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
1096 * first, otherwise all data accesses will be fully virtualised
1097 * as if they were performed by guest mode.
1099 write_c0_guestctl1(0);
1102 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
1103 back_to_back_c0_hazard();
1104 temp = read_c0_guestctl0();
1106 if (temp & MIPS_GCTL0_DRG) {
1107 write_c0_guestctl0(guestctl0);
1108 c->options |= MIPS_CPU_DRG;
1113 static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1115 if (cpu_has_guestid) {
1116 /* determine the number of bits of GuestID available */
1117 write_c0_guestctl1(MIPS_GCTL1_ID);
1118 back_to_back_c0_hazard();
1119 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1120 >> MIPS_GCTL1_ID_SHIFT;
1121 write_c0_guestctl1(0);
1125 static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1127 /* determine the number of bits of GTOffset available */
1128 write_c0_gtoffset(0xffffffff);
1129 back_to_back_c0_hazard();
1130 c->gtoffset_mask = read_c0_gtoffset();
1131 write_c0_gtoffset(0);
1134 static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1136 cpu_probe_guestctl0(c);
1137 if (cpu_has_guestctl1)
1138 cpu_probe_guestctl1(c);
1140 cpu_probe_gtoffset(c);
1142 decode_guest_configs(c);
1145 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1148 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1150 switch (c->processor_id & PRID_IMP_MASK) {
1151 case PRID_IMP_R2000:
1152 c->cputype = CPU_R2000;
1153 __cpu_name[cpu] = "R2000";
1154 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1155 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1157 if (__cpu_has_fpu())
1158 c->options |= MIPS_CPU_FPU;
1161 case PRID_IMP_R3000:
1162 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
1163 if (cpu_has_confreg()) {
1164 c->cputype = CPU_R3081E;
1165 __cpu_name[cpu] = "R3081";
1167 c->cputype = CPU_R3000A;
1168 __cpu_name[cpu] = "R3000A";
1171 c->cputype = CPU_R3000;
1172 __cpu_name[cpu] = "R3000";
1174 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1175 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1177 if (__cpu_has_fpu())
1178 c->options |= MIPS_CPU_FPU;
1181 case PRID_IMP_R4000:
1182 if (read_c0_config() & CONF_SC) {
1183 if ((c->processor_id & PRID_REV_MASK) >=
1185 c->cputype = CPU_R4400PC;
1186 __cpu_name[cpu] = "R4400PC";
1188 c->cputype = CPU_R4000PC;
1189 __cpu_name[cpu] = "R4000PC";
1192 int cca = read_c0_config() & CONF_CM_CMASK;
1196 * SC and MC versions can't be reliably told apart,
1197 * but only the latter support coherent caching
1198 * modes so assume the firmware has set the KSEG0
1199 * coherency attribute reasonably (if uncached, we
1203 case CONF_CM_CACHABLE_CE:
1204 case CONF_CM_CACHABLE_COW:
1205 case CONF_CM_CACHABLE_CUW:
1212 if ((c->processor_id & PRID_REV_MASK) >=
1214 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1215 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
1217 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1218 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
1222 set_isa(c, MIPS_CPU_ISA_III);
1223 c->fpu_msk31 |= FPU_CSR_CONDX;
1224 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1225 MIPS_CPU_WATCH | MIPS_CPU_VCE |
1229 case PRID_IMP_VR41XX:
1230 set_isa(c, MIPS_CPU_ISA_III);
1231 c->fpu_msk31 |= FPU_CSR_CONDX;
1232 c->options = R4K_OPTS;
1234 switch (c->processor_id & 0xf0) {
1235 case PRID_REV_VR4111:
1236 c->cputype = CPU_VR4111;
1237 __cpu_name[cpu] = "NEC VR4111";
1239 case PRID_REV_VR4121:
1240 c->cputype = CPU_VR4121;
1241 __cpu_name[cpu] = "NEC VR4121";
1243 case PRID_REV_VR4122:
1244 if ((c->processor_id & 0xf) < 0x3) {
1245 c->cputype = CPU_VR4122;
1246 __cpu_name[cpu] = "NEC VR4122";
1248 c->cputype = CPU_VR4181A;
1249 __cpu_name[cpu] = "NEC VR4181A";
1252 case PRID_REV_VR4130:
1253 if ((c->processor_id & 0xf) < 0x4) {
1254 c->cputype = CPU_VR4131;
1255 __cpu_name[cpu] = "NEC VR4131";
1257 c->cputype = CPU_VR4133;
1258 c->options |= MIPS_CPU_LLSC;
1259 __cpu_name[cpu] = "NEC VR4133";
1263 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1264 c->cputype = CPU_VR41XX;
1265 __cpu_name[cpu] = "NEC Vr41xx";
1269 case PRID_IMP_R4300:
1270 c->cputype = CPU_R4300;
1271 __cpu_name[cpu] = "R4300";
1272 set_isa(c, MIPS_CPU_ISA_III);
1273 c->fpu_msk31 |= FPU_CSR_CONDX;
1274 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1278 case PRID_IMP_R4600:
1279 c->cputype = CPU_R4600;
1280 __cpu_name[cpu] = "R4600";
1281 set_isa(c, MIPS_CPU_ISA_III);
1282 c->fpu_msk31 |= FPU_CSR_CONDX;
1283 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1288 case PRID_IMP_R4650:
1290 * This processor doesn't have an MMU, so it's not
1291 * "real easy" to run Linux on it. It is left purely
1292 * for documentation. Commented out because it shares
1293 * it's c0_prid id number with the TX3900.
1295 c->cputype = CPU_R4650;
1296 __cpu_name[cpu] = "R4650";
1297 set_isa(c, MIPS_CPU_ISA_III);
1298 c->fpu_msk31 |= FPU_CSR_CONDX;
1299 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1304 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1305 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1307 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1308 c->cputype = CPU_TX3927;
1309 __cpu_name[cpu] = "TX3927";
1312 switch (c->processor_id & PRID_REV_MASK) {
1313 case PRID_REV_TX3912:
1314 c->cputype = CPU_TX3912;
1315 __cpu_name[cpu] = "TX3912";
1318 case PRID_REV_TX3922:
1319 c->cputype = CPU_TX3922;
1320 __cpu_name[cpu] = "TX3922";
1326 case PRID_IMP_R4700:
1327 c->cputype = CPU_R4700;
1328 __cpu_name[cpu] = "R4700";
1329 set_isa(c, MIPS_CPU_ISA_III);
1330 c->fpu_msk31 |= FPU_CSR_CONDX;
1331 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1336 c->cputype = CPU_TX49XX;
1337 __cpu_name[cpu] = "R49XX";
1338 set_isa(c, MIPS_CPU_ISA_III);
1339 c->fpu_msk31 |= FPU_CSR_CONDX;
1340 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1341 if (!(c->processor_id & 0x08))
1342 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1345 case PRID_IMP_R5000:
1346 c->cputype = CPU_R5000;
1347 __cpu_name[cpu] = "R5000";
1348 set_isa(c, MIPS_CPU_ISA_IV);
1349 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1353 case PRID_IMP_R5432:
1354 c->cputype = CPU_R5432;
1355 __cpu_name[cpu] = "R5432";
1356 set_isa(c, MIPS_CPU_ISA_IV);
1357 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1358 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1361 case PRID_IMP_R5500:
1362 c->cputype = CPU_R5500;
1363 __cpu_name[cpu] = "R5500";
1364 set_isa(c, MIPS_CPU_ISA_IV);
1365 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1366 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1369 case PRID_IMP_NEVADA:
1370 c->cputype = CPU_NEVADA;
1371 __cpu_name[cpu] = "Nevada";
1372 set_isa(c, MIPS_CPU_ISA_IV);
1373 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1374 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1377 case PRID_IMP_R6000:
1378 c->cputype = CPU_R6000;
1379 __cpu_name[cpu] = "R6000";
1380 set_isa(c, MIPS_CPU_ISA_II);
1381 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1382 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
1386 case PRID_IMP_R6000A:
1387 c->cputype = CPU_R6000A;
1388 __cpu_name[cpu] = "R6000A";
1389 set_isa(c, MIPS_CPU_ISA_II);
1390 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1391 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
1395 case PRID_IMP_RM7000:
1396 c->cputype = CPU_RM7000;
1397 __cpu_name[cpu] = "RM7000";
1398 set_isa(c, MIPS_CPU_ISA_IV);
1399 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1402 * Undocumented RM7000: Bit 29 in the info register of
1403 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1406 * 29 1 => 64 entry JTLB
1407 * 0 => 48 entry JTLB
1409 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1411 case PRID_IMP_R8000:
1412 c->cputype = CPU_R8000;
1413 __cpu_name[cpu] = "RM8000";
1414 set_isa(c, MIPS_CPU_ISA_IV);
1415 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
1416 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1418 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
1420 case PRID_IMP_R10000:
1421 c->cputype = CPU_R10000;
1422 __cpu_name[cpu] = "R10000";
1423 set_isa(c, MIPS_CPU_ISA_IV);
1424 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1425 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1426 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1430 case PRID_IMP_R12000:
1431 c->cputype = CPU_R12000;
1432 __cpu_name[cpu] = "R12000";
1433 set_isa(c, MIPS_CPU_ISA_IV);
1434 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1435 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1436 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1437 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1440 case PRID_IMP_R14000:
1441 if (((c->processor_id >> 4) & 0x0f) > 2) {
1442 c->cputype = CPU_R16000;
1443 __cpu_name[cpu] = "R16000";
1445 c->cputype = CPU_R14000;
1446 __cpu_name[cpu] = "R14000";
1448 set_isa(c, MIPS_CPU_ISA_IV);
1449 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1450 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1451 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1452 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1455 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1456 switch (c->processor_id & PRID_REV_MASK) {
1457 case PRID_REV_LOONGSON2E:
1458 c->cputype = CPU_LOONGSON2;
1459 __cpu_name[cpu] = "ICT Loongson-2";
1460 set_elf_platform(cpu, "loongson2e");
1461 set_isa(c, MIPS_CPU_ISA_III);
1462 c->fpu_msk31 |= FPU_CSR_CONDX;
1464 case PRID_REV_LOONGSON2F:
1465 c->cputype = CPU_LOONGSON2;
1466 __cpu_name[cpu] = "ICT Loongson-2";
1467 set_elf_platform(cpu, "loongson2f");
1468 set_isa(c, MIPS_CPU_ISA_III);
1469 c->fpu_msk31 |= FPU_CSR_CONDX;
1471 case PRID_REV_LOONGSON3A_R1:
1472 c->cputype = CPU_LOONGSON3;
1473 __cpu_name[cpu] = "ICT Loongson-3";
1474 set_elf_platform(cpu, "loongson3a");
1475 set_isa(c, MIPS_CPU_ISA_M64R1);
1477 case PRID_REV_LOONGSON3B_R1:
1478 case PRID_REV_LOONGSON3B_R2:
1479 c->cputype = CPU_LOONGSON3;
1480 __cpu_name[cpu] = "ICT Loongson-3";
1481 set_elf_platform(cpu, "loongson3b");
1482 set_isa(c, MIPS_CPU_ISA_M64R1);
1486 c->options = R4K_OPTS |
1487 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1490 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1492 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1495 c->cputype = CPU_LOONGSON1;
1497 switch (c->processor_id & PRID_REV_MASK) {
1498 case PRID_REV_LOONGSON1B:
1499 __cpu_name[cpu] = "Loongson 1B";
1507 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1509 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1510 switch (c->processor_id & PRID_IMP_MASK) {
1511 case PRID_IMP_QEMU_GENERIC:
1512 c->writecombine = _CACHE_UNCACHED;
1513 c->cputype = CPU_QEMU_GENERIC;
1514 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1517 c->cputype = CPU_4KC;
1518 c->writecombine = _CACHE_UNCACHED;
1519 __cpu_name[cpu] = "MIPS 4Kc";
1522 case PRID_IMP_4KECR2:
1523 c->cputype = CPU_4KEC;
1524 c->writecombine = _CACHE_UNCACHED;
1525 __cpu_name[cpu] = "MIPS 4KEc";
1529 c->cputype = CPU_4KSC;
1530 c->writecombine = _CACHE_UNCACHED;
1531 __cpu_name[cpu] = "MIPS 4KSc";
1534 c->cputype = CPU_5KC;
1535 c->writecombine = _CACHE_UNCACHED;
1536 __cpu_name[cpu] = "MIPS 5Kc";
1539 c->cputype = CPU_5KE;
1540 c->writecombine = _CACHE_UNCACHED;
1541 __cpu_name[cpu] = "MIPS 5KE";
1544 c->cputype = CPU_20KC;
1545 c->writecombine = _CACHE_UNCACHED;
1546 __cpu_name[cpu] = "MIPS 20Kc";
1549 c->cputype = CPU_24K;
1550 c->writecombine = _CACHE_UNCACHED;
1551 __cpu_name[cpu] = "MIPS 24Kc";
1554 c->cputype = CPU_24K;
1555 c->writecombine = _CACHE_UNCACHED;
1556 __cpu_name[cpu] = "MIPS 24KEc";
1559 c->cputype = CPU_25KF;
1560 c->writecombine = _CACHE_UNCACHED;
1561 __cpu_name[cpu] = "MIPS 25Kc";
1564 c->cputype = CPU_34K;
1565 c->writecombine = _CACHE_UNCACHED;
1566 __cpu_name[cpu] = "MIPS 34Kc";
1569 c->cputype = CPU_74K;
1570 c->writecombine = _CACHE_UNCACHED;
1571 __cpu_name[cpu] = "MIPS 74Kc";
1573 case PRID_IMP_M14KC:
1574 c->cputype = CPU_M14KC;
1575 c->writecombine = _CACHE_UNCACHED;
1576 __cpu_name[cpu] = "MIPS M14Kc";
1578 case PRID_IMP_M14KEC:
1579 c->cputype = CPU_M14KEC;
1580 c->writecombine = _CACHE_UNCACHED;
1581 __cpu_name[cpu] = "MIPS M14KEc";
1583 case PRID_IMP_1004K:
1584 c->cputype = CPU_1004K;
1585 c->writecombine = _CACHE_UNCACHED;
1586 __cpu_name[cpu] = "MIPS 1004Kc";
1588 case PRID_IMP_1074K:
1589 c->cputype = CPU_1074K;
1590 c->writecombine = _CACHE_UNCACHED;
1591 __cpu_name[cpu] = "MIPS 1074Kc";
1593 case PRID_IMP_INTERAPTIV_UP:
1594 c->cputype = CPU_INTERAPTIV;
1595 __cpu_name[cpu] = "MIPS interAptiv";
1597 case PRID_IMP_INTERAPTIV_MP:
1598 c->cputype = CPU_INTERAPTIV;
1599 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1601 case PRID_IMP_PROAPTIV_UP:
1602 c->cputype = CPU_PROAPTIV;
1603 __cpu_name[cpu] = "MIPS proAptiv";
1605 case PRID_IMP_PROAPTIV_MP:
1606 c->cputype = CPU_PROAPTIV;
1607 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1609 case PRID_IMP_P5600:
1610 c->cputype = CPU_P5600;
1611 __cpu_name[cpu] = "MIPS P5600";
1613 case PRID_IMP_P6600:
1614 c->cputype = CPU_P6600;
1615 __cpu_name[cpu] = "MIPS P6600";
1617 case PRID_IMP_I6400:
1618 c->cputype = CPU_I6400;
1619 __cpu_name[cpu] = "MIPS I6400";
1621 case PRID_IMP_M5150:
1622 c->cputype = CPU_M5150;
1623 __cpu_name[cpu] = "MIPS M5150";
1625 case PRID_IMP_M6250:
1626 c->cputype = CPU_M6250;
1627 __cpu_name[cpu] = "MIPS M6250";
1636 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1639 switch (c->processor_id & PRID_IMP_MASK) {
1640 case PRID_IMP_AU1_REV1:
1641 case PRID_IMP_AU1_REV2:
1642 c->cputype = CPU_ALCHEMY;
1643 switch ((c->processor_id >> 24) & 0xff) {
1645 __cpu_name[cpu] = "Au1000";
1648 __cpu_name[cpu] = "Au1500";
1651 __cpu_name[cpu] = "Au1100";
1654 __cpu_name[cpu] = "Au1550";
1657 __cpu_name[cpu] = "Au1200";
1658 if ((c->processor_id & PRID_REV_MASK) == 2)
1659 __cpu_name[cpu] = "Au1250";
1662 __cpu_name[cpu] = "Au1210";
1665 __cpu_name[cpu] = "Au1xxx";
1672 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1676 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1677 switch (c->processor_id & PRID_IMP_MASK) {
1679 c->cputype = CPU_SB1;
1680 __cpu_name[cpu] = "SiByte SB1";
1681 /* FPU in pass1 is known to have issues. */
1682 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1683 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1686 c->cputype = CPU_SB1A;
1687 __cpu_name[cpu] = "SiByte SB1A";
1692 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1695 switch (c->processor_id & PRID_IMP_MASK) {
1696 case PRID_IMP_SR71000:
1697 c->cputype = CPU_SR71000;
1698 __cpu_name[cpu] = "Sandcraft SR71000";
1705 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1708 switch (c->processor_id & PRID_IMP_MASK) {
1709 case PRID_IMP_PR4450:
1710 c->cputype = CPU_PR4450;
1711 __cpu_name[cpu] = "Philips PR4450";
1712 set_isa(c, MIPS_CPU_ISA_M32R1);
1717 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1720 switch (c->processor_id & PRID_IMP_MASK) {
1721 case PRID_IMP_BMIPS32_REV4:
1722 case PRID_IMP_BMIPS32_REV8:
1723 c->cputype = CPU_BMIPS32;
1724 __cpu_name[cpu] = "Broadcom BMIPS32";
1725 set_elf_platform(cpu, "bmips32");
1727 case PRID_IMP_BMIPS3300:
1728 case PRID_IMP_BMIPS3300_ALT:
1729 case PRID_IMP_BMIPS3300_BUG:
1730 c->cputype = CPU_BMIPS3300;
1731 __cpu_name[cpu] = "Broadcom BMIPS3300";
1732 set_elf_platform(cpu, "bmips3300");
1734 case PRID_IMP_BMIPS43XX: {
1735 int rev = c->processor_id & PRID_REV_MASK;
1737 if (rev >= PRID_REV_BMIPS4380_LO &&
1738 rev <= PRID_REV_BMIPS4380_HI) {
1739 c->cputype = CPU_BMIPS4380;
1740 __cpu_name[cpu] = "Broadcom BMIPS4380";
1741 set_elf_platform(cpu, "bmips4380");
1742 c->options |= MIPS_CPU_RIXI;
1744 c->cputype = CPU_BMIPS4350;
1745 __cpu_name[cpu] = "Broadcom BMIPS4350";
1746 set_elf_platform(cpu, "bmips4350");
1750 case PRID_IMP_BMIPS5000:
1751 case PRID_IMP_BMIPS5200:
1752 c->cputype = CPU_BMIPS5000;
1753 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1754 __cpu_name[cpu] = "Broadcom BMIPS5200";
1756 __cpu_name[cpu] = "Broadcom BMIPS5000";
1757 set_elf_platform(cpu, "bmips5000");
1758 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
1763 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1766 switch (c->processor_id & PRID_IMP_MASK) {
1767 case PRID_IMP_CAVIUM_CN38XX:
1768 case PRID_IMP_CAVIUM_CN31XX:
1769 case PRID_IMP_CAVIUM_CN30XX:
1770 c->cputype = CPU_CAVIUM_OCTEON;
1771 __cpu_name[cpu] = "Cavium Octeon";
1773 case PRID_IMP_CAVIUM_CN58XX:
1774 case PRID_IMP_CAVIUM_CN56XX:
1775 case PRID_IMP_CAVIUM_CN50XX:
1776 case PRID_IMP_CAVIUM_CN52XX:
1777 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1778 __cpu_name[cpu] = "Cavium Octeon+";
1780 set_elf_platform(cpu, "octeon");
1782 case PRID_IMP_CAVIUM_CN61XX:
1783 case PRID_IMP_CAVIUM_CN63XX:
1784 case PRID_IMP_CAVIUM_CN66XX:
1785 case PRID_IMP_CAVIUM_CN68XX:
1786 case PRID_IMP_CAVIUM_CNF71XX:
1787 c->cputype = CPU_CAVIUM_OCTEON2;
1788 __cpu_name[cpu] = "Cavium Octeon II";
1789 set_elf_platform(cpu, "octeon2");
1791 case PRID_IMP_CAVIUM_CN70XX:
1792 case PRID_IMP_CAVIUM_CN73XX:
1793 case PRID_IMP_CAVIUM_CNF75XX:
1794 case PRID_IMP_CAVIUM_CN78XX:
1795 c->cputype = CPU_CAVIUM_OCTEON3;
1796 __cpu_name[cpu] = "Cavium Octeon III";
1797 set_elf_platform(cpu, "octeon3");
1800 printk(KERN_INFO "Unknown Octeon chip!\n");
1801 c->cputype = CPU_UNKNOWN;
1806 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1808 switch (c->processor_id & PRID_IMP_MASK) {
1809 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1810 switch (c->processor_id & PRID_REV_MASK) {
1811 case PRID_REV_LOONGSON3A_R2:
1812 c->cputype = CPU_LOONGSON3;
1813 __cpu_name[cpu] = "ICT Loongson-3";
1814 set_elf_platform(cpu, "loongson3a");
1815 set_isa(c, MIPS_CPU_ISA_M64R2);
1820 c->options |= MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
1821 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1824 panic("Unknown Loongson Processor ID!");
1829 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1832 /* JZRISC does not implement the CP0 counter. */
1833 c->options &= ~MIPS_CPU_COUNTER;
1834 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1835 switch (c->processor_id & PRID_IMP_MASK) {
1836 case PRID_IMP_JZRISC:
1837 c->cputype = CPU_JZRISC;
1838 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1839 __cpu_name[cpu] = "Ingenic JZRISC";
1842 panic("Unknown Ingenic Processor ID!");
1847 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1851 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1852 c->cputype = CPU_ALCHEMY;
1853 __cpu_name[cpu] = "Au1300";
1854 /* following stuff is not for Alchemy */
1858 c->options = (MIPS_CPU_TLB |
1866 switch (c->processor_id & PRID_IMP_MASK) {
1867 case PRID_IMP_NETLOGIC_XLP2XX:
1868 case PRID_IMP_NETLOGIC_XLP9XX:
1869 case PRID_IMP_NETLOGIC_XLP5XX:
1870 c->cputype = CPU_XLP;
1871 __cpu_name[cpu] = "Broadcom XLPII";
1874 case PRID_IMP_NETLOGIC_XLP8XX:
1875 case PRID_IMP_NETLOGIC_XLP3XX:
1876 c->cputype = CPU_XLP;
1877 __cpu_name[cpu] = "Netlogic XLP";
1880 case PRID_IMP_NETLOGIC_XLR732:
1881 case PRID_IMP_NETLOGIC_XLR716:
1882 case PRID_IMP_NETLOGIC_XLR532:
1883 case PRID_IMP_NETLOGIC_XLR308:
1884 case PRID_IMP_NETLOGIC_XLR532C:
1885 case PRID_IMP_NETLOGIC_XLR516C:
1886 case PRID_IMP_NETLOGIC_XLR508C:
1887 case PRID_IMP_NETLOGIC_XLR308C:
1888 c->cputype = CPU_XLR;
1889 __cpu_name[cpu] = "Netlogic XLR";
1892 case PRID_IMP_NETLOGIC_XLS608:
1893 case PRID_IMP_NETLOGIC_XLS408:
1894 case PRID_IMP_NETLOGIC_XLS404:
1895 case PRID_IMP_NETLOGIC_XLS208:
1896 case PRID_IMP_NETLOGIC_XLS204:
1897 case PRID_IMP_NETLOGIC_XLS108:
1898 case PRID_IMP_NETLOGIC_XLS104:
1899 case PRID_IMP_NETLOGIC_XLS616B:
1900 case PRID_IMP_NETLOGIC_XLS608B:
1901 case PRID_IMP_NETLOGIC_XLS416B:
1902 case PRID_IMP_NETLOGIC_XLS412B:
1903 case PRID_IMP_NETLOGIC_XLS408B:
1904 case PRID_IMP_NETLOGIC_XLS404B:
1905 c->cputype = CPU_XLR;
1906 __cpu_name[cpu] = "Netlogic XLS";
1910 pr_info("Unknown Netlogic chip id [%02x]!\n",
1912 c->cputype = CPU_XLR;
1916 if (c->cputype == CPU_XLP) {
1917 set_isa(c, MIPS_CPU_ISA_M64R2);
1918 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1919 /* This will be updated again after all threads are woken up */
1920 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1922 set_isa(c, MIPS_CPU_ISA_M64R1);
1923 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1925 c->kscratch_mask = 0xf;
1929 /* For use by uaccess.h */
1931 EXPORT_SYMBOL(__ua_limit);
1934 const char *__cpu_name[NR_CPUS];
1935 const char *__elf_platform;
1937 void cpu_probe(void)
1939 struct cpuinfo_mips *c = ¤t_cpu_data;
1940 unsigned int cpu = smp_processor_id();
1942 c->processor_id = PRID_IMP_UNKNOWN;
1943 c->fpu_id = FPIR_IMP_NONE;
1944 c->cputype = CPU_UNKNOWN;
1945 c->writecombine = _CACHE_UNCACHED;
1947 c->fpu_csr31 = FPU_CSR_RN;
1948 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1950 c->processor_id = read_c0_prid();
1951 switch (c->processor_id & PRID_COMP_MASK) {
1952 case PRID_COMP_LEGACY:
1953 cpu_probe_legacy(c, cpu);
1955 case PRID_COMP_MIPS:
1956 cpu_probe_mips(c, cpu);
1958 case PRID_COMP_ALCHEMY:
1959 cpu_probe_alchemy(c, cpu);
1961 case PRID_COMP_SIBYTE:
1962 cpu_probe_sibyte(c, cpu);
1964 case PRID_COMP_BROADCOM:
1965 cpu_probe_broadcom(c, cpu);
1967 case PRID_COMP_SANDCRAFT:
1968 cpu_probe_sandcraft(c, cpu);
1971 cpu_probe_nxp(c, cpu);
1973 case PRID_COMP_CAVIUM:
1974 cpu_probe_cavium(c, cpu);
1976 case PRID_COMP_LOONGSON:
1977 cpu_probe_loongson(c, cpu);
1979 case PRID_COMP_INGENIC_D0:
1980 case PRID_COMP_INGENIC_D1:
1981 case PRID_COMP_INGENIC_E1:
1982 cpu_probe_ingenic(c, cpu);
1984 case PRID_COMP_NETLOGIC:
1985 cpu_probe_netlogic(c, cpu);
1989 BUG_ON(!__cpu_name[cpu]);
1990 BUG_ON(c->cputype == CPU_UNKNOWN);
1993 * Platform code can force the cpu type to optimize code
1994 * generation. In that case be sure the cpu type is correctly
1995 * manually setup otherwise it could trigger some nasty bugs.
1997 BUG_ON(current_cpu_type() != c->cputype);
2000 /* Enable the RIXI exceptions */
2001 set_c0_pagegrain(PG_IEC);
2002 back_to_back_c0_hazard();
2003 /* Verify the IEC bit is set */
2004 if (read_c0_pagegrain() & PG_IEC)
2005 c->options |= MIPS_CPU_RIXIEX;
2008 if (mips_fpu_disabled)
2009 c->options &= ~MIPS_CPU_FPU;
2011 if (mips_dsp_disabled)
2012 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
2014 if (mips_htw_disabled) {
2015 c->options &= ~MIPS_CPU_HTW;
2016 write_c0_pwctl(read_c0_pwctl() &
2017 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
2020 if (c->options & MIPS_CPU_FPU)
2021 cpu_set_fpu_opts(c);
2023 cpu_set_nofpu_opts(c);
2025 if (cpu_has_bp_ghist)
2026 write_c0_r10k_diag(read_c0_r10k_diag() |
2029 if (cpu_has_mips_r2_r6) {
2030 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
2031 /* R2 has Performance Counter Interrupt indicator */
2032 c->options |= MIPS_CPU_PCI;
2037 if (cpu_has_mips_r6)
2038 elf_hwcap |= HWCAP_MIPS_R6;
2041 c->msa_id = cpu_get_msa_id();
2042 WARN(c->msa_id & MSA_IR_WRPF,
2043 "Vector register partitioning unimplemented!");
2044 elf_hwcap |= HWCAP_MIPS_MSA;
2050 cpu_probe_vmbits(c);
2054 __ua_limit = ~((1ull << cpu_vmbits) - 1);
2058 void cpu_report(void)
2060 struct cpuinfo_mips *c = ¤t_cpu_data;
2062 pr_info("CPU%d revision is: %08x (%s)\n",
2063 smp_processor_id(), c->processor_id, cpu_name_string());
2064 if (c->options & MIPS_CPU_FPU)
2065 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
2067 pr_info("MSA revision is: %08x\n", c->msa_id);