arch/mips/kvm/mips.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: MIPS specific KVM APIs
   7  *
   8  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/errno.h>
  14 #include <linux/err.h>
  15 #include <linux/kdebug.h>
  16 #include <linux/module.h>
  17 #include <linux/uaccess.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/fs.h>
  20 #include <linux/bootmem.h>
  21 #include <asm/fpu.h>
  22 #include <asm/page.h>
  23 #include <asm/cacheflush.h>
  24 #include <asm/mmu_context.h>
  25 #include <asm/pgtable.h>
  26
  27 #include <linux/kvm_host.h>
  28
  29 #include "interrupt.h"
  30 #include "commpage.h"
  31
  32 #define CREATE_TRACE_POINTS
  33 #include "trace.h"
  34
  35 #ifndef VECTORSPACING
  36 #define VECTORSPACING 0x100     /* for EI/VI mode */
  37 #endif
  38
  39 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
  40 struct kvm_stats_debugfs_item debugfs_entries[] = {
  41         { "wait",         VCPU_STAT(wait_exits),         KVM_STAT_VCPU },
  42         { "cache",        VCPU_STAT(cache_exits),        KVM_STAT_VCPU },
  43         { "signal",       VCPU_STAT(signal_exits),       KVM_STAT_VCPU },
  44         { "interrupt",    VCPU_STAT(int_exits),          KVM_STAT_VCPU },
  45         { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
  46         { "tlbmod",       VCPU_STAT(tlbmod_exits),       KVM_STAT_VCPU },
  47         { "tlbmiss_ld",   VCPU_STAT(tlbmiss_ld_exits),   KVM_STAT_VCPU },
  48         { "tlbmiss_st",   VCPU_STAT(tlbmiss_st_exits),   KVM_STAT_VCPU },
  49         { "addrerr_st",   VCPU_STAT(addrerr_st_exits),   KVM_STAT_VCPU },
  50         { "addrerr_ld",   VCPU_STAT(addrerr_ld_exits),   KVM_STAT_VCPU },
  51         { "syscall",      VCPU_STAT(syscall_exits),      KVM_STAT_VCPU },
  52         { "resvd_inst",   VCPU_STAT(resvd_inst_exits),   KVM_STAT_VCPU },
  53         { "break_inst",   VCPU_STAT(break_inst_exits),   KVM_STAT_VCPU },
  54         { "trap_inst",    VCPU_STAT(trap_inst_exits),    KVM_STAT_VCPU },
  55         { "msa_fpe",      VCPU_STAT(msa_fpe_exits),      KVM_STAT_VCPU },
  56         { "fpe",          VCPU_STAT(fpe_exits),          KVM_STAT_VCPU },
  57         { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
  58         { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
  59         { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
  60         { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
  61         { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
  62         { "halt_wakeup",  VCPU_STAT(halt_wakeup),        KVM_STAT_VCPU },
  63         {NULL}
  64 };
  65
  66 /*
  67  * XXXKYMA: We are simulatoring a processor that has the WII bit set in
  68  * Config7, so we are "runnable" if interrupts are pending
  69  */
  70 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
  71 {
  72         return !!(vcpu->arch.pending_exceptions);
  73 }
  74
  75 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
  76 {
  77         return 1;
  78 }
  79
  80 int kvm_arch_hardware_enable(void)
  81 {
  82         return 0;
  83 }
  84
  85 int kvm_arch_hardware_setup(void)
  86 {
  87         return 0;
  88 }
  89
  90 void kvm_arch_check_processor_compat(void *rtn)
  91 {
  92         *(int *)rtn = 0;
  93 }
  94
  95 static void kvm_mips_init_tlbs(struct kvm *kvm)
  96 {
  97         unsigned long wired;
  98
  99         /*
 100          * Add a wired entry to the TLB, it is used to map the commpage to
 101          * the Guest kernel
 102          */
 103         wired = read_c0_wired();
 104         write_c0_wired(wired + 1);
 105         mtc0_tlbw_hazard();
 106         kvm->arch.commpage_tlb = wired;
 107
 108         kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
 109                   kvm->arch.commpage_tlb);
 110 }
 111
 112 static void kvm_mips_init_vm_percpu(void *arg)
 113 {
 114         struct kvm *kvm = (struct kvm *)arg;
 115
 116         kvm_mips_init_tlbs(kvm);
 117         kvm_mips_callbacks->vm_init(kvm);
 118
 119 }
 120
 121 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
 122 {
 123         if (atomic_inc_return(&kvm_mips_instance) == 1) {
 124                 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
 125                           __func__);
 126                 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1);
 127         }
 128
 129         return 0;
 130 }
 131
 132 bool kvm_arch_has_vcpu_debugfs(void)
 133 {
 134         return false;
 135 }
 136
 137 int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu)
 138 {
 139         return 0;
 140 }
 141
 142 void kvm_mips_free_vcpus(struct kvm *kvm)
 143 {
 144         unsigned int i;
 145         struct kvm_vcpu *vcpu;
 146
 147         /* Put the pages we reserved for the guest pmap */
 148         for (i = 0; i < kvm->arch.guest_pmap_npages; i++) {
 149                 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE)
 150                         kvm_release_pfn_clean(kvm->arch.guest_pmap[i]);
 151         }
 152         kfree(kvm->arch.guest_pmap);
 153
 154         kvm_for_each_vcpu(i, vcpu, kvm) {
 155                 kvm_arch_vcpu_free(vcpu);
 156         }
 157
 158         mutex_lock(&kvm->lock);
 159
 160         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
 161                 kvm->vcpus[i] = NULL;
 162
 163         atomic_set(&kvm->online_vcpus, 0);
 164
 165         mutex_unlock(&kvm->lock);
 166 }
 167
 168 static void kvm_mips_uninit_tlbs(void *arg)
 169 {
 170         /* Restore wired count */
 171         write_c0_wired(0);
 172         mtc0_tlbw_hazard();
 173         /* Clear out all the TLBs */
 174         kvm_local_flush_tlb_all();
 175 }
 176
 177 void kvm_arch_destroy_vm(struct kvm *kvm)
 178 {
 179         kvm_mips_free_vcpus(kvm);
 180
 181         /* If this is the last instance, restore wired count */
 182         if (atomic_dec_return(&kvm_mips_instance) == 0) {
 183                 kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
 184                           __func__);
 185                 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1);
 186         }
 187 }
 188
 189 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
 190                         unsigned long arg)
 191 {
 192         return -ENOIOCTLCMD;
 193 }
 194
 195 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
 196                             unsigned long npages)
 197 {
 198         return 0;
 199 }
 200
 201 int kvm_arch_prepare_memory_region(struct kvm *kvm,
 202                                    struct kvm_memory_slot *memslot,
 203                                    const struct kvm_userspace_memory_region *mem,
 204                                    enum kvm_mr_change change)
 205 {
 206         return 0;
 207 }
 208
 209 void kvm_arch_commit_memory_region(struct kvm *kvm,
 210                                    const struct kvm_userspace_memory_region *mem,
 211                                    const struct kvm_memory_slot *old,
 212                                    const struct kvm_memory_slot *new,
 213                                    enum kvm_mr_change change)
 214 {
 215         unsigned long npages = 0;
 216         int i;
 217
 218         kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
 219                   __func__, kvm, mem->slot, mem->guest_phys_addr,
 220                   mem->memory_size, mem->userspace_addr);
 221
 222         /* Setup Guest PMAP table */
 223         if (!kvm->arch.guest_pmap) {
 224                 if (mem->slot == 0)
 225                         npages = mem->memory_size >> PAGE_SHIFT;
 226
 227                 if (npages) {
 228                         kvm->arch.guest_pmap_npages = npages;
 229                         kvm->arch.guest_pmap =
 230                             kzalloc(npages * sizeof(unsigned long), GFP_KERNEL);
 231
 232                         if (!kvm->arch.guest_pmap) {
 233                                 kvm_err("Failed to allocate guest PMAP\n");
 234                                 return;
 235                         }
 236
 237                         kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
 238                                   npages, kvm->arch.guest_pmap);
 239
 240                         /* Now setup the page table */
 241                         for (i = 0; i < npages; i++)
 242                                 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE;
 243                 }
 244         }
 245 }
 246
 247 static inline void dump_handler(const char *symbol, void *start, void *end)
 248 {
 249         u32 *p;
 250
 251         pr_debug("LEAF(%s)\n", symbol);
 252
 253         pr_debug("\t.set push\n");
 254         pr_debug("\t.set noreorder\n");
 255
 256         for (p = start; p < (u32 *)end; ++p)
 257                 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
 258
 259         pr_debug("\t.set\tpop\n");
 260
 261         pr_debug("\tEND(%s)\n", symbol);
 262 }
 263
 264 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
 265 {
 266         int err, size;
 267         void *gebase, *p, *handler;
 268         int i;
 269
 270         struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
 271
 272         if (!vcpu) {
 273                 err = -ENOMEM;
 274                 goto out;
 275         }
 276
 277         err = kvm_vcpu_init(vcpu, kvm, id);
 278
 279         if (err)
 280                 goto out_free_cpu;
 281
 282         kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
 283
 284         /*
 285          * Allocate space for host mode exception handlers that handle
 286          * guest mode exits
 287          */
 288         if (cpu_has_veic || cpu_has_vint)
 289                 size = 0x200 + VECTORSPACING * 64;
 290         else
 291                 size = 0x4000;
 292
 293         gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
 294
 295         if (!gebase) {
 296                 err = -ENOMEM;
 297                 goto out_uninit_cpu;
 298         }
 299         kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
 300                   ALIGN(size, PAGE_SIZE), gebase);
 301
 302         /*
 303          * Check new ebase actually fits in CP0_EBase. The lack of a write gate
 304          * limits us to the low 512MB of physical address space. If the memory
 305          * we allocate is out of range, just give up now.
 306          */
 307         if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
 308                 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
 309                         gebase);
 310                 err = -ENOMEM;
 311                 goto out_free_gebase;
 312         }
 313
 314         /* Save new ebase */
 315         vcpu->arch.guest_ebase = gebase;
 316
 317         /* Build guest exception vectors dynamically in unmapped memory */
 318         handler = gebase + 0x2000;
 319
 320         /* TLB Refill, EXL = 0 */
 321         kvm_mips_build_exception(gebase, handler);
 322
 323         /* General Exception Entry point */
 324         kvm_mips_build_exception(gebase + 0x180, handler);
 325
 326         /* For vectored interrupts poke the exception code @ all offsets 0-7 */
 327         for (i = 0; i < 8; i++) {
 328                 kvm_debug("L1 Vectored handler @ %p\n",
 329                           gebase + 0x200 + (i * VECTORSPACING));
 330                 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
 331                                          handler);
 332         }
 333
 334         /* General exit handler */
 335         p = handler;
 336         p = kvm_mips_build_exit(p);
 337
 338         /* Guest entry routine */
 339         vcpu->arch.vcpu_run = p;
 340         p = kvm_mips_build_vcpu_run(p);
 341
 342         /* Dump the generated code */
 343         pr_debug("#include <asm/asm.h>\n");
 344         pr_debug("#include <asm/regdef.h>\n");
 345         pr_debug("\n");
 346         dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
 347         dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
 348         dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
 349
 350         /* Invalidate the icache for these ranges */
 351         flush_icache_range((unsigned long)gebase,
 352                            (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
 353
 354         /*
 355          * Allocate comm page for guest kernel, a TLB will be reserved for
 356          * mapping GVA @ 0xFFFF8000 to this page
 357          */
 358         vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
 359
 360         if (!vcpu->arch.kseg0_commpage) {
 361                 err = -ENOMEM;
 362                 goto out_free_gebase;
 363         }
 364
 365         kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
 366         kvm_mips_commpage_init(vcpu);
 367
 368         /* Init */
 369         vcpu->arch.last_sched_cpu = -1;
 370
 371         /* Start off the timer */
 372         kvm_mips_init_count(vcpu);
 373
 374         return vcpu;
 375
 376 out_free_gebase:
 377         kfree(gebase);
 378
 379 out_uninit_cpu:
 380         kvm_vcpu_uninit(vcpu);
 381
 382 out_free_cpu:
 383         kfree(vcpu);
 384
 385 out:
 386         return ERR_PTR(err);
 387 }
 388
 389 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
 390 {
 391         hrtimer_cancel(&vcpu->arch.comparecount_timer);
 392
 393         kvm_vcpu_uninit(vcpu);
 394
 395         kvm_mips_dump_stats(vcpu);
 396
 397         kfree(vcpu->arch.guest_ebase);
 398         kfree(vcpu->arch.kseg0_commpage);
 399         kfree(vcpu);
 400 }
 401
 402 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 403 {
 404         kvm_arch_vcpu_free(vcpu);
 405 }
 406
 407 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
 408                                         struct kvm_guest_debug *dbg)
 409 {
 410         return -ENOIOCTLCMD;
 411 }
 412
 413 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
 414 {
 415         int r = 0;
 416         sigset_t sigsaved;
 417
 418         if (vcpu->sigset_active)
 419                 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
 420
 421         if (vcpu->mmio_needed) {
 422                 if (!vcpu->mmio_is_write)
 423                         kvm_mips_complete_mmio_load(vcpu, run);
 424                 vcpu->mmio_needed = 0;
 425         }
 426
 427         lose_fpu(1);
 428
 429         local_irq_disable();
 430         guest_enter_irqoff();
 431         trace_kvm_enter(vcpu);
 432
 433         r = kvm_mips_callbacks->vcpu_run(run, vcpu);
 434
 435         trace_kvm_out(vcpu);
 436         guest_exit_irqoff();
 437         local_irq_enable();
 438
 439         if (vcpu->sigset_active)
 440                 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
 441
 442         return r;
 443 }
 444
 445 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
 446                              struct kvm_mips_interrupt *irq)
 447 {
 448         int intr = (int)irq->irq;
 449         struct kvm_vcpu *dvcpu = NULL;
 450
 451         if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
 452                 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
 453                           (int)intr);
 454
 455         if (irq->cpu == -1)
 456                 dvcpu = vcpu;
 457         else
 458                 dvcpu = vcpu->kvm->vcpus[irq->cpu];
 459
 460         if (intr == 2 || intr == 3 || intr == 4) {
 461                 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
 462
 463         } else if (intr == -2 || intr == -3 || intr == -4) {
 464                 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
 465         } else {
 466                 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
 467                         irq->cpu, irq->irq);
 468                 return -EINVAL;
 469         }
 470
 471         dvcpu->arch.wait = 0;
 472
 473         if (swait_active(&dvcpu->wq))
 474                 swake_up(&dvcpu->wq);
 475
 476         return 0;
 477 }
 478
 479 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
 480                                     struct kvm_mp_state *mp_state)
 481 {
 482         return -ENOIOCTLCMD;
 483 }
 484
 485 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
 486                                     struct kvm_mp_state *mp_state)
 487 {
 488         return -ENOIOCTLCMD;
 489 }
 490
 491 static u64 kvm_mips_get_one_regs[] = {
 492         KVM_REG_MIPS_R0,
 493         KVM_REG_MIPS_R1,
 494         KVM_REG_MIPS_R2,
 495         KVM_REG_MIPS_R3,
 496         KVM_REG_MIPS_R4,
 497         KVM_REG_MIPS_R5,
 498         KVM_REG_MIPS_R6,
 499         KVM_REG_MIPS_R7,
 500         KVM_REG_MIPS_R8,
 501         KVM_REG_MIPS_R9,
 502         KVM_REG_MIPS_R10,
 503         KVM_REG_MIPS_R11,
 504         KVM_REG_MIPS_R12,
 505         KVM_REG_MIPS_R13,
 506         KVM_REG_MIPS_R14,
 507         KVM_REG_MIPS_R15,
 508         KVM_REG_MIPS_R16,
 509         KVM_REG_MIPS_R17,
 510         KVM_REG_MIPS_R18,
 511         KVM_REG_MIPS_R19,
 512         KVM_REG_MIPS_R20,
 513         KVM_REG_MIPS_R21,
 514         KVM_REG_MIPS_R22,
 515         KVM_REG_MIPS_R23,
 516         KVM_REG_MIPS_R24,
 517         KVM_REG_MIPS_R25,
 518         KVM_REG_MIPS_R26,
 519         KVM_REG_MIPS_R27,
 520         KVM_REG_MIPS_R28,
 521         KVM_REG_MIPS_R29,
 522         KVM_REG_MIPS_R30,
 523         KVM_REG_MIPS_R31,
 524
 525 #ifndef CONFIG_CPU_MIPSR6
 526         KVM_REG_MIPS_HI,
 527         KVM_REG_MIPS_LO,
 528 #endif
 529         KVM_REG_MIPS_PC,
 530
 531         KVM_REG_MIPS_CP0_INDEX,
 532         KVM_REG_MIPS_CP0_CONTEXT,
 533         KVM_REG_MIPS_CP0_USERLOCAL,
 534         KVM_REG_MIPS_CP0_PAGEMASK,
 535         KVM_REG_MIPS_CP0_WIRED,
 536         KVM_REG_MIPS_CP0_HWRENA,
 537         KVM_REG_MIPS_CP0_BADVADDR,
 538         KVM_REG_MIPS_CP0_COUNT,
 539         KVM_REG_MIPS_CP0_ENTRYHI,
 540         KVM_REG_MIPS_CP0_COMPARE,
 541         KVM_REG_MIPS_CP0_STATUS,
 542         KVM_REG_MIPS_CP0_CAUSE,
 543         KVM_REG_MIPS_CP0_EPC,
 544         KVM_REG_MIPS_CP0_PRID,
 545         KVM_REG_MIPS_CP0_CONFIG,
 546         KVM_REG_MIPS_CP0_CONFIG1,
 547         KVM_REG_MIPS_CP0_CONFIG2,
 548         KVM_REG_MIPS_CP0_CONFIG3,
 549         KVM_REG_MIPS_CP0_CONFIG4,
 550         KVM_REG_MIPS_CP0_CONFIG5,
 551         KVM_REG_MIPS_CP0_CONFIG7,
 552         KVM_REG_MIPS_CP0_ERROREPC,
 553
 554         KVM_REG_MIPS_COUNT_CTL,
 555         KVM_REG_MIPS_COUNT_RESUME,
 556         KVM_REG_MIPS_COUNT_HZ,
 557 };
 558
 559 static u64 kvm_mips_get_one_regs_fpu[] = {
 560         KVM_REG_MIPS_FCR_IR,
 561         KVM_REG_MIPS_FCR_CSR,
 562 };
 563
 564 static u64 kvm_mips_get_one_regs_msa[] = {
 565         KVM_REG_MIPS_MSA_IR,
 566         KVM_REG_MIPS_MSA_CSR,
 567 };
 568
 569 static u64 kvm_mips_get_one_regs_kscratch[] = {
 570         KVM_REG_MIPS_CP0_KSCRATCH1,
 571         KVM_REG_MIPS_CP0_KSCRATCH2,
 572         KVM_REG_MIPS_CP0_KSCRATCH3,
 573         KVM_REG_MIPS_CP0_KSCRATCH4,
 574         KVM_REG_MIPS_CP0_KSCRATCH5,
 575         KVM_REG_MIPS_CP0_KSCRATCH6,
 576 };
 577
 578 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
 579 {
 580         unsigned long ret;
 581
 582         ret = ARRAY_SIZE(kvm_mips_get_one_regs);
 583         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 584                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
 585                 /* odd doubles */
 586                 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
 587                         ret += 16;
 588         }
 589         if (kvm_mips_guest_can_have_msa(&vcpu->arch))
 590                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
 591         ret += __arch_hweight8(vcpu->arch.kscratch_enabled);
 592         ret += kvm_mips_callbacks->num_regs(vcpu);
 593
 594         return ret;
 595 }
 596
 597 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
 598 {
 599         u64 index;
 600         unsigned int i;
 601
 602         if (copy_to_user(indices, kvm_mips_get_one_regs,
 603                          sizeof(kvm_mips_get_one_regs)))
 604                 return -EFAULT;
 605         indices += ARRAY_SIZE(kvm_mips_get_one_regs);
 606
 607         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 608                 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
 609                                  sizeof(kvm_mips_get_one_regs_fpu)))
 610                         return -EFAULT;
 611                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
 612
 613                 for (i = 0; i < 32; ++i) {
 614                         index = KVM_REG_MIPS_FPR_32(i);
 615                         if (copy_to_user(indices, &index, sizeof(index)))
 616                                 return -EFAULT;
 617                         ++indices;
 618
 619                         /* skip odd doubles if no F64 */
 620                         if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
 621                                 continue;
 622
 623                         index = KVM_REG_MIPS_FPR_64(i);
 624                         if (copy_to_user(indices, &index, sizeof(index)))
 625                                 return -EFAULT;
 626                         ++indices;
 627                 }
 628         }
 629
 630         if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
 631                 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
 632                                  sizeof(kvm_mips_get_one_regs_msa)))
 633                         return -EFAULT;
 634                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
 635
 636                 for (i = 0; i < 32; ++i) {
 637                         index = KVM_REG_MIPS_VEC_128(i);
 638                         if (copy_to_user(indices, &index, sizeof(index)))
 639                                 return -EFAULT;
 640                         ++indices;
 641                 }
 642         }
 643
 644         for (i = 0; i < 6; ++i) {
 645                 if (!(vcpu->arch.kscratch_enabled & BIT(i + 2)))
 646                         continue;
 647
 648                 if (copy_to_user(indices, &kvm_mips_get_one_regs_kscratch[i],
 649                                  sizeof(kvm_mips_get_one_regs_kscratch[i])))
 650                         return -EFAULT;
 651                 ++indices;
 652         }
 653
 654         return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
 655 }
 656
 657 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
 658                             const struct kvm_one_reg *reg)
 659 {
 660         struct mips_coproc *cop0 = vcpu->arch.cop0;
 661         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 662         int ret;
 663         s64 v;
 664         s64 vs[2];
 665         unsigned int idx;
 666
 667         switch (reg->id) {
 668         /* General purpose registers */
 669         case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
 670                 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
 671                 break;
 672 #ifndef CONFIG_CPU_MIPSR6
 673         case KVM_REG_MIPS_HI:
 674                 v = (long)vcpu->arch.hi;
 675                 break;
 676         case KVM_REG_MIPS_LO:
 677                 v = (long)vcpu->arch.lo;
 678                 break;
 679 #endif
 680         case KVM_REG_MIPS_PC:
 681                 v = (long)vcpu->arch.pc;
 682                 break;
 683
 684         /* Floating point registers */
 685         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 686                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 687                         return -EINVAL;
 688                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 689                 /* Odd singles in top of even double when FR=0 */
 690                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 691                         v = get_fpr32(&fpu->fpr[idx], 0);
 692                 else
 693                         v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
 694                 break;
 695         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 696                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 697                         return -EINVAL;
 698                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 699                 /* Can't access odd doubles in FR=0 mode */
 700                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 701                         return -EINVAL;
 702                 v = get_fpr64(&fpu->fpr[idx], 0);
 703                 break;
 704         case KVM_REG_MIPS_FCR_IR:
 705                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 706                         return -EINVAL;
 707                 v = boot_cpu_data.fpu_id;
 708                 break;
 709         case KVM_REG_MIPS_FCR_CSR:
 710                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 711                         return -EINVAL;
 712                 v = fpu->fcr31;
 713                 break;
 714
 715         /* MIPS SIMD Architecture (MSA) registers */
 716         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 717                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 718                         return -EINVAL;
 719                 /* Can't access MSA registers in FR=0 mode */
 720                 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
 721                         return -EINVAL;
 722                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 723 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 724                 /* least significant byte first */
 725                 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
 726                 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
 727 #else
 728                 /* most significant byte first */
 729                 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
 730                 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
 731 #endif
 732                 break;
 733         case KVM_REG_MIPS_MSA_IR:
 734                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 735                         return -EINVAL;
 736                 v = boot_cpu_data.msa_id;
 737                 break;
 738         case KVM_REG_MIPS_MSA_CSR:
 739                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 740                         return -EINVAL;
 741                 v = fpu->msacsr;
 742                 break;
 743
 744         /* Co-processor 0 registers */
 745         case KVM_REG_MIPS_CP0_INDEX:
 746                 v = (long)kvm_read_c0_guest_index(cop0);
 747                 break;
 748         case KVM_REG_MIPS_CP0_CONTEXT:
 749                 v = (long)kvm_read_c0_guest_context(cop0);
 750                 break;
 751         case KVM_REG_MIPS_CP0_USERLOCAL:
 752                 v = (long)kvm_read_c0_guest_userlocal(cop0);
 753                 break;
 754         case KVM_REG_MIPS_CP0_PAGEMASK:
 755                 v = (long)kvm_read_c0_guest_pagemask(cop0);
 756                 break;
 757         case KVM_REG_MIPS_CP0_WIRED:
 758                 v = (long)kvm_read_c0_guest_wired(cop0);
 759                 break;
 760         case KVM_REG_MIPS_CP0_HWRENA:
 761                 v = (long)kvm_read_c0_guest_hwrena(cop0);
 762                 break;
 763         case KVM_REG_MIPS_CP0_BADVADDR:
 764                 v = (long)kvm_read_c0_guest_badvaddr(cop0);
 765                 break;
 766         case KVM_REG_MIPS_CP0_ENTRYHI:
 767                 v = (long)kvm_read_c0_guest_entryhi(cop0);
 768                 break;
 769         case KVM_REG_MIPS_CP0_COMPARE:
 770                 v = (long)kvm_read_c0_guest_compare(cop0);
 771                 break;
 772         case KVM_REG_MIPS_CP0_STATUS:
 773                 v = (long)kvm_read_c0_guest_status(cop0);
 774                 break;
 775         case KVM_REG_MIPS_CP0_CAUSE:
 776                 v = (long)kvm_read_c0_guest_cause(cop0);
 777                 break;
 778         case KVM_REG_MIPS_CP0_EPC:
 779                 v = (long)kvm_read_c0_guest_epc(cop0);
 780                 break;
 781         case KVM_REG_MIPS_CP0_PRID:
 782                 v = (long)kvm_read_c0_guest_prid(cop0);
 783                 break;
 784         case KVM_REG_MIPS_CP0_CONFIG:
 785                 v = (long)kvm_read_c0_guest_config(cop0);
 786                 break;
 787         case KVM_REG_MIPS_CP0_CONFIG1:
 788                 v = (long)kvm_read_c0_guest_config1(cop0);
 789                 break;
 790         case KVM_REG_MIPS_CP0_CONFIG2:
 791                 v = (long)kvm_read_c0_guest_config2(cop0);
 792                 break;
 793         case KVM_REG_MIPS_CP0_CONFIG3:
 794                 v = (long)kvm_read_c0_guest_config3(cop0);
 795                 break;
 796         case KVM_REG_MIPS_CP0_CONFIG4:
 797                 v = (long)kvm_read_c0_guest_config4(cop0);
 798                 break;
 799         case KVM_REG_MIPS_CP0_CONFIG5:
 800                 v = (long)kvm_read_c0_guest_config5(cop0);
 801                 break;
 802         case KVM_REG_MIPS_CP0_CONFIG7:
 803                 v = (long)kvm_read_c0_guest_config7(cop0);
 804                 break;
 805         case KVM_REG_MIPS_CP0_ERROREPC:
 806                 v = (long)kvm_read_c0_guest_errorepc(cop0);
 807                 break;
 808         case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6:
 809                 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2;
 810                 if (!(vcpu->arch.kscratch_enabled & BIT(idx)))
 811                         return -EINVAL;
 812                 switch (idx) {
 813                 case 2:
 814                         v = (long)kvm_read_c0_guest_kscratch1(cop0);
 815                         break;
 816                 case 3:
 817                         v = (long)kvm_read_c0_guest_kscratch2(cop0);
 818                         break;
 819                 case 4:
 820                         v = (long)kvm_read_c0_guest_kscratch3(cop0);
 821                         break;
 822                 case 5:
 823                         v = (long)kvm_read_c0_guest_kscratch4(cop0);
 824                         break;
 825                 case 6:
 826                         v = (long)kvm_read_c0_guest_kscratch5(cop0);
 827                         break;
 828                 case 7:
 829                         v = (long)kvm_read_c0_guest_kscratch6(cop0);
 830                         break;
 831                 }
 832                 break;
 833         /* registers to be handled specially */
 834         default:
 835                 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
 836                 if (ret)
 837                         return ret;
 838                 break;
 839         }
 840         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 841                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 842
 843                 return put_user(v, uaddr64);
 844         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 845                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 846                 u32 v32 = (u32)v;
 847
 848                 return put_user(v32, uaddr32);
 849         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 850                 void __user *uaddr = (void __user *)(long)reg->addr;
 851
 852                 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
 853         } else {
 854                 return -EINVAL;
 855         }
 856 }
 857
 858 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
 859                             const struct kvm_one_reg *reg)
 860 {
 861         struct mips_coproc *cop0 = vcpu->arch.cop0;
 862         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 863         s64 v;
 864         s64 vs[2];
 865         unsigned int idx;
 866
 867         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 868                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 869
 870                 if (get_user(v, uaddr64) != 0)
 871                         return -EFAULT;
 872         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 873                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 874                 s32 v32;
 875
 876                 if (get_user(v32, uaddr32) != 0)
 877                         return -EFAULT;
 878                 v = (s64)v32;
 879         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 880                 void __user *uaddr = (void __user *)(long)reg->addr;
 881
 882                 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
 883         } else {
 884                 return -EINVAL;
 885         }
 886
 887         switch (reg->id) {
 888         /* General purpose registers */
 889         case KVM_REG_MIPS_R0:
 890                 /* Silently ignore requests to set $0 */
 891                 break;
 892         case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
 893                 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
 894                 break;
 895 #ifndef CONFIG_CPU_MIPSR6
 896         case KVM_REG_MIPS_HI:
 897                 vcpu->arch.hi = v;
 898                 break;
 899         case KVM_REG_MIPS_LO:
 900                 vcpu->arch.lo = v;
 901                 break;
 902 #endif
 903         case KVM_REG_MIPS_PC:
 904                 vcpu->arch.pc = v;
 905                 break;
 906
 907         /* Floating point registers */
 908         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 909                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 910                         return -EINVAL;
 911                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 912                 /* Odd singles in top of even double when FR=0 */
 913                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 914                         set_fpr32(&fpu->fpr[idx], 0, v);
 915                 else
 916                         set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
 917                 break;
 918         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 919                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 920                         return -EINVAL;
 921                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 922                 /* Can't access odd doubles in FR=0 mode */
 923                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 924                         return -EINVAL;
 925                 set_fpr64(&fpu->fpr[idx], 0, v);
 926                 break;
 927         case KVM_REG_MIPS_FCR_IR:
 928                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 929                         return -EINVAL;
 930                 /* Read-only */
 931                 break;
 932         case KVM_REG_MIPS_FCR_CSR:
 933                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 934                         return -EINVAL;
 935                 fpu->fcr31 = v;
 936                 break;
 937
 938         /* MIPS SIMD Architecture (MSA) registers */
 939         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 940                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 941                         return -EINVAL;
 942                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 943 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 944                 /* least significant byte first */
 945                 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
 946                 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
 947 #else
 948                 /* most significant byte first */
 949                 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
 950                 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
 951 #endif
 952                 break;
 953         case KVM_REG_MIPS_MSA_IR:
 954                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 955                         return -EINVAL;
 956                 /* Read-only */
 957                 break;
 958         case KVM_REG_MIPS_MSA_CSR:
 959                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 960                         return -EINVAL;
 961                 fpu->msacsr = v;
 962                 break;
 963
 964         /* Co-processor 0 registers */
 965         case KVM_REG_MIPS_CP0_INDEX:
 966                 kvm_write_c0_guest_index(cop0, v);
 967                 break;
 968         case KVM_REG_MIPS_CP0_CONTEXT:
 969                 kvm_write_c0_guest_context(cop0, v);
 970                 break;
 971         case KVM_REG_MIPS_CP0_USERLOCAL:
 972                 kvm_write_c0_guest_userlocal(cop0, v);
 973                 break;
 974         case KVM_REG_MIPS_CP0_PAGEMASK:
 975                 kvm_write_c0_guest_pagemask(cop0, v);
 976                 break;
 977         case KVM_REG_MIPS_CP0_WIRED:
 978                 kvm_write_c0_guest_wired(cop0, v);
 979                 break;
 980         case KVM_REG_MIPS_CP0_HWRENA:
 981                 kvm_write_c0_guest_hwrena(cop0, v);
 982                 break;
 983         case KVM_REG_MIPS_CP0_BADVADDR:
 984                 kvm_write_c0_guest_badvaddr(cop0, v);
 985                 break;
 986         case KVM_REG_MIPS_CP0_ENTRYHI:
 987                 kvm_write_c0_guest_entryhi(cop0, v);
 988                 break;
 989         case KVM_REG_MIPS_CP0_STATUS:
 990                 kvm_write_c0_guest_status(cop0, v);
 991                 break;
 992         case KVM_REG_MIPS_CP0_EPC:
 993                 kvm_write_c0_guest_epc(cop0, v);
 994                 break;
 995         case KVM_REG_MIPS_CP0_PRID:
 996                 kvm_write_c0_guest_prid(cop0, v);
 997                 break;
 998         case KVM_REG_MIPS_CP0_ERROREPC:
 999                 kvm_write_c0_guest_errorepc(cop0, v);
1000                 break;
1001         case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6:
1002                 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2;
1003                 if (!(vcpu->arch.kscratch_enabled & BIT(idx)))
1004                         return -EINVAL;
1005                 switch (idx) {
1006                 case 2:
1007                         kvm_write_c0_guest_kscratch1(cop0, v);
1008                         break;
1009                 case 3:
1010                         kvm_write_c0_guest_kscratch2(cop0, v);
1011                         break;
1012                 case 4:
1013                         kvm_write_c0_guest_kscratch3(cop0, v);
1014                         break;
1015                 case 5:
1016                         kvm_write_c0_guest_kscratch4(cop0, v);
1017                         break;
1018                 case 6:
1019                         kvm_write_c0_guest_kscratch5(cop0, v);
1020                         break;
1021                 case 7:
1022                         kvm_write_c0_guest_kscratch6(cop0, v);
1023                         break;
1024                 }
1025                 break;
1026         /* registers to be handled specially */
1027         default:
1028                 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
1029         }
1030         return 0;
1031 }
1032
1033 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
1034                                      struct kvm_enable_cap *cap)
1035 {
1036         int r = 0;
1037
1038         if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
1039                 return -EINVAL;
1040         if (cap->flags)
1041                 return -EINVAL;
1042         if (cap->args[0])
1043                 return -EINVAL;
1044
1045         switch (cap->cap) {
1046         case KVM_CAP_MIPS_FPU:
1047                 vcpu->arch.fpu_enabled = true;
1048                 break;
1049         case KVM_CAP_MIPS_MSA:
1050                 vcpu->arch.msa_enabled = true;
1051                 break;
1052         default:
1053                 r = -EINVAL;
1054                 break;
1055         }
1056
1057         return r;
1058 }
1059
1060 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
1061                          unsigned long arg)
1062 {
1063         struct kvm_vcpu *vcpu = filp->private_data;
1064         void __user *argp = (void __user *)arg;
1065         long r;
1066
1067         switch (ioctl) {
1068         case KVM_SET_ONE_REG:
1069         case KVM_GET_ONE_REG: {
1070                 struct kvm_one_reg reg;
1071
1072                 if (copy_from_user(&reg, argp, sizeof(reg)))
1073                         return -EFAULT;
1074                 if (ioctl == KVM_SET_ONE_REG)
1075                         return kvm_mips_set_reg(vcpu, &reg);
1076                 else
1077                         return kvm_mips_get_reg(vcpu, &reg);
1078         }
1079         case KVM_GET_REG_LIST: {
1080                 struct kvm_reg_list __user *user_list = argp;
1081                 struct kvm_reg_list reg_list;
1082                 unsigned n;
1083
1084                 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
1085                         return -EFAULT;
1086                 n = reg_list.n;
1087                 reg_list.n = kvm_mips_num_regs(vcpu);
1088                 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
1089                         return -EFAULT;
1090                 if (n < reg_list.n)
1091                         return -E2BIG;
1092                 return kvm_mips_copy_reg_indices(vcpu, user_list->reg);
1093         }
1094         case KVM_INTERRUPT:
1095                 {
1096                         struct kvm_mips_interrupt irq;
1097
1098                         if (copy_from_user(&irq, argp, sizeof(irq)))
1099                                 return -EFAULT;
1100                         kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
1101                                   irq.irq);
1102
1103                         r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1104                         break;
1105                 }
1106         case KVM_ENABLE_CAP: {
1107                 struct kvm_enable_cap cap;
1108
1109                 if (copy_from_user(&cap, argp, sizeof(cap)))
1110                         return -EFAULT;
1111                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
1112                 break;
1113         }
1114         default:
1115                 r = -ENOIOCTLCMD;
1116         }
1117         return r;
1118 }
1119
1120 /* Get (and clear) the dirty memory log for a memory slot. */
1121 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
1122 {
1123         struct kvm_memslots *slots;
1124         struct kvm_memory_slot *memslot;
1125         unsigned long ga, ga_end;
1126         int is_dirty = 0;
1127         int r;
1128         unsigned long n;
1129
1130         mutex_lock(&kvm->slots_lock);
1131
1132         r = kvm_get_dirty_log(kvm, log, &is_dirty);
1133         if (r)
1134                 goto out;
1135
1136         /* If nothing is dirty, don't bother messing with page tables. */
1137         if (is_dirty) {
1138                 slots = kvm_memslots(kvm);
1139                 memslot = id_to_memslot(slots, log->slot);
1140
1141                 ga = memslot->base_gfn << PAGE_SHIFT;
1142                 ga_end = ga + (memslot->npages << PAGE_SHIFT);
1143
1144                 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga,
1145                          ga_end);
1146
1147                 n = kvm_dirty_bitmap_bytes(memslot);
1148                 memset(memslot->dirty_bitmap, 0, n);
1149         }
1150
1151         r = 0;
1152 out:
1153         mutex_unlock(&kvm->slots_lock);
1154         return r;
1155
1156 }
1157
1158 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1159 {
1160         long r;
1161
1162         switch (ioctl) {
1163         default:
1164                 r = -ENOIOCTLCMD;
1165         }
1166
1167         return r;
1168 }
1169
1170 int kvm_arch_init(void *opaque)
1171 {
1172         if (kvm_mips_callbacks) {
1173                 kvm_err("kvm: module already exists\n");
1174                 return -EEXIST;
1175         }
1176
1177         return kvm_mips_emulation_init(&kvm_mips_callbacks);
1178 }
1179
1180 void kvm_arch_exit(void)
1181 {
1182         kvm_mips_callbacks = NULL;
1183 }
1184
1185 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1186                                   struct kvm_sregs *sregs)
1187 {
1188         return -ENOIOCTLCMD;
1189 }
1190
1191 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1192                                   struct kvm_sregs *sregs)
1193 {
1194         return -ENOIOCTLCMD;
1195 }
1196
1197 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1198 {
1199 }
1200
1201 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1202 {
1203         return -ENOIOCTLCMD;
1204 }
1205
1206 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1207 {
1208         return -ENOIOCTLCMD;
1209 }
1210
1211 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1212 {
1213         return VM_FAULT_SIGBUS;
1214 }
1215
1216 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1217 {
1218         int r;
1219
1220         switch (ext) {
1221         case KVM_CAP_ONE_REG:
1222         case KVM_CAP_ENABLE_CAP:
1223                 r = 1;
1224                 break;
1225         case KVM_CAP_COALESCED_MMIO:
1226                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1227                 break;
1228         case KVM_CAP_MIPS_FPU:
1229                 /* We don't handle systems with inconsistent cpu_has_fpu */
1230                 r = !!raw_cpu_has_fpu;
1231                 break;
1232         case KVM_CAP_MIPS_MSA:
1233                 /*
1234                  * We don't support MSA vector partitioning yet:
1235                  * 1) It would require explicit support which can't be tested
1236                  *    yet due to lack of support in current hardware.
1237                  * 2) It extends the state that would need to be saved/restored
1238                  *    by e.g. QEMU for migration.
1239                  *
1240                  * When vector partitioning hardware becomes available, support
1241                  * could be added by requiring a flag when enabling
1242                  * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1243                  * to save/restore the appropriate extra state.
1244                  */
1245                 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1246                 break;
1247         default:
1248                 r = 0;
1249                 break;
1250         }
1251         return r;
1252 }
1253
1254 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1255 {
1256         return kvm_mips_pending_timer(vcpu);
1257 }
1258
1259 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1260 {
1261         int i;
1262         struct mips_coproc *cop0;
1263
1264         if (!vcpu)
1265                 return -1;
1266
1267         kvm_debug("VCPU Register Dump:\n");
1268         kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1269         kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1270
1271         for (i = 0; i < 32; i += 4) {
1272                 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1273                        vcpu->arch.gprs[i],
1274                        vcpu->arch.gprs[i + 1],
1275                        vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1276         }
1277         kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1278         kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1279
1280         cop0 = vcpu->arch.cop0;
1281         kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1282                   kvm_read_c0_guest_status(cop0),
1283                   kvm_read_c0_guest_cause(cop0));
1284
1285         kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1286
1287         return 0;
1288 }
1289
1290 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1291 {
1292         int i;
1293
1294         for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1295                 vcpu->arch.gprs[i] = regs->gpr[i];
1296         vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1297         vcpu->arch.hi = regs->hi;
1298         vcpu->arch.lo = regs->lo;
1299         vcpu->arch.pc = regs->pc;
1300
1301         return 0;
1302 }
1303
1304 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1305 {
1306         int i;
1307
1308         for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1309                 regs->gpr[i] = vcpu->arch.gprs[i];
1310
1311         regs->hi = vcpu->arch.hi;
1312         regs->lo = vcpu->arch.lo;
1313         regs->pc = vcpu->arch.pc;
1314
1315         return 0;
1316 }
1317
1318 static void kvm_mips_comparecount_func(unsigned long data)
1319 {
1320         struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1321
1322         kvm_mips_callbacks->queue_timer_int(vcpu);
1323
1324         vcpu->arch.wait = 0;
1325         if (swait_active(&vcpu->wq))
1326                 swake_up(&vcpu->wq);
1327 }
1328
1329 /* low level hrtimer wake routine */
1330 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1331 {
1332         struct kvm_vcpu *vcpu;
1333
1334         vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1335         kvm_mips_comparecount_func((unsigned long) vcpu);
1336         return kvm_mips_count_timeout(vcpu);
1337 }
1338
1339 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1340 {
1341         kvm_mips_callbacks->vcpu_init(vcpu);
1342         hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1343                      HRTIMER_MODE_REL);
1344         vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1345         return 0;
1346 }
1347
1348 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1349                                   struct kvm_translation *tr)
1350 {
1351         return 0;
1352 }
1353
1354 /* Initial guest state */
1355 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1356 {
1357         return kvm_mips_callbacks->vcpu_setup(vcpu);
1358 }
1359
1360 static void kvm_mips_set_c0_status(void)
1361 {
1362         u32 status = read_c0_status();
1363
1364         if (cpu_has_dsp)
1365                 status |= (ST0_MX);
1366
1367         write_c0_status(status);
1368         ehb();
1369 }
1370
1371 /*
1372  * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1373  */
1374 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1375 {
1376         u32 cause = vcpu->arch.host_cp0_cause;
1377         u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1378         u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1379         unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1380         enum emulation_result er = EMULATE_DONE;
1381         int ret = RESUME_GUEST;
1382
1383         /* re-enable HTW before enabling interrupts */
1384         htw_start();
1385
1386         /* Set a default exit reason */
1387         run->exit_reason = KVM_EXIT_UNKNOWN;
1388         run->ready_for_interrupt_injection = 1;
1389
1390         /*
1391          * Set the appropriate status bits based on host CPU features,
1392          * before we hit the scheduler
1393          */
1394         kvm_mips_set_c0_status();
1395
1396         local_irq_enable();
1397
1398         kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1399                         cause, opc, run, vcpu);
1400         trace_kvm_exit(vcpu, exccode);
1401
1402         /*
1403          * Do a privilege check, if in UM most of these exit conditions end up
1404          * causing an exception to be delivered to the Guest Kernel
1405          */
1406         er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1407         if (er == EMULATE_PRIV_FAIL) {
1408                 goto skip_emul;
1409         } else if (er == EMULATE_FAIL) {
1410                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1411                 ret = RESUME_HOST;
1412                 goto skip_emul;
1413         }
1414
1415         switch (exccode) {
1416         case EXCCODE_INT:
1417                 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1418
1419                 ++vcpu->stat.int_exits;
1420
1421                 if (need_resched())
1422                         cond_resched();
1423
1424                 ret = RESUME_GUEST;
1425                 break;
1426
1427         case EXCCODE_CPU:
1428                 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1429
1430                 ++vcpu->stat.cop_unusable_exits;
1431                 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1432                 /* XXXKYMA: Might need to return to user space */
1433                 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1434                         ret = RESUME_HOST;
1435                 break;
1436
1437         case EXCCODE_MOD:
1438                 ++vcpu->stat.tlbmod_exits;
1439                 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1440                 break;
1441
1442         case EXCCODE_TLBS:
1443                 kvm_debug("TLB ST fault:  cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1444                           cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1445                           badvaddr);
1446
1447                 ++vcpu->stat.tlbmiss_st_exits;
1448                 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1449                 break;
1450
1451         case EXCCODE_TLBL:
1452                 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1453                           cause, opc, badvaddr);
1454
1455                 ++vcpu->stat.tlbmiss_ld_exits;
1456                 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1457                 break;
1458
1459         case EXCCODE_ADES:
1460                 ++vcpu->stat.addrerr_st_exits;
1461                 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1462                 break;
1463
1464         case EXCCODE_ADEL:
1465                 ++vcpu->stat.addrerr_ld_exits;
1466                 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1467                 break;
1468
1469         case EXCCODE_SYS:
1470                 ++vcpu->stat.syscall_exits;
1471                 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1472                 break;
1473
1474         case EXCCODE_RI:
1475                 ++vcpu->stat.resvd_inst_exits;
1476                 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1477                 break;
1478
1479         case EXCCODE_BP:
1480                 ++vcpu->stat.break_inst_exits;
1481                 ret = kvm_mips_callbacks->handle_break(vcpu);
1482                 break;
1483
1484         case EXCCODE_TR:
1485                 ++vcpu->stat.trap_inst_exits;
1486                 ret = kvm_mips_callbacks->handle_trap(vcpu);
1487                 break;
1488
1489         case EXCCODE_MSAFPE:
1490                 ++vcpu->stat.msa_fpe_exits;
1491                 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1492                 break;
1493
1494         case EXCCODE_FPE:
1495                 ++vcpu->stat.fpe_exits;
1496                 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1497                 break;
1498
1499         case EXCCODE_MSADIS:
1500                 ++vcpu->stat.msa_disabled_exits;
1501                 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1502                 break;
1503
1504         default:
1505                 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x  BadVaddr: %#lx Status: %#lx\n",
1506                         exccode, opc, kvm_get_inst(opc, vcpu), badvaddr,
1507                         kvm_read_c0_guest_status(vcpu->arch.cop0));
1508                 kvm_arch_vcpu_dump_regs(vcpu);
1509                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1510                 ret = RESUME_HOST;
1511                 break;
1512
1513         }
1514
1515 skip_emul:
1516         local_irq_disable();
1517
1518         if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1519                 kvm_mips_deliver_interrupts(vcpu, cause);
1520
1521         if (!(ret & RESUME_HOST)) {
1522                 /* Only check for signals if not already exiting to userspace */
1523                 if (signal_pending(current)) {
1524                         run->exit_reason = KVM_EXIT_INTR;
1525                         ret = (-EINTR << 2) | RESUME_HOST;
1526                         ++vcpu->stat.signal_exits;
1527                         trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1528                 }
1529         }
1530
1531         if (ret == RESUME_GUEST) {
1532                 trace_kvm_reenter(vcpu);
1533
1534                 kvm_mips_callbacks->vcpu_reenter(run, vcpu);
1535
1536                 /*
1537                  * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1538                  * is live), restore FCR31 / MSACSR.
1539                  *
1540                  * This should be before returning to the guest exception
1541                  * vector, as it may well cause an [MSA] FP exception if there
1542                  * are pending exception bits unmasked. (see
1543                  * kvm_mips_csr_die_notifier() for how that is handled).
1544                  */
1545                 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1546                     read_c0_status() & ST0_CU1)
1547                         __kvm_restore_fcsr(&vcpu->arch);
1548
1549                 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1550                     read_c0_config5() & MIPS_CONF5_MSAEN)
1551                         __kvm_restore_msacsr(&vcpu->arch);
1552         }
1553
1554         /* Disable HTW before returning to guest or host */
1555         htw_stop();
1556
1557         return ret;
1558 }
1559
1560 /* Enable FPU for guest and restore context */
1561 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1562 {
1563         struct mips_coproc *cop0 = vcpu->arch.cop0;
1564         unsigned int sr, cfg5;
1565
1566         preempt_disable();
1567
1568         sr = kvm_read_c0_guest_status(cop0);
1569
1570         /*
1571          * If MSA state is already live, it is undefined how it interacts with
1572          * FR=0 FPU state, and we don't want to hit reserved instruction
1573          * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1574          * play it safe and save it first.
1575          *
1576          * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1577          * get called when guest CU1 is set, however we can't trust the guest
1578          * not to clobber the status register directly via the commpage.
1579          */
1580         if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1581             vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1582                 kvm_lose_fpu(vcpu);
1583
1584         /*
1585          * Enable FPU for guest
1586          * We set FR and FRE according to guest context
1587          */
1588         change_c0_status(ST0_CU1 | ST0_FR, sr);
1589         if (cpu_has_fre) {
1590                 cfg5 = kvm_read_c0_guest_config5(cop0);
1591                 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1592         }
1593         enable_fpu_hazard();
1594
1595         /* If guest FPU state not active, restore it now */
1596         if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1597                 __kvm_restore_fpu(&vcpu->arch);
1598                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1599                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1600         } else {
1601                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1602         }
1603
1604         preempt_enable();
1605 }
1606
1607 #ifdef CONFIG_CPU_HAS_MSA
1608 /* Enable MSA for guest and restore context */
1609 void kvm_own_msa(struct kvm_vcpu *vcpu)
1610 {
1611         struct mips_coproc *cop0 = vcpu->arch.cop0;
1612         unsigned int sr, cfg5;
1613
1614         preempt_disable();
1615
1616         /*
1617          * Enable FPU if enabled in guest, since we're restoring FPU context
1618          * anyway. We set FR and FRE according to guest context.
1619          */
1620         if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1621                 sr = kvm_read_c0_guest_status(cop0);
1622
1623                 /*
1624                  * If FR=0 FPU state is already live, it is undefined how it
1625                  * interacts with MSA state, so play it safe and save it first.
1626                  */
1627                 if (!(sr & ST0_FR) &&
1628                     (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1629                                 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1630                         kvm_lose_fpu(vcpu);
1631
1632                 change_c0_status(ST0_CU1 | ST0_FR, sr);
1633                 if (sr & ST0_CU1 && cpu_has_fre) {
1634                         cfg5 = kvm_read_c0_guest_config5(cop0);
1635                         change_c0_config5(MIPS_CONF5_FRE, cfg5);
1636                 }
1637         }
1638
1639         /* Enable MSA for guest */
1640         set_c0_config5(MIPS_CONF5_MSAEN);
1641         enable_fpu_hazard();
1642
1643         switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1644         case KVM_MIPS_AUX_FPU:
1645                 /*
1646                  * Guest FPU state already loaded, only restore upper MSA state
1647                  */
1648                 __kvm_restore_msa_upper(&vcpu->arch);
1649                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1650                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1651                 break;
1652         case 0:
1653                 /* Neither FPU or MSA already active, restore full MSA state */
1654                 __kvm_restore_msa(&vcpu->arch);
1655                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1656                 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1657                         vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1658                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1659                               KVM_TRACE_AUX_FPU_MSA);
1660                 break;
1661         default:
1662                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1663                 break;
1664         }
1665
1666         preempt_enable();
1667 }
1668 #endif
1669
1670 /* Drop FPU & MSA without saving it */
1671 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1672 {
1673         preempt_disable();
1674         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1675                 disable_msa();
1676                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1677                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1678         }
1679         if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1680                 clear_c0_status(ST0_CU1 | ST0_FR);
1681                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1682                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1683         }
1684         preempt_enable();
1685 }
1686
1687 /* Save and disable FPU & MSA */
1688 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1689 {
1690         /*
1691          * FPU & MSA get disabled in root context (hardware) when it is disabled
1692          * in guest context (software), but the register state in the hardware
1693          * may still be in use. This is why we explicitly re-enable the hardware
1694          * before saving.
1695          */
1696
1697         preempt_disable();
1698         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1699                 set_c0_config5(MIPS_CONF5_MSAEN);
1700                 enable_fpu_hazard();
1701
1702                 __kvm_save_msa(&vcpu->arch);
1703                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1704
1705                 /* Disable MSA & FPU */
1706                 disable_msa();
1707                 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1708                         clear_c0_status(ST0_CU1 | ST0_FR);
1709                         disable_fpu_hazard();
1710                 }
1711                 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1712         } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1713                 set_c0_status(ST0_CU1);
1714                 enable_fpu_hazard();
1715
1716                 __kvm_save_fpu(&vcpu->arch);
1717                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1718                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1719
1720                 /* Disable FPU */
1721                 clear_c0_status(ST0_CU1 | ST0_FR);
1722                 disable_fpu_hazard();
1723         }
1724         preempt_enable();
1725 }
1726
1727 /*
1728  * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1729  * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1730  * exception if cause bits are set in the value being written.
1731  */
1732 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1733                                    unsigned long cmd, void *ptr)
1734 {
1735         struct die_args *args = (struct die_args *)ptr;
1736         struct pt_regs *regs = args->regs;
1737         unsigned long pc;
1738
1739         /* Only interested in FPE and MSAFPE */
1740         if (cmd != DIE_FP && cmd != DIE_MSAFP)
1741                 return NOTIFY_DONE;
1742
1743         /* Return immediately if guest context isn't active */
1744         if (!(current->flags & PF_VCPU))
1745                 return NOTIFY_DONE;
1746
1747         /* Should never get here from user mode */
1748         BUG_ON(user_mode(regs));
1749
1750         pc = instruction_pointer(regs);
1751         switch (cmd) {
1752         case DIE_FP:
1753                 /* match 2nd instruction in __kvm_restore_fcsr */
1754                 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1755                         return NOTIFY_DONE;
1756                 break;
1757         case DIE_MSAFP:
1758                 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1759                 if (!cpu_has_msa ||
1760                     pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1761                     pc > (unsigned long)&__kvm_restore_msacsr + 8)
1762                         return NOTIFY_DONE;
1763                 break;
1764         }
1765
1766         /* Move PC forward a little and continue executing */
1767         instruction_pointer(regs) += 4;
1768
1769         return NOTIFY_STOP;
1770 }
1771
1772 static struct notifier_block kvm_mips_csr_die_notifier = {
1773         .notifier_call = kvm_mips_csr_die_notify,
1774 };
1775
1776 static int __init kvm_mips_init(void)
1777 {
1778         int ret;
1779
1780         ret = kvm_mips_entry_setup();
1781         if (ret)
1782                 return ret;
1783
1784         ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1785
1786         if (ret)
1787                 return ret;
1788
1789         register_die_notifier(&kvm_mips_csr_die_notifier);
1790
1791         return 0;
1792 }
1793
1794 static void __exit kvm_mips_exit(void)
1795 {
1796         kvm_exit();
1797
1798         unregister_die_notifier(&kvm_mips_csr_die_notifier);
1799 }
1800
1801 module_init(kvm_mips_init);
1802 module_exit(kvm_mips_exit);
1803
1804 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);