2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * KVM/MIPS: MIPS specific KVM APIs
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
12 #include <linux/bitops.h>
13 #include <linux/errno.h>
14 #include <linux/err.h>
15 #include <linux/kdebug.h>
16 #include <linux/module.h>
17 #include <linux/uaccess.h>
18 #include <linux/vmalloc.h>
19 #include <linux/sched/signal.h>
21 #include <linux/bootmem.h>
25 #include <asm/cacheflush.h>
26 #include <asm/mmu_context.h>
27 #include <asm/pgalloc.h>
28 #include <asm/pgtable.h>
30 #include <linux/kvm_host.h>
32 #include "interrupt.h"
35 #define CREATE_TRACE_POINTS
39 #define VECTORSPACING 0x100 /* for EI/VI mode */
42 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
43 struct kvm_stats_debugfs_item debugfs_entries[] = {
44 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU },
45 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
46 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
47 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
48 { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
49 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
50 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
51 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
52 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU },
53 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU },
54 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU },
55 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU },
56 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU },
57 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU },
58 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU },
59 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU },
60 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
61 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
62 #ifdef CONFIG_KVM_MIPS_VZ
63 { "vz_gpsi", VCPU_STAT(vz_gpsi_exits), KVM_STAT_VCPU },
64 { "vz_gsfc", VCPU_STAT(vz_gsfc_exits), KVM_STAT_VCPU },
65 { "vz_hc", VCPU_STAT(vz_hc_exits), KVM_STAT_VCPU },
66 { "vz_grr", VCPU_STAT(vz_grr_exits), KVM_STAT_VCPU },
67 { "vz_gva", VCPU_STAT(vz_gva_exits), KVM_STAT_VCPU },
68 { "vz_ghfc", VCPU_STAT(vz_ghfc_exits), KVM_STAT_VCPU },
69 { "vz_gpa", VCPU_STAT(vz_gpa_exits), KVM_STAT_VCPU },
70 { "vz_resvd", VCPU_STAT(vz_resvd_exits), KVM_STAT_VCPU },
72 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
73 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
74 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
75 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU },
79 bool kvm_trace_guest_mode_change;
81 int kvm_guest_mode_change_trace_reg(void)
83 kvm_trace_guest_mode_change = 1;
87 void kvm_guest_mode_change_trace_unreg(void)
89 kvm_trace_guest_mode_change = 0;
93 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
94 * Config7, so we are "runnable" if interrupts are pending
96 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
98 return !!(vcpu->arch.pending_exceptions);
101 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
106 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
111 int kvm_arch_hardware_enable(void)
113 return kvm_mips_callbacks->hardware_enable();
116 void kvm_arch_hardware_disable(void)
118 kvm_mips_callbacks->hardware_disable();
121 int kvm_arch_hardware_setup(void)
126 void kvm_arch_check_processor_compat(void *rtn)
131 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
134 #ifdef CONFIG_KVM_MIPS_VZ
141 /* Unsupported KVM type */
145 /* Allocate page table to map GPA -> RPA */
146 kvm->arch.gpa_mm.pgd = kvm_pgd_alloc();
147 if (!kvm->arch.gpa_mm.pgd)
153 bool kvm_arch_has_vcpu_debugfs(void)
158 int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu)
163 void kvm_mips_free_vcpus(struct kvm *kvm)
166 struct kvm_vcpu *vcpu;
168 kvm_for_each_vcpu(i, vcpu, kvm) {
169 kvm_arch_vcpu_free(vcpu);
172 mutex_lock(&kvm->lock);
174 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
175 kvm->vcpus[i] = NULL;
177 atomic_set(&kvm->online_vcpus, 0);
179 mutex_unlock(&kvm->lock);
182 static void kvm_mips_free_gpa_pt(struct kvm *kvm)
184 /* It should always be safe to remove after flushing the whole range */
185 WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0));
186 pgd_free(NULL, kvm->arch.gpa_mm.pgd);
189 void kvm_arch_destroy_vm(struct kvm *kvm)
191 kvm_mips_free_vcpus(kvm);
192 kvm_mips_free_gpa_pt(kvm);
195 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
201 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
202 unsigned long npages)
207 void kvm_arch_flush_shadow_all(struct kvm *kvm)
209 /* Flush whole GPA */
210 kvm_mips_flush_gpa_pt(kvm, 0, ~0);
212 /* Let implementation do the rest */
213 kvm_mips_callbacks->flush_shadow_all(kvm);
216 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
217 struct kvm_memory_slot *slot)
220 * The slot has been made invalid (ready for moving or deletion), so we
221 * need to ensure that it can no longer be accessed by any guest VCPUs.
224 spin_lock(&kvm->mmu_lock);
225 /* Flush slot from GPA */
226 kvm_mips_flush_gpa_pt(kvm, slot->base_gfn,
227 slot->base_gfn + slot->npages - 1);
228 /* Let implementation do the rest */
229 kvm_mips_callbacks->flush_shadow_memslot(kvm, slot);
230 spin_unlock(&kvm->mmu_lock);
233 int kvm_arch_prepare_memory_region(struct kvm *kvm,
234 struct kvm_memory_slot *memslot,
235 const struct kvm_userspace_memory_region *mem,
236 enum kvm_mr_change change)
241 void kvm_arch_commit_memory_region(struct kvm *kvm,
242 const struct kvm_userspace_memory_region *mem,
243 const struct kvm_memory_slot *old,
244 const struct kvm_memory_slot *new,
245 enum kvm_mr_change change)
249 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
250 __func__, kvm, mem->slot, mem->guest_phys_addr,
251 mem->memory_size, mem->userspace_addr);
254 * If dirty page logging is enabled, write protect all pages in the slot
255 * ready for dirty logging.
257 * There is no need to do this in any of the following cases:
258 * CREATE: No dirty mappings will already exist.
259 * MOVE/DELETE: The old mappings will already have been cleaned up by
260 * kvm_arch_flush_shadow_memslot()
262 if (change == KVM_MR_FLAGS_ONLY &&
263 (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
264 new->flags & KVM_MEM_LOG_DIRTY_PAGES)) {
265 spin_lock(&kvm->mmu_lock);
266 /* Write protect GPA page table entries */
267 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn,
268 new->base_gfn + new->npages - 1);
269 /* Let implementation do the rest */
271 kvm_mips_callbacks->flush_shadow_memslot(kvm, new);
272 spin_unlock(&kvm->mmu_lock);
276 static inline void dump_handler(const char *symbol, void *start, void *end)
280 pr_debug("LEAF(%s)\n", symbol);
282 pr_debug("\t.set push\n");
283 pr_debug("\t.set noreorder\n");
285 for (p = start; p < (u32 *)end; ++p)
286 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
288 pr_debug("\t.set\tpop\n");
290 pr_debug("\tEND(%s)\n", symbol);
293 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
296 void *gebase, *p, *handler, *refill_start, *refill_end;
299 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
306 err = kvm_vcpu_init(vcpu, kvm, id);
311 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
314 * Allocate space for host mode exception handlers that handle
317 if (cpu_has_veic || cpu_has_vint)
318 size = 0x200 + VECTORSPACING * 64;
322 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
328 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
329 ALIGN(size, PAGE_SIZE), gebase);
332 * Check new ebase actually fits in CP0_EBase. The lack of a write gate
333 * limits us to the low 512MB of physical address space. If the memory
334 * we allocate is out of range, just give up now.
336 if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
337 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
340 goto out_free_gebase;
344 vcpu->arch.guest_ebase = gebase;
346 /* Build guest exception vectors dynamically in unmapped memory */
347 handler = gebase + 0x2000;
349 /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */
350 refill_start = gebase;
351 if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && IS_ENABLED(CONFIG_64BIT))
352 refill_start += 0x080;
353 refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler);
355 /* General Exception Entry point */
356 kvm_mips_build_exception(gebase + 0x180, handler);
358 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
359 for (i = 0; i < 8; i++) {
360 kvm_debug("L1 Vectored handler @ %p\n",
361 gebase + 0x200 + (i * VECTORSPACING));
362 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
366 /* General exit handler */
368 p = kvm_mips_build_exit(p);
370 /* Guest entry routine */
371 vcpu->arch.vcpu_run = p;
372 p = kvm_mips_build_vcpu_run(p);
374 /* Dump the generated code */
375 pr_debug("#include <asm/asm.h>\n");
376 pr_debug("#include <asm/regdef.h>\n");
378 dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
379 dump_handler("kvm_tlb_refill", refill_start, refill_end);
380 dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
381 dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
383 /* Invalidate the icache for these ranges */
384 flush_icache_range((unsigned long)gebase,
385 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
388 * Allocate comm page for guest kernel, a TLB will be reserved for
389 * mapping GVA @ 0xFFFF8000 to this page
391 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
393 if (!vcpu->arch.kseg0_commpage) {
395 goto out_free_gebase;
398 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
399 kvm_mips_commpage_init(vcpu);
402 vcpu->arch.last_sched_cpu = -1;
403 vcpu->arch.last_exec_cpu = -1;
411 kvm_vcpu_uninit(vcpu);
420 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
422 hrtimer_cancel(&vcpu->arch.comparecount_timer);
424 kvm_vcpu_uninit(vcpu);
426 kvm_mips_dump_stats(vcpu);
428 kvm_mmu_free_memory_caches(vcpu);
429 kfree(vcpu->arch.guest_ebase);
430 kfree(vcpu->arch.kseg0_commpage);
434 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
436 kvm_arch_vcpu_free(vcpu);
439 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
440 struct kvm_guest_debug *dbg)
445 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
451 kvm_sigset_activate(vcpu);
453 if (vcpu->mmio_needed) {
454 if (!vcpu->mmio_is_write)
455 kvm_mips_complete_mmio_load(vcpu, run);
456 vcpu->mmio_needed = 0;
459 if (run->immediate_exit)
465 guest_enter_irqoff();
466 trace_kvm_enter(vcpu);
469 * Make sure the read of VCPU requests in vcpu_run() callback is not
470 * reordered ahead of the write to vcpu->mode, or we could miss a TLB
471 * flush request while the requester sees the VCPU as outside of guest
472 * mode and not needing an IPI.
474 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
476 r = kvm_mips_callbacks->vcpu_run(run, vcpu);
483 kvm_sigset_deactivate(vcpu);
489 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
490 struct kvm_mips_interrupt *irq)
492 int intr = (int)irq->irq;
493 struct kvm_vcpu *dvcpu = NULL;
495 if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
496 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
502 dvcpu = vcpu->kvm->vcpus[irq->cpu];
504 if (intr == 2 || intr == 3 || intr == 4) {
505 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
507 } else if (intr == -2 || intr == -3 || intr == -4) {
508 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
510 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
515 dvcpu->arch.wait = 0;
517 if (swq_has_sleeper(&dvcpu->wq))
518 swake_up(&dvcpu->wq);
523 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
524 struct kvm_mp_state *mp_state)
529 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
530 struct kvm_mp_state *mp_state)
535 static u64 kvm_mips_get_one_regs[] = {
569 #ifndef CONFIG_CPU_MIPSR6
576 static u64 kvm_mips_get_one_regs_fpu[] = {
578 KVM_REG_MIPS_FCR_CSR,
581 static u64 kvm_mips_get_one_regs_msa[] = {
583 KVM_REG_MIPS_MSA_CSR,
586 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
590 ret = ARRAY_SIZE(kvm_mips_get_one_regs);
591 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
592 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
594 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
597 if (kvm_mips_guest_can_have_msa(&vcpu->arch))
598 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
599 ret += kvm_mips_callbacks->num_regs(vcpu);
604 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
609 if (copy_to_user(indices, kvm_mips_get_one_regs,
610 sizeof(kvm_mips_get_one_regs)))
612 indices += ARRAY_SIZE(kvm_mips_get_one_regs);
614 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
615 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
616 sizeof(kvm_mips_get_one_regs_fpu)))
618 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
620 for (i = 0; i < 32; ++i) {
621 index = KVM_REG_MIPS_FPR_32(i);
622 if (copy_to_user(indices, &index, sizeof(index)))
626 /* skip odd doubles if no F64 */
627 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
630 index = KVM_REG_MIPS_FPR_64(i);
631 if (copy_to_user(indices, &index, sizeof(index)))
637 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
638 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
639 sizeof(kvm_mips_get_one_regs_msa)))
641 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
643 for (i = 0; i < 32; ++i) {
644 index = KVM_REG_MIPS_VEC_128(i);
645 if (copy_to_user(indices, &index, sizeof(index)))
651 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
654 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
655 const struct kvm_one_reg *reg)
657 struct mips_coproc *cop0 = vcpu->arch.cop0;
658 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
665 /* General purpose registers */
666 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
667 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
669 #ifndef CONFIG_CPU_MIPSR6
670 case KVM_REG_MIPS_HI:
671 v = (long)vcpu->arch.hi;
673 case KVM_REG_MIPS_LO:
674 v = (long)vcpu->arch.lo;
677 case KVM_REG_MIPS_PC:
678 v = (long)vcpu->arch.pc;
681 /* Floating point registers */
682 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
683 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
685 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
686 /* Odd singles in top of even double when FR=0 */
687 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
688 v = get_fpr32(&fpu->fpr[idx], 0);
690 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
692 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
693 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
695 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
696 /* Can't access odd doubles in FR=0 mode */
697 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
699 v = get_fpr64(&fpu->fpr[idx], 0);
701 case KVM_REG_MIPS_FCR_IR:
702 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
704 v = boot_cpu_data.fpu_id;
706 case KVM_REG_MIPS_FCR_CSR:
707 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
712 /* MIPS SIMD Architecture (MSA) registers */
713 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
714 if (!kvm_mips_guest_has_msa(&vcpu->arch))
716 /* Can't access MSA registers in FR=0 mode */
717 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
719 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
720 #ifdef CONFIG_CPU_LITTLE_ENDIAN
721 /* least significant byte first */
722 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
723 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
725 /* most significant byte first */
726 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
727 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
730 case KVM_REG_MIPS_MSA_IR:
731 if (!kvm_mips_guest_has_msa(&vcpu->arch))
733 v = boot_cpu_data.msa_id;
735 case KVM_REG_MIPS_MSA_CSR:
736 if (!kvm_mips_guest_has_msa(&vcpu->arch))
741 /* registers to be handled specially */
743 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
748 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
749 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
751 return put_user(v, uaddr64);
752 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
753 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
756 return put_user(v32, uaddr32);
757 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
758 void __user *uaddr = (void __user *)(long)reg->addr;
760 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
766 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
767 const struct kvm_one_reg *reg)
769 struct mips_coproc *cop0 = vcpu->arch.cop0;
770 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
775 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
776 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
778 if (get_user(v, uaddr64) != 0)
780 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
781 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
784 if (get_user(v32, uaddr32) != 0)
787 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
788 void __user *uaddr = (void __user *)(long)reg->addr;
790 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
796 /* General purpose registers */
797 case KVM_REG_MIPS_R0:
798 /* Silently ignore requests to set $0 */
800 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
801 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
803 #ifndef CONFIG_CPU_MIPSR6
804 case KVM_REG_MIPS_HI:
807 case KVM_REG_MIPS_LO:
811 case KVM_REG_MIPS_PC:
815 /* Floating point registers */
816 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
817 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
819 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
820 /* Odd singles in top of even double when FR=0 */
821 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
822 set_fpr32(&fpu->fpr[idx], 0, v);
824 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
826 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
827 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
829 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
830 /* Can't access odd doubles in FR=0 mode */
831 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
833 set_fpr64(&fpu->fpr[idx], 0, v);
835 case KVM_REG_MIPS_FCR_IR:
836 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
840 case KVM_REG_MIPS_FCR_CSR:
841 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
846 /* MIPS SIMD Architecture (MSA) registers */
847 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
848 if (!kvm_mips_guest_has_msa(&vcpu->arch))
850 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
851 #ifdef CONFIG_CPU_LITTLE_ENDIAN
852 /* least significant byte first */
853 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
854 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
856 /* most significant byte first */
857 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
858 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
861 case KVM_REG_MIPS_MSA_IR:
862 if (!kvm_mips_guest_has_msa(&vcpu->arch))
866 case KVM_REG_MIPS_MSA_CSR:
867 if (!kvm_mips_guest_has_msa(&vcpu->arch))
872 /* registers to be handled specially */
874 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
879 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
880 struct kvm_enable_cap *cap)
884 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
892 case KVM_CAP_MIPS_FPU:
893 vcpu->arch.fpu_enabled = true;
895 case KVM_CAP_MIPS_MSA:
896 vcpu->arch.msa_enabled = true;
906 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
909 struct kvm_vcpu *vcpu = filp->private_data;
910 void __user *argp = (void __user *)arg;
913 if (ioctl == KVM_INTERRUPT) {
914 struct kvm_mips_interrupt irq;
916 if (copy_from_user(&irq, argp, sizeof(irq)))
918 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
921 return kvm_vcpu_ioctl_interrupt(vcpu, &irq);
927 case KVM_SET_ONE_REG:
928 case KVM_GET_ONE_REG: {
929 struct kvm_one_reg reg;
932 if (copy_from_user(®, argp, sizeof(reg)))
934 if (ioctl == KVM_SET_ONE_REG)
935 r = kvm_mips_set_reg(vcpu, ®);
937 r = kvm_mips_get_reg(vcpu, ®);
940 case KVM_GET_REG_LIST: {
941 struct kvm_reg_list __user *user_list = argp;
942 struct kvm_reg_list reg_list;
946 if (copy_from_user(®_list, user_list, sizeof(reg_list)))
949 reg_list.n = kvm_mips_num_regs(vcpu);
950 if (copy_to_user(user_list, ®_list, sizeof(reg_list)))
955 r = kvm_mips_copy_reg_indices(vcpu, user_list->reg);
958 case KVM_ENABLE_CAP: {
959 struct kvm_enable_cap cap;
962 if (copy_from_user(&cap, argp, sizeof(cap)))
964 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
976 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
978 * @log: slot id and address to which we copy the log
980 * Steps 1-4 below provide general overview of dirty page logging. See
981 * kvm_get_dirty_log_protect() function description for additional details.
983 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
984 * always flush the TLB (step 4) even if previous step failed and the dirty
985 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
986 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
987 * writes will be marked dirty for next log read.
989 * 1. Take a snapshot of the bit and clear it if needed.
990 * 2. Write protect the corresponding page.
991 * 3. Copy the snapshot to the userspace.
992 * 4. Flush TLB's if needed.
994 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
996 struct kvm_memslots *slots;
997 struct kvm_memory_slot *memslot;
998 bool is_dirty = false;
1001 mutex_lock(&kvm->slots_lock);
1003 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
1006 slots = kvm_memslots(kvm);
1007 memslot = id_to_memslot(slots, log->slot);
1009 /* Let implementation handle TLB/GVA invalidation */
1010 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot);
1013 mutex_unlock(&kvm->slots_lock);
1017 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1029 int kvm_arch_init(void *opaque)
1031 if (kvm_mips_callbacks) {
1032 kvm_err("kvm: module already exists\n");
1036 return kvm_mips_emulation_init(&kvm_mips_callbacks);
1039 void kvm_arch_exit(void)
1041 kvm_mips_callbacks = NULL;
1044 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1045 struct kvm_sregs *sregs)
1047 return -ENOIOCTLCMD;
1050 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1051 struct kvm_sregs *sregs)
1053 return -ENOIOCTLCMD;
1056 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1060 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1062 return -ENOIOCTLCMD;
1065 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1067 return -ENOIOCTLCMD;
1070 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1072 return VM_FAULT_SIGBUS;
1075 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1080 case KVM_CAP_ONE_REG:
1081 case KVM_CAP_ENABLE_CAP:
1082 case KVM_CAP_READONLY_MEM:
1083 case KVM_CAP_SYNC_MMU:
1084 case KVM_CAP_IMMEDIATE_EXIT:
1087 case KVM_CAP_NR_VCPUS:
1088 r = num_online_cpus();
1090 case KVM_CAP_MAX_VCPUS:
1093 case KVM_CAP_MIPS_FPU:
1094 /* We don't handle systems with inconsistent cpu_has_fpu */
1095 r = !!raw_cpu_has_fpu;
1097 case KVM_CAP_MIPS_MSA:
1099 * We don't support MSA vector partitioning yet:
1100 * 1) It would require explicit support which can't be tested
1101 * yet due to lack of support in current hardware.
1102 * 2) It extends the state that would need to be saved/restored
1103 * by e.g. QEMU for migration.
1105 * When vector partitioning hardware becomes available, support
1106 * could be added by requiring a flag when enabling
1107 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1108 * to save/restore the appropriate extra state.
1110 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1113 r = kvm_mips_callbacks->check_extension(kvm, ext);
1119 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1121 return kvm_mips_pending_timer(vcpu) ||
1122 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI;
1125 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1128 struct mips_coproc *cop0;
1133 kvm_debug("VCPU Register Dump:\n");
1134 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1135 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1137 for (i = 0; i < 32; i += 4) {
1138 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1140 vcpu->arch.gprs[i + 1],
1141 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1143 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1144 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1146 cop0 = vcpu->arch.cop0;
1147 kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n",
1148 kvm_read_c0_guest_status(cop0),
1149 kvm_read_c0_guest_cause(cop0));
1151 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1156 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1162 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1163 vcpu->arch.gprs[i] = regs->gpr[i];
1164 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1165 vcpu->arch.hi = regs->hi;
1166 vcpu->arch.lo = regs->lo;
1167 vcpu->arch.pc = regs->pc;
1173 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1179 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1180 regs->gpr[i] = vcpu->arch.gprs[i];
1182 regs->hi = vcpu->arch.hi;
1183 regs->lo = vcpu->arch.lo;
1184 regs->pc = vcpu->arch.pc;
1190 static void kvm_mips_comparecount_func(unsigned long data)
1192 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1194 kvm_mips_callbacks->queue_timer_int(vcpu);
1196 vcpu->arch.wait = 0;
1197 if (swq_has_sleeper(&vcpu->wq))
1198 swake_up(&vcpu->wq);
1201 /* low level hrtimer wake routine */
1202 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1204 struct kvm_vcpu *vcpu;
1206 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1207 kvm_mips_comparecount_func((unsigned long) vcpu);
1208 return kvm_mips_count_timeout(vcpu);
1211 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1215 err = kvm_mips_callbacks->vcpu_init(vcpu);
1219 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1221 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1225 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
1227 kvm_mips_callbacks->vcpu_uninit(vcpu);
1230 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1231 struct kvm_translation *tr)
1236 /* Initial guest state */
1237 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1239 return kvm_mips_callbacks->vcpu_setup(vcpu);
1242 static void kvm_mips_set_c0_status(void)
1244 u32 status = read_c0_status();
1249 write_c0_status(status);
1254 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1256 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1258 u32 cause = vcpu->arch.host_cp0_cause;
1259 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1260 u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1261 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1262 enum emulation_result er = EMULATE_DONE;
1264 int ret = RESUME_GUEST;
1266 vcpu->mode = OUTSIDE_GUEST_MODE;
1268 /* re-enable HTW before enabling interrupts */
1269 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1272 /* Set a default exit reason */
1273 run->exit_reason = KVM_EXIT_UNKNOWN;
1274 run->ready_for_interrupt_injection = 1;
1277 * Set the appropriate status bits based on host CPU features,
1278 * before we hit the scheduler
1280 kvm_mips_set_c0_status();
1284 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1285 cause, opc, run, vcpu);
1286 trace_kvm_exit(vcpu, exccode);
1288 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1290 * Do a privilege check, if in UM most of these exit conditions
1291 * end up causing an exception to be delivered to the Guest
1294 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1295 if (er == EMULATE_PRIV_FAIL) {
1297 } else if (er == EMULATE_FAIL) {
1298 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1306 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1308 ++vcpu->stat.int_exits;
1317 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1319 ++vcpu->stat.cop_unusable_exits;
1320 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1321 /* XXXKYMA: Might need to return to user space */
1322 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1327 ++vcpu->stat.tlbmod_exits;
1328 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1332 kvm_debug("TLB ST fault: cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n",
1333 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1336 ++vcpu->stat.tlbmiss_st_exits;
1337 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1341 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1342 cause, opc, badvaddr);
1344 ++vcpu->stat.tlbmiss_ld_exits;
1345 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1349 ++vcpu->stat.addrerr_st_exits;
1350 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1354 ++vcpu->stat.addrerr_ld_exits;
1355 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1359 ++vcpu->stat.syscall_exits;
1360 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1364 ++vcpu->stat.resvd_inst_exits;
1365 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1369 ++vcpu->stat.break_inst_exits;
1370 ret = kvm_mips_callbacks->handle_break(vcpu);
1374 ++vcpu->stat.trap_inst_exits;
1375 ret = kvm_mips_callbacks->handle_trap(vcpu);
1378 case EXCCODE_MSAFPE:
1379 ++vcpu->stat.msa_fpe_exits;
1380 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1384 ++vcpu->stat.fpe_exits;
1385 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1388 case EXCCODE_MSADIS:
1389 ++vcpu->stat.msa_disabled_exits;
1390 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1394 /* defer exit accounting to handler */
1395 ret = kvm_mips_callbacks->handle_guest_exit(vcpu);
1399 if (cause & CAUSEF_BD)
1402 kvm_get_badinstr(opc, vcpu, &inst);
1403 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#x\n",
1404 exccode, opc, inst, badvaddr,
1405 kvm_read_c0_guest_status(vcpu->arch.cop0));
1406 kvm_arch_vcpu_dump_regs(vcpu);
1407 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1414 local_irq_disable();
1416 if (ret == RESUME_GUEST)
1417 kvm_vz_acquire_htimer(vcpu);
1419 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1420 kvm_mips_deliver_interrupts(vcpu, cause);
1422 if (!(ret & RESUME_HOST)) {
1423 /* Only check for signals if not already exiting to userspace */
1424 if (signal_pending(current)) {
1425 run->exit_reason = KVM_EXIT_INTR;
1426 ret = (-EINTR << 2) | RESUME_HOST;
1427 ++vcpu->stat.signal_exits;
1428 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1432 if (ret == RESUME_GUEST) {
1433 trace_kvm_reenter(vcpu);
1436 * Make sure the read of VCPU requests in vcpu_reenter()
1437 * callback is not reordered ahead of the write to vcpu->mode,
1438 * or we could miss a TLB flush request while the requester sees
1439 * the VCPU as outside of guest mode and not needing an IPI.
1441 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
1443 kvm_mips_callbacks->vcpu_reenter(run, vcpu);
1446 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1447 * is live), restore FCR31 / MSACSR.
1449 * This should be before returning to the guest exception
1450 * vector, as it may well cause an [MSA] FP exception if there
1451 * are pending exception bits unmasked. (see
1452 * kvm_mips_csr_die_notifier() for how that is handled).
1454 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1455 read_c0_status() & ST0_CU1)
1456 __kvm_restore_fcsr(&vcpu->arch);
1458 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1459 read_c0_config5() & MIPS_CONF5_MSAEN)
1460 __kvm_restore_msacsr(&vcpu->arch);
1463 /* Disable HTW before returning to guest or host */
1464 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1470 /* Enable FPU for guest and restore context */
1471 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1473 struct mips_coproc *cop0 = vcpu->arch.cop0;
1474 unsigned int sr, cfg5;
1478 sr = kvm_read_c0_guest_status(cop0);
1481 * If MSA state is already live, it is undefined how it interacts with
1482 * FR=0 FPU state, and we don't want to hit reserved instruction
1483 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1484 * play it safe and save it first.
1486 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1487 * get called when guest CU1 is set, however we can't trust the guest
1488 * not to clobber the status register directly via the commpage.
1490 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1491 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1495 * Enable FPU for guest
1496 * We set FR and FRE according to guest context
1498 change_c0_status(ST0_CU1 | ST0_FR, sr);
1500 cfg5 = kvm_read_c0_guest_config5(cop0);
1501 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1503 enable_fpu_hazard();
1505 /* If guest FPU state not active, restore it now */
1506 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1507 __kvm_restore_fpu(&vcpu->arch);
1508 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1509 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1511 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1517 #ifdef CONFIG_CPU_HAS_MSA
1518 /* Enable MSA for guest and restore context */
1519 void kvm_own_msa(struct kvm_vcpu *vcpu)
1521 struct mips_coproc *cop0 = vcpu->arch.cop0;
1522 unsigned int sr, cfg5;
1527 * Enable FPU if enabled in guest, since we're restoring FPU context
1528 * anyway. We set FR and FRE according to guest context.
1530 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1531 sr = kvm_read_c0_guest_status(cop0);
1534 * If FR=0 FPU state is already live, it is undefined how it
1535 * interacts with MSA state, so play it safe and save it first.
1537 if (!(sr & ST0_FR) &&
1538 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1539 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1542 change_c0_status(ST0_CU1 | ST0_FR, sr);
1543 if (sr & ST0_CU1 && cpu_has_fre) {
1544 cfg5 = kvm_read_c0_guest_config5(cop0);
1545 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1549 /* Enable MSA for guest */
1550 set_c0_config5(MIPS_CONF5_MSAEN);
1551 enable_fpu_hazard();
1553 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1554 case KVM_MIPS_AUX_FPU:
1556 * Guest FPU state already loaded, only restore upper MSA state
1558 __kvm_restore_msa_upper(&vcpu->arch);
1559 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1560 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1563 /* Neither FPU or MSA already active, restore full MSA state */
1564 __kvm_restore_msa(&vcpu->arch);
1565 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1566 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1567 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1568 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1569 KVM_TRACE_AUX_FPU_MSA);
1572 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1580 /* Drop FPU & MSA without saving it */
1581 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1584 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1586 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1587 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1589 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1590 clear_c0_status(ST0_CU1 | ST0_FR);
1591 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1592 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1597 /* Save and disable FPU & MSA */
1598 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1601 * With T&E, FPU & MSA get disabled in root context (hardware) when it
1602 * is disabled in guest context (software), but the register state in
1603 * the hardware may still be in use.
1604 * This is why we explicitly re-enable the hardware before saving.
1608 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1609 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1610 set_c0_config5(MIPS_CONF5_MSAEN);
1611 enable_fpu_hazard();
1614 __kvm_save_msa(&vcpu->arch);
1615 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1617 /* Disable MSA & FPU */
1619 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1620 clear_c0_status(ST0_CU1 | ST0_FR);
1621 disable_fpu_hazard();
1623 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1624 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1625 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1626 set_c0_status(ST0_CU1);
1627 enable_fpu_hazard();
1630 __kvm_save_fpu(&vcpu->arch);
1631 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1632 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1635 clear_c0_status(ST0_CU1 | ST0_FR);
1636 disable_fpu_hazard();
1642 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1643 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1644 * exception if cause bits are set in the value being written.
1646 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1647 unsigned long cmd, void *ptr)
1649 struct die_args *args = (struct die_args *)ptr;
1650 struct pt_regs *regs = args->regs;
1653 /* Only interested in FPE and MSAFPE */
1654 if (cmd != DIE_FP && cmd != DIE_MSAFP)
1657 /* Return immediately if guest context isn't active */
1658 if (!(current->flags & PF_VCPU))
1661 /* Should never get here from user mode */
1662 BUG_ON(user_mode(regs));
1664 pc = instruction_pointer(regs);
1667 /* match 2nd instruction in __kvm_restore_fcsr */
1668 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1672 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1674 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1675 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1680 /* Move PC forward a little and continue executing */
1681 instruction_pointer(regs) += 4;
1686 static struct notifier_block kvm_mips_csr_die_notifier = {
1687 .notifier_call = kvm_mips_csr_die_notify,
1690 static int __init kvm_mips_init(void)
1694 ret = kvm_mips_entry_setup();
1698 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1703 register_die_notifier(&kvm_mips_csr_die_notifier);
1708 static void __exit kvm_mips_exit(void)
1712 unregister_die_notifier(&kvm_mips_csr_die_notifier);
1715 module_init(kvm_mips_init);
1716 module_exit(kvm_mips_exit);
1718 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);