arch/mips/kvm/mips.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * KVM/MIPS: MIPS specific KVM APIs
   7  *
   8  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10  */
  11
  12 #include <linux/bitops.h>
  13 #include <linux/errno.h>
  14 #include <linux/err.h>
  15 #include <linux/kdebug.h>
  16 #include <linux/module.h>
  17 #include <linux/uaccess.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/fs.h>
  20 #include <linux/bootmem.h>
  21 #include <asm/fpu.h>
  22 #include <asm/page.h>
  23 #include <asm/cacheflush.h>
  24 #include <asm/mmu_context.h>
  25 #include <asm/pgalloc.h>
  26 #include <asm/pgtable.h>
  27
  28 #include <linux/kvm_host.h>
  29
  30 #include "interrupt.h"
  31 #include "commpage.h"
  32
  33 #define CREATE_TRACE_POINTS
  34 #include "trace.h"
  35
  36 #ifndef VECTORSPACING
  37 #define VECTORSPACING 0x100     /* for EI/VI mode */
  38 #endif
  39
  40 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
  41 struct kvm_stats_debugfs_item debugfs_entries[] = {
  42         { "wait",         VCPU_STAT(wait_exits),         KVM_STAT_VCPU },
  43         { "cache",        VCPU_STAT(cache_exits),        KVM_STAT_VCPU },
  44         { "signal",       VCPU_STAT(signal_exits),       KVM_STAT_VCPU },
  45         { "interrupt",    VCPU_STAT(int_exits),          KVM_STAT_VCPU },
  46         { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
  47         { "tlbmod",       VCPU_STAT(tlbmod_exits),       KVM_STAT_VCPU },
  48         { "tlbmiss_ld",   VCPU_STAT(tlbmiss_ld_exits),   KVM_STAT_VCPU },
  49         { "tlbmiss_st",   VCPU_STAT(tlbmiss_st_exits),   KVM_STAT_VCPU },
  50         { "addrerr_st",   VCPU_STAT(addrerr_st_exits),   KVM_STAT_VCPU },
  51         { "addrerr_ld",   VCPU_STAT(addrerr_ld_exits),   KVM_STAT_VCPU },
  52         { "syscall",      VCPU_STAT(syscall_exits),      KVM_STAT_VCPU },
  53         { "resvd_inst",   VCPU_STAT(resvd_inst_exits),   KVM_STAT_VCPU },
  54         { "break_inst",   VCPU_STAT(break_inst_exits),   KVM_STAT_VCPU },
  55         { "trap_inst",    VCPU_STAT(trap_inst_exits),    KVM_STAT_VCPU },
  56         { "msa_fpe",      VCPU_STAT(msa_fpe_exits),      KVM_STAT_VCPU },
  57         { "fpe",          VCPU_STAT(fpe_exits),          KVM_STAT_VCPU },
  58         { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
  59         { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
  60         { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
  61         { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
  62         { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
  63         { "halt_wakeup",  VCPU_STAT(halt_wakeup),        KVM_STAT_VCPU },
  64         {NULL}
  65 };
  66
  67 /*
  68  * XXXKYMA: We are simulatoring a processor that has the WII bit set in
  69  * Config7, so we are "runnable" if interrupts are pending
  70  */
  71 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
  72 {
  73         return !!(vcpu->arch.pending_exceptions);
  74 }
  75
  76 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
  77 {
  78         return 1;
  79 }
  80
  81 int kvm_arch_hardware_enable(void)
  82 {
  83         return 0;
  84 }
  85
  86 int kvm_arch_hardware_setup(void)
  87 {
  88         return 0;
  89 }
  90
  91 void kvm_arch_check_processor_compat(void *rtn)
  92 {
  93         *(int *)rtn = 0;
  94 }
  95
  96 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
  97 {
  98         /* Allocate page table to map GPA -> RPA */
  99         kvm->arch.gpa_mm.pgd = kvm_pgd_alloc();
 100         if (!kvm->arch.gpa_mm.pgd)
 101                 return -ENOMEM;
 102
 103         return 0;
 104 }
 105
 106 bool kvm_arch_has_vcpu_debugfs(void)
 107 {
 108         return false;
 109 }
 110
 111 int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu)
 112 {
 113         return 0;
 114 }
 115
 116 void kvm_mips_free_vcpus(struct kvm *kvm)
 117 {
 118         unsigned int i;
 119         struct kvm_vcpu *vcpu;
 120
 121         kvm_for_each_vcpu(i, vcpu, kvm) {
 122                 kvm_arch_vcpu_free(vcpu);
 123         }
 124
 125         mutex_lock(&kvm->lock);
 126
 127         for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
 128                 kvm->vcpus[i] = NULL;
 129
 130         atomic_set(&kvm->online_vcpus, 0);
 131
 132         mutex_unlock(&kvm->lock);
 133 }
 134
 135 static void kvm_mips_free_gpa_pt(struct kvm *kvm)
 136 {
 137         /* It should always be safe to remove after flushing the whole range */
 138         WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0));
 139         pgd_free(NULL, kvm->arch.gpa_mm.pgd);
 140 }
 141
 142 void kvm_arch_destroy_vm(struct kvm *kvm)
 143 {
 144         kvm_mips_free_vcpus(kvm);
 145         kvm_mips_free_gpa_pt(kvm);
 146 }
 147
 148 long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
 149                         unsigned long arg)
 150 {
 151         return -ENOIOCTLCMD;
 152 }
 153
 154 int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
 155                             unsigned long npages)
 156 {
 157         return 0;
 158 }
 159
 160 void kvm_arch_flush_shadow_all(struct kvm *kvm)
 161 {
 162         /* Flush whole GPA */
 163         kvm_mips_flush_gpa_pt(kvm, 0, ~0);
 164
 165         /* Let implementation do the rest */
 166         kvm_mips_callbacks->flush_shadow_all(kvm);
 167 }
 168
 169 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
 170                                    struct kvm_memory_slot *slot)
 171 {
 172         /*
 173          * The slot has been made invalid (ready for moving or deletion), so we
 174          * need to ensure that it can no longer be accessed by any guest VCPUs.
 175          */
 176
 177         spin_lock(&kvm->mmu_lock);
 178         /* Flush slot from GPA */
 179         kvm_mips_flush_gpa_pt(kvm, slot->base_gfn,
 180                               slot->base_gfn + slot->npages - 1);
 181         /* Let implementation do the rest */
 182         kvm_mips_callbacks->flush_shadow_memslot(kvm, slot);
 183         spin_unlock(&kvm->mmu_lock);
 184 }
 185
 186 int kvm_arch_prepare_memory_region(struct kvm *kvm,
 187                                    struct kvm_memory_slot *memslot,
 188                                    const struct kvm_userspace_memory_region *mem,
 189                                    enum kvm_mr_change change)
 190 {
 191         return 0;
 192 }
 193
 194 void kvm_arch_commit_memory_region(struct kvm *kvm,
 195                                    const struct kvm_userspace_memory_region *mem,
 196                                    const struct kvm_memory_slot *old,
 197                                    const struct kvm_memory_slot *new,
 198                                    enum kvm_mr_change change)
 199 {
 200         int needs_flush;
 201
 202         kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
 203                   __func__, kvm, mem->slot, mem->guest_phys_addr,
 204                   mem->memory_size, mem->userspace_addr);
 205
 206         /*
 207          * If dirty page logging is enabled, write protect all pages in the slot
 208          * ready for dirty logging.
 209          *
 210          * There is no need to do this in any of the following cases:
 211          * CREATE:      No dirty mappings will already exist.
 212          * MOVE/DELETE: The old mappings will already have been cleaned up by
 213          *              kvm_arch_flush_shadow_memslot()
 214          */
 215         if (change == KVM_MR_FLAGS_ONLY &&
 216             (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
 217              new->flags & KVM_MEM_LOG_DIRTY_PAGES)) {
 218                 spin_lock(&kvm->mmu_lock);
 219                 /* Write protect GPA page table entries */
 220                 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn,
 221                                         new->base_gfn + new->npages - 1);
 222                 /* Let implementation do the rest */
 223                 if (needs_flush)
 224                         kvm_mips_callbacks->flush_shadow_memslot(kvm, new);
 225                 spin_unlock(&kvm->mmu_lock);
 226         }
 227 }
 228
 229 static inline void dump_handler(const char *symbol, void *start, void *end)
 230 {
 231         u32 *p;
 232
 233         pr_debug("LEAF(%s)\n", symbol);
 234
 235         pr_debug("\t.set push\n");
 236         pr_debug("\t.set noreorder\n");
 237
 238         for (p = start; p < (u32 *)end; ++p)
 239                 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
 240
 241         pr_debug("\t.set\tpop\n");
 242
 243         pr_debug("\tEND(%s)\n", symbol);
 244 }
 245
 246 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
 247 {
 248         int err, size;
 249         void *gebase, *p, *handler, *refill_start, *refill_end;
 250         int i;
 251
 252         struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
 253
 254         if (!vcpu) {
 255                 err = -ENOMEM;
 256                 goto out;
 257         }
 258
 259         err = kvm_vcpu_init(vcpu, kvm, id);
 260
 261         if (err)
 262                 goto out_free_cpu;
 263
 264         kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
 265
 266         /*
 267          * Allocate space for host mode exception handlers that handle
 268          * guest mode exits
 269          */
 270         if (cpu_has_veic || cpu_has_vint)
 271                 size = 0x200 + VECTORSPACING * 64;
 272         else
 273                 size = 0x4000;
 274
 275         gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
 276
 277         if (!gebase) {
 278                 err = -ENOMEM;
 279                 goto out_uninit_cpu;
 280         }
 281         kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
 282                   ALIGN(size, PAGE_SIZE), gebase);
 283
 284         /*
 285          * Check new ebase actually fits in CP0_EBase. The lack of a write gate
 286          * limits us to the low 512MB of physical address space. If the memory
 287          * we allocate is out of range, just give up now.
 288          */
 289         if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
 290                 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
 291                         gebase);
 292                 err = -ENOMEM;
 293                 goto out_free_gebase;
 294         }
 295
 296         /* Save new ebase */
 297         vcpu->arch.guest_ebase = gebase;
 298
 299         /* Build guest exception vectors dynamically in unmapped memory */
 300         handler = gebase + 0x2000;
 301
 302         /* TLB refill */
 303         refill_start = gebase;
 304         refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler);
 305
 306         /* General Exception Entry point */
 307         kvm_mips_build_exception(gebase + 0x180, handler);
 308
 309         /* For vectored interrupts poke the exception code @ all offsets 0-7 */
 310         for (i = 0; i < 8; i++) {
 311                 kvm_debug("L1 Vectored handler @ %p\n",
 312                           gebase + 0x200 + (i * VECTORSPACING));
 313                 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
 314                                          handler);
 315         }
 316
 317         /* General exit handler */
 318         p = handler;
 319         p = kvm_mips_build_exit(p);
 320
 321         /* Guest entry routine */
 322         vcpu->arch.vcpu_run = p;
 323         p = kvm_mips_build_vcpu_run(p);
 324
 325         /* Dump the generated code */
 326         pr_debug("#include <asm/asm.h>\n");
 327         pr_debug("#include <asm/regdef.h>\n");
 328         pr_debug("\n");
 329         dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
 330         dump_handler("kvm_tlb_refill", refill_start, refill_end);
 331         dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
 332         dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
 333
 334         /* Invalidate the icache for these ranges */
 335         flush_icache_range((unsigned long)gebase,
 336                            (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
 337
 338         /*
 339          * Allocate comm page for guest kernel, a TLB will be reserved for
 340          * mapping GVA @ 0xFFFF8000 to this page
 341          */
 342         vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
 343
 344         if (!vcpu->arch.kseg0_commpage) {
 345                 err = -ENOMEM;
 346                 goto out_free_gebase;
 347         }
 348
 349         kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
 350         kvm_mips_commpage_init(vcpu);
 351
 352         /* Init */
 353         vcpu->arch.last_sched_cpu = -1;
 354
 355         /* Start off the timer */
 356         kvm_mips_init_count(vcpu);
 357
 358         return vcpu;
 359
 360 out_free_gebase:
 361         kfree(gebase);
 362
 363 out_uninit_cpu:
 364         kvm_vcpu_uninit(vcpu);
 365
 366 out_free_cpu:
 367         kfree(vcpu);
 368
 369 out:
 370         return ERR_PTR(err);
 371 }
 372
 373 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
 374 {
 375         hrtimer_cancel(&vcpu->arch.comparecount_timer);
 376
 377         kvm_vcpu_uninit(vcpu);
 378
 379         kvm_mips_dump_stats(vcpu);
 380
 381         kvm_mmu_free_memory_caches(vcpu);
 382         kfree(vcpu->arch.guest_ebase);
 383         kfree(vcpu->arch.kseg0_commpage);
 384         kfree(vcpu);
 385 }
 386
 387 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 388 {
 389         kvm_arch_vcpu_free(vcpu);
 390 }
 391
 392 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
 393                                         struct kvm_guest_debug *dbg)
 394 {
 395         return -ENOIOCTLCMD;
 396 }
 397
 398 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
 399 {
 400         int r = 0;
 401         sigset_t sigsaved;
 402
 403         if (vcpu->sigset_active)
 404                 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
 405
 406         if (vcpu->mmio_needed) {
 407                 if (!vcpu->mmio_is_write)
 408                         kvm_mips_complete_mmio_load(vcpu, run);
 409                 vcpu->mmio_needed = 0;
 410         }
 411
 412         lose_fpu(1);
 413
 414         local_irq_disable();
 415         guest_enter_irqoff();
 416         trace_kvm_enter(vcpu);
 417
 418         /*
 419          * Make sure the read of VCPU requests in vcpu_run() callback is not
 420          * reordered ahead of the write to vcpu->mode, or we could miss a TLB
 421          * flush request while the requester sees the VCPU as outside of guest
 422          * mode and not needing an IPI.
 423          */
 424         smp_store_mb(vcpu->mode, IN_GUEST_MODE);
 425
 426         r = kvm_mips_callbacks->vcpu_run(run, vcpu);
 427
 428         trace_kvm_out(vcpu);
 429         guest_exit_irqoff();
 430         local_irq_enable();
 431
 432         if (vcpu->sigset_active)
 433                 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
 434
 435         return r;
 436 }
 437
 438 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
 439                              struct kvm_mips_interrupt *irq)
 440 {
 441         int intr = (int)irq->irq;
 442         struct kvm_vcpu *dvcpu = NULL;
 443
 444         if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
 445                 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
 446                           (int)intr);
 447
 448         if (irq->cpu == -1)
 449                 dvcpu = vcpu;
 450         else
 451                 dvcpu = vcpu->kvm->vcpus[irq->cpu];
 452
 453         if (intr == 2 || intr == 3 || intr == 4) {
 454                 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
 455
 456         } else if (intr == -2 || intr == -3 || intr == -4) {
 457                 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
 458         } else {
 459                 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
 460                         irq->cpu, irq->irq);
 461                 return -EINVAL;
 462         }
 463
 464         dvcpu->arch.wait = 0;
 465
 466         if (swait_active(&dvcpu->wq))
 467                 swake_up(&dvcpu->wq);
 468
 469         return 0;
 470 }
 471
 472 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
 473                                     struct kvm_mp_state *mp_state)
 474 {
 475         return -ENOIOCTLCMD;
 476 }
 477
 478 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
 479                                     struct kvm_mp_state *mp_state)
 480 {
 481         return -ENOIOCTLCMD;
 482 }
 483
 484 static u64 kvm_mips_get_one_regs[] = {
 485         KVM_REG_MIPS_R0,
 486         KVM_REG_MIPS_R1,
 487         KVM_REG_MIPS_R2,
 488         KVM_REG_MIPS_R3,
 489         KVM_REG_MIPS_R4,
 490         KVM_REG_MIPS_R5,
 491         KVM_REG_MIPS_R6,
 492         KVM_REG_MIPS_R7,
 493         KVM_REG_MIPS_R8,
 494         KVM_REG_MIPS_R9,
 495         KVM_REG_MIPS_R10,
 496         KVM_REG_MIPS_R11,
 497         KVM_REG_MIPS_R12,
 498         KVM_REG_MIPS_R13,
 499         KVM_REG_MIPS_R14,
 500         KVM_REG_MIPS_R15,
 501         KVM_REG_MIPS_R16,
 502         KVM_REG_MIPS_R17,
 503         KVM_REG_MIPS_R18,
 504         KVM_REG_MIPS_R19,
 505         KVM_REG_MIPS_R20,
 506         KVM_REG_MIPS_R21,
 507         KVM_REG_MIPS_R22,
 508         KVM_REG_MIPS_R23,
 509         KVM_REG_MIPS_R24,
 510         KVM_REG_MIPS_R25,
 511         KVM_REG_MIPS_R26,
 512         KVM_REG_MIPS_R27,
 513         KVM_REG_MIPS_R28,
 514         KVM_REG_MIPS_R29,
 515         KVM_REG_MIPS_R30,
 516         KVM_REG_MIPS_R31,
 517
 518 #ifndef CONFIG_CPU_MIPSR6
 519         KVM_REG_MIPS_HI,
 520         KVM_REG_MIPS_LO,
 521 #endif
 522         KVM_REG_MIPS_PC,
 523
 524         KVM_REG_MIPS_CP0_INDEX,
 525         KVM_REG_MIPS_CP0_CONTEXT,
 526         KVM_REG_MIPS_CP0_USERLOCAL,
 527         KVM_REG_MIPS_CP0_PAGEMASK,
 528         KVM_REG_MIPS_CP0_WIRED,
 529         KVM_REG_MIPS_CP0_HWRENA,
 530         KVM_REG_MIPS_CP0_BADVADDR,
 531         KVM_REG_MIPS_CP0_COUNT,
 532         KVM_REG_MIPS_CP0_ENTRYHI,
 533         KVM_REG_MIPS_CP0_COMPARE,
 534         KVM_REG_MIPS_CP0_STATUS,
 535         KVM_REG_MIPS_CP0_CAUSE,
 536         KVM_REG_MIPS_CP0_EPC,
 537         KVM_REG_MIPS_CP0_PRID,
 538         KVM_REG_MIPS_CP0_CONFIG,
 539         KVM_REG_MIPS_CP0_CONFIG1,
 540         KVM_REG_MIPS_CP0_CONFIG2,
 541         KVM_REG_MIPS_CP0_CONFIG3,
 542         KVM_REG_MIPS_CP0_CONFIG4,
 543         KVM_REG_MIPS_CP0_CONFIG5,
 544         KVM_REG_MIPS_CP0_CONFIG7,
 545         KVM_REG_MIPS_CP0_ERROREPC,
 546
 547         KVM_REG_MIPS_COUNT_CTL,
 548         KVM_REG_MIPS_COUNT_RESUME,
 549         KVM_REG_MIPS_COUNT_HZ,
 550 };
 551
 552 static u64 kvm_mips_get_one_regs_fpu[] = {
 553         KVM_REG_MIPS_FCR_IR,
 554         KVM_REG_MIPS_FCR_CSR,
 555 };
 556
 557 static u64 kvm_mips_get_one_regs_msa[] = {
 558         KVM_REG_MIPS_MSA_IR,
 559         KVM_REG_MIPS_MSA_CSR,
 560 };
 561
 562 static u64 kvm_mips_get_one_regs_kscratch[] = {
 563         KVM_REG_MIPS_CP0_KSCRATCH1,
 564         KVM_REG_MIPS_CP0_KSCRATCH2,
 565         KVM_REG_MIPS_CP0_KSCRATCH3,
 566         KVM_REG_MIPS_CP0_KSCRATCH4,
 567         KVM_REG_MIPS_CP0_KSCRATCH5,
 568         KVM_REG_MIPS_CP0_KSCRATCH6,
 569 };
 570
 571 static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
 572 {
 573         unsigned long ret;
 574
 575         ret = ARRAY_SIZE(kvm_mips_get_one_regs);
 576         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 577                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
 578                 /* odd doubles */
 579                 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
 580                         ret += 16;
 581         }
 582         if (kvm_mips_guest_can_have_msa(&vcpu->arch))
 583                 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
 584         ret += __arch_hweight8(vcpu->arch.kscratch_enabled);
 585         ret += kvm_mips_callbacks->num_regs(vcpu);
 586
 587         return ret;
 588 }
 589
 590 static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
 591 {
 592         u64 index;
 593         unsigned int i;
 594
 595         if (copy_to_user(indices, kvm_mips_get_one_regs,
 596                          sizeof(kvm_mips_get_one_regs)))
 597                 return -EFAULT;
 598         indices += ARRAY_SIZE(kvm_mips_get_one_regs);
 599
 600         if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
 601                 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
 602                                  sizeof(kvm_mips_get_one_regs_fpu)))
 603                         return -EFAULT;
 604                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
 605
 606                 for (i = 0; i < 32; ++i) {
 607                         index = KVM_REG_MIPS_FPR_32(i);
 608                         if (copy_to_user(indices, &index, sizeof(index)))
 609                                 return -EFAULT;
 610                         ++indices;
 611
 612                         /* skip odd doubles if no F64 */
 613                         if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
 614                                 continue;
 615
 616                         index = KVM_REG_MIPS_FPR_64(i);
 617                         if (copy_to_user(indices, &index, sizeof(index)))
 618                                 return -EFAULT;
 619                         ++indices;
 620                 }
 621         }
 622
 623         if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
 624                 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
 625                                  sizeof(kvm_mips_get_one_regs_msa)))
 626                         return -EFAULT;
 627                 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
 628
 629                 for (i = 0; i < 32; ++i) {
 630                         index = KVM_REG_MIPS_VEC_128(i);
 631                         if (copy_to_user(indices, &index, sizeof(index)))
 632                                 return -EFAULT;
 633                         ++indices;
 634                 }
 635         }
 636
 637         for (i = 0; i < 6; ++i) {
 638                 if (!(vcpu->arch.kscratch_enabled & BIT(i + 2)))
 639                         continue;
 640
 641                 if (copy_to_user(indices, &kvm_mips_get_one_regs_kscratch[i],
 642                                  sizeof(kvm_mips_get_one_regs_kscratch[i])))
 643                         return -EFAULT;
 644                 ++indices;
 645         }
 646
 647         return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
 648 }
 649
 650 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
 651                             const struct kvm_one_reg *reg)
 652 {
 653         struct mips_coproc *cop0 = vcpu->arch.cop0;
 654         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 655         int ret;
 656         s64 v;
 657         s64 vs[2];
 658         unsigned int idx;
 659
 660         switch (reg->id) {
 661         /* General purpose registers */
 662         case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
 663                 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
 664                 break;
 665 #ifndef CONFIG_CPU_MIPSR6
 666         case KVM_REG_MIPS_HI:
 667                 v = (long)vcpu->arch.hi;
 668                 break;
 669         case KVM_REG_MIPS_LO:
 670                 v = (long)vcpu->arch.lo;
 671                 break;
 672 #endif
 673         case KVM_REG_MIPS_PC:
 674                 v = (long)vcpu->arch.pc;
 675                 break;
 676
 677         /* Floating point registers */
 678         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 679                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 680                         return -EINVAL;
 681                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 682                 /* Odd singles in top of even double when FR=0 */
 683                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 684                         v = get_fpr32(&fpu->fpr[idx], 0);
 685                 else
 686                         v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
 687                 break;
 688         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 689                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 690                         return -EINVAL;
 691                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 692                 /* Can't access odd doubles in FR=0 mode */
 693                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 694                         return -EINVAL;
 695                 v = get_fpr64(&fpu->fpr[idx], 0);
 696                 break;
 697         case KVM_REG_MIPS_FCR_IR:
 698                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 699                         return -EINVAL;
 700                 v = boot_cpu_data.fpu_id;
 701                 break;
 702         case KVM_REG_MIPS_FCR_CSR:
 703                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 704                         return -EINVAL;
 705                 v = fpu->fcr31;
 706                 break;
 707
 708         /* MIPS SIMD Architecture (MSA) registers */
 709         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 710                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 711                         return -EINVAL;
 712                 /* Can't access MSA registers in FR=0 mode */
 713                 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
 714                         return -EINVAL;
 715                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 716 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 717                 /* least significant byte first */
 718                 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
 719                 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
 720 #else
 721                 /* most significant byte first */
 722                 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
 723                 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
 724 #endif
 725                 break;
 726         case KVM_REG_MIPS_MSA_IR:
 727                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 728                         return -EINVAL;
 729                 v = boot_cpu_data.msa_id;
 730                 break;
 731         case KVM_REG_MIPS_MSA_CSR:
 732                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 733                         return -EINVAL;
 734                 v = fpu->msacsr;
 735                 break;
 736
 737         /* Co-processor 0 registers */
 738         case KVM_REG_MIPS_CP0_INDEX:
 739                 v = (long)kvm_read_c0_guest_index(cop0);
 740                 break;
 741         case KVM_REG_MIPS_CP0_CONTEXT:
 742                 v = (long)kvm_read_c0_guest_context(cop0);
 743                 break;
 744         case KVM_REG_MIPS_CP0_USERLOCAL:
 745                 v = (long)kvm_read_c0_guest_userlocal(cop0);
 746                 break;
 747         case KVM_REG_MIPS_CP0_PAGEMASK:
 748                 v = (long)kvm_read_c0_guest_pagemask(cop0);
 749                 break;
 750         case KVM_REG_MIPS_CP0_WIRED:
 751                 v = (long)kvm_read_c0_guest_wired(cop0);
 752                 break;
 753         case KVM_REG_MIPS_CP0_HWRENA:
 754                 v = (long)kvm_read_c0_guest_hwrena(cop0);
 755                 break;
 756         case KVM_REG_MIPS_CP0_BADVADDR:
 757                 v = (long)kvm_read_c0_guest_badvaddr(cop0);
 758                 break;
 759         case KVM_REG_MIPS_CP0_ENTRYHI:
 760                 v = (long)kvm_read_c0_guest_entryhi(cop0);
 761                 break;
 762         case KVM_REG_MIPS_CP0_COMPARE:
 763                 v = (long)kvm_read_c0_guest_compare(cop0);
 764                 break;
 765         case KVM_REG_MIPS_CP0_STATUS:
 766                 v = (long)kvm_read_c0_guest_status(cop0);
 767                 break;
 768         case KVM_REG_MIPS_CP0_CAUSE:
 769                 v = (long)kvm_read_c0_guest_cause(cop0);
 770                 break;
 771         case KVM_REG_MIPS_CP0_EPC:
 772                 v = (long)kvm_read_c0_guest_epc(cop0);
 773                 break;
 774         case KVM_REG_MIPS_CP0_PRID:
 775                 v = (long)kvm_read_c0_guest_prid(cop0);
 776                 break;
 777         case KVM_REG_MIPS_CP0_CONFIG:
 778                 v = (long)kvm_read_c0_guest_config(cop0);
 779                 break;
 780         case KVM_REG_MIPS_CP0_CONFIG1:
 781                 v = (long)kvm_read_c0_guest_config1(cop0);
 782                 break;
 783         case KVM_REG_MIPS_CP0_CONFIG2:
 784                 v = (long)kvm_read_c0_guest_config2(cop0);
 785                 break;
 786         case KVM_REG_MIPS_CP0_CONFIG3:
 787                 v = (long)kvm_read_c0_guest_config3(cop0);
 788                 break;
 789         case KVM_REG_MIPS_CP0_CONFIG4:
 790                 v = (long)kvm_read_c0_guest_config4(cop0);
 791                 break;
 792         case KVM_REG_MIPS_CP0_CONFIG5:
 793                 v = (long)kvm_read_c0_guest_config5(cop0);
 794                 break;
 795         case KVM_REG_MIPS_CP0_CONFIG7:
 796                 v = (long)kvm_read_c0_guest_config7(cop0);
 797                 break;
 798         case KVM_REG_MIPS_CP0_ERROREPC:
 799                 v = (long)kvm_read_c0_guest_errorepc(cop0);
 800                 break;
 801         case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6:
 802                 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2;
 803                 if (!(vcpu->arch.kscratch_enabled & BIT(idx)))
 804                         return -EINVAL;
 805                 switch (idx) {
 806                 case 2:
 807                         v = (long)kvm_read_c0_guest_kscratch1(cop0);
 808                         break;
 809                 case 3:
 810                         v = (long)kvm_read_c0_guest_kscratch2(cop0);
 811                         break;
 812                 case 4:
 813                         v = (long)kvm_read_c0_guest_kscratch3(cop0);
 814                         break;
 815                 case 5:
 816                         v = (long)kvm_read_c0_guest_kscratch4(cop0);
 817                         break;
 818                 case 6:
 819                         v = (long)kvm_read_c0_guest_kscratch5(cop0);
 820                         break;
 821                 case 7:
 822                         v = (long)kvm_read_c0_guest_kscratch6(cop0);
 823                         break;
 824                 }
 825                 break;
 826         /* registers to be handled specially */
 827         default:
 828                 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
 829                 if (ret)
 830                         return ret;
 831                 break;
 832         }
 833         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 834                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 835
 836                 return put_user(v, uaddr64);
 837         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 838                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 839                 u32 v32 = (u32)v;
 840
 841                 return put_user(v32, uaddr32);
 842         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 843                 void __user *uaddr = (void __user *)(long)reg->addr;
 844
 845                 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
 846         } else {
 847                 return -EINVAL;
 848         }
 849 }
 850
 851 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
 852                             const struct kvm_one_reg *reg)
 853 {
 854         struct mips_coproc *cop0 = vcpu->arch.cop0;
 855         struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
 856         s64 v;
 857         s64 vs[2];
 858         unsigned int idx;
 859
 860         if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
 861                 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
 862
 863                 if (get_user(v, uaddr64) != 0)
 864                         return -EFAULT;
 865         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
 866                 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
 867                 s32 v32;
 868
 869                 if (get_user(v32, uaddr32) != 0)
 870                         return -EFAULT;
 871                 v = (s64)v32;
 872         } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
 873                 void __user *uaddr = (void __user *)(long)reg->addr;
 874
 875                 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
 876         } else {
 877                 return -EINVAL;
 878         }
 879
 880         switch (reg->id) {
 881         /* General purpose registers */
 882         case KVM_REG_MIPS_R0:
 883                 /* Silently ignore requests to set $0 */
 884                 break;
 885         case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
 886                 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
 887                 break;
 888 #ifndef CONFIG_CPU_MIPSR6
 889         case KVM_REG_MIPS_HI:
 890                 vcpu->arch.hi = v;
 891                 break;
 892         case KVM_REG_MIPS_LO:
 893                 vcpu->arch.lo = v;
 894                 break;
 895 #endif
 896         case KVM_REG_MIPS_PC:
 897                 vcpu->arch.pc = v;
 898                 break;
 899
 900         /* Floating point registers */
 901         case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
 902                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 903                         return -EINVAL;
 904                 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
 905                 /* Odd singles in top of even double when FR=0 */
 906                 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
 907                         set_fpr32(&fpu->fpr[idx], 0, v);
 908                 else
 909                         set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
 910                 break;
 911         case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
 912                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 913                         return -EINVAL;
 914                 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
 915                 /* Can't access odd doubles in FR=0 mode */
 916                 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
 917                         return -EINVAL;
 918                 set_fpr64(&fpu->fpr[idx], 0, v);
 919                 break;
 920         case KVM_REG_MIPS_FCR_IR:
 921                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 922                         return -EINVAL;
 923                 /* Read-only */
 924                 break;
 925         case KVM_REG_MIPS_FCR_CSR:
 926                 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
 927                         return -EINVAL;
 928                 fpu->fcr31 = v;
 929                 break;
 930
 931         /* MIPS SIMD Architecture (MSA) registers */
 932         case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
 933                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 934                         return -EINVAL;
 935                 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
 936 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 937                 /* least significant byte first */
 938                 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
 939                 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
 940 #else
 941                 /* most significant byte first */
 942                 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
 943                 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
 944 #endif
 945                 break;
 946         case KVM_REG_MIPS_MSA_IR:
 947                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 948                         return -EINVAL;
 949                 /* Read-only */
 950                 break;
 951         case KVM_REG_MIPS_MSA_CSR:
 952                 if (!kvm_mips_guest_has_msa(&vcpu->arch))
 953                         return -EINVAL;
 954                 fpu->msacsr = v;
 955                 break;
 956
 957         /* Co-processor 0 registers */
 958         case KVM_REG_MIPS_CP0_INDEX:
 959                 kvm_write_c0_guest_index(cop0, v);
 960                 break;
 961         case KVM_REG_MIPS_CP0_CONTEXT:
 962                 kvm_write_c0_guest_context(cop0, v);
 963                 break;
 964         case KVM_REG_MIPS_CP0_USERLOCAL:
 965                 kvm_write_c0_guest_userlocal(cop0, v);
 966                 break;
 967         case KVM_REG_MIPS_CP0_PAGEMASK:
 968                 kvm_write_c0_guest_pagemask(cop0, v);
 969                 break;
 970         case KVM_REG_MIPS_CP0_WIRED:
 971                 kvm_write_c0_guest_wired(cop0, v);
 972                 break;
 973         case KVM_REG_MIPS_CP0_HWRENA:
 974                 kvm_write_c0_guest_hwrena(cop0, v);
 975                 break;
 976         case KVM_REG_MIPS_CP0_BADVADDR:
 977                 kvm_write_c0_guest_badvaddr(cop0, v);
 978                 break;
 979         case KVM_REG_MIPS_CP0_ENTRYHI:
 980                 kvm_write_c0_guest_entryhi(cop0, v);
 981                 break;
 982         case KVM_REG_MIPS_CP0_STATUS:
 983                 kvm_write_c0_guest_status(cop0, v);
 984                 break;
 985         case KVM_REG_MIPS_CP0_EPC:
 986                 kvm_write_c0_guest_epc(cop0, v);
 987                 break;
 988         case KVM_REG_MIPS_CP0_PRID:
 989                 kvm_write_c0_guest_prid(cop0, v);
 990                 break;
 991         case KVM_REG_MIPS_CP0_ERROREPC:
 992                 kvm_write_c0_guest_errorepc(cop0, v);
 993                 break;
 994         case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6:
 995                 idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2;
 996                 if (!(vcpu->arch.kscratch_enabled & BIT(idx)))
 997                         return -EINVAL;
 998                 switch (idx) {
 999                 case 2:
1000                         kvm_write_c0_guest_kscratch1(cop0, v);
1001                         break;
1002                 case 3:
1003                         kvm_write_c0_guest_kscratch2(cop0, v);
1004                         break;
1005                 case 4:
1006                         kvm_write_c0_guest_kscratch3(cop0, v);
1007                         break;
1008                 case 5:
1009                         kvm_write_c0_guest_kscratch4(cop0, v);
1010                         break;
1011                 case 6:
1012                         kvm_write_c0_guest_kscratch5(cop0, v);
1013                         break;
1014                 case 7:
1015                         kvm_write_c0_guest_kscratch6(cop0, v);
1016                         break;
1017                 }
1018                 break;
1019         /* registers to be handled specially */
1020         default:
1021                 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
1022         }
1023         return 0;
1024 }
1025
1026 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
1027                                      struct kvm_enable_cap *cap)
1028 {
1029         int r = 0;
1030
1031         if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
1032                 return -EINVAL;
1033         if (cap->flags)
1034                 return -EINVAL;
1035         if (cap->args[0])
1036                 return -EINVAL;
1037
1038         switch (cap->cap) {
1039         case KVM_CAP_MIPS_FPU:
1040                 vcpu->arch.fpu_enabled = true;
1041                 break;
1042         case KVM_CAP_MIPS_MSA:
1043                 vcpu->arch.msa_enabled = true;
1044                 break;
1045         default:
1046                 r = -EINVAL;
1047                 break;
1048         }
1049
1050         return r;
1051 }
1052
1053 long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
1054                          unsigned long arg)
1055 {
1056         struct kvm_vcpu *vcpu = filp->private_data;
1057         void __user *argp = (void __user *)arg;
1058         long r;
1059
1060         switch (ioctl) {
1061         case KVM_SET_ONE_REG:
1062         case KVM_GET_ONE_REG: {
1063                 struct kvm_one_reg reg;
1064
1065                 if (copy_from_user(&reg, argp, sizeof(reg)))
1066                         return -EFAULT;
1067                 if (ioctl == KVM_SET_ONE_REG)
1068                         return kvm_mips_set_reg(vcpu, &reg);
1069                 else
1070                         return kvm_mips_get_reg(vcpu, &reg);
1071         }
1072         case KVM_GET_REG_LIST: {
1073                 struct kvm_reg_list __user *user_list = argp;
1074                 struct kvm_reg_list reg_list;
1075                 unsigned n;
1076
1077                 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
1078                         return -EFAULT;
1079                 n = reg_list.n;
1080                 reg_list.n = kvm_mips_num_regs(vcpu);
1081                 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
1082                         return -EFAULT;
1083                 if (n < reg_list.n)
1084                         return -E2BIG;
1085                 return kvm_mips_copy_reg_indices(vcpu, user_list->reg);
1086         }
1087         case KVM_INTERRUPT:
1088                 {
1089                         struct kvm_mips_interrupt irq;
1090
1091                         if (copy_from_user(&irq, argp, sizeof(irq)))
1092                                 return -EFAULT;
1093                         kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
1094                                   irq.irq);
1095
1096                         r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1097                         break;
1098                 }
1099         case KVM_ENABLE_CAP: {
1100                 struct kvm_enable_cap cap;
1101
1102                 if (copy_from_user(&cap, argp, sizeof(cap)))
1103                         return -EFAULT;
1104                 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
1105                 break;
1106         }
1107         default:
1108                 r = -ENOIOCTLCMD;
1109         }
1110         return r;
1111 }
1112
1113 /**
1114  * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
1115  * @kvm: kvm instance
1116  * @log: slot id and address to which we copy the log
1117  *
1118  * Steps 1-4 below provide general overview of dirty page logging. See
1119  * kvm_get_dirty_log_protect() function description for additional details.
1120  *
1121  * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
1122  * always flush the TLB (step 4) even if previous step failed  and the dirty
1123  * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
1124  * does not preclude user space subsequent dirty log read. Flushing TLB ensures
1125  * writes will be marked dirty for next log read.
1126  *
1127  *   1. Take a snapshot of the bit and clear it if needed.
1128  *   2. Write protect the corresponding page.
1129  *   3. Copy the snapshot to the userspace.
1130  *   4. Flush TLB's if needed.
1131  */
1132 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
1133 {
1134         struct kvm_memslots *slots;
1135         struct kvm_memory_slot *memslot;
1136         bool is_dirty = false;
1137         int r;
1138
1139         mutex_lock(&kvm->slots_lock);
1140
1141         r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
1142
1143         if (is_dirty) {
1144                 slots = kvm_memslots(kvm);
1145                 memslot = id_to_memslot(slots, log->slot);
1146
1147                 /* Let implementation handle TLB/GVA invalidation */
1148                 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot);
1149         }
1150
1151         mutex_unlock(&kvm->slots_lock);
1152         return r;
1153 }
1154
1155 long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1156 {
1157         long r;
1158
1159         switch (ioctl) {
1160         default:
1161                 r = -ENOIOCTLCMD;
1162         }
1163
1164         return r;
1165 }
1166
1167 int kvm_arch_init(void *opaque)
1168 {
1169         if (kvm_mips_callbacks) {
1170                 kvm_err("kvm: module already exists\n");
1171                 return -EEXIST;
1172         }
1173
1174         return kvm_mips_emulation_init(&kvm_mips_callbacks);
1175 }
1176
1177 void kvm_arch_exit(void)
1178 {
1179         kvm_mips_callbacks = NULL;
1180 }
1181
1182 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1183                                   struct kvm_sregs *sregs)
1184 {
1185         return -ENOIOCTLCMD;
1186 }
1187
1188 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1189                                   struct kvm_sregs *sregs)
1190 {
1191         return -ENOIOCTLCMD;
1192 }
1193
1194 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1195 {
1196 }
1197
1198 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1199 {
1200         return -ENOIOCTLCMD;
1201 }
1202
1203 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1204 {
1205         return -ENOIOCTLCMD;
1206 }
1207
1208 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1209 {
1210         return VM_FAULT_SIGBUS;
1211 }
1212
1213 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1214 {
1215         int r;
1216
1217         switch (ext) {
1218         case KVM_CAP_ONE_REG:
1219         case KVM_CAP_ENABLE_CAP:
1220         case KVM_CAP_SYNC_MMU:
1221                 r = 1;
1222                 break;
1223         case KVM_CAP_COALESCED_MMIO:
1224                 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1225                 break;
1226         case KVM_CAP_MIPS_FPU:
1227                 /* We don't handle systems with inconsistent cpu_has_fpu */
1228                 r = !!raw_cpu_has_fpu;
1229                 break;
1230         case KVM_CAP_MIPS_MSA:
1231                 /*
1232                  * We don't support MSA vector partitioning yet:
1233                  * 1) It would require explicit support which can't be tested
1234                  *    yet due to lack of support in current hardware.
1235                  * 2) It extends the state that would need to be saved/restored
1236                  *    by e.g. QEMU for migration.
1237                  *
1238                  * When vector partitioning hardware becomes available, support
1239                  * could be added by requiring a flag when enabling
1240                  * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1241                  * to save/restore the appropriate extra state.
1242                  */
1243                 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1244                 break;
1245         default:
1246                 r = 0;
1247                 break;
1248         }
1249         return r;
1250 }
1251
1252 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1253 {
1254         return kvm_mips_pending_timer(vcpu);
1255 }
1256
1257 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1258 {
1259         int i;
1260         struct mips_coproc *cop0;
1261
1262         if (!vcpu)
1263                 return -1;
1264
1265         kvm_debug("VCPU Register Dump:\n");
1266         kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1267         kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1268
1269         for (i = 0; i < 32; i += 4) {
1270                 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1271                        vcpu->arch.gprs[i],
1272                        vcpu->arch.gprs[i + 1],
1273                        vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1274         }
1275         kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1276         kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1277
1278         cop0 = vcpu->arch.cop0;
1279         kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1280                   kvm_read_c0_guest_status(cop0),
1281                   kvm_read_c0_guest_cause(cop0));
1282
1283         kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1284
1285         return 0;
1286 }
1287
1288 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1289 {
1290         int i;
1291
1292         for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1293                 vcpu->arch.gprs[i] = regs->gpr[i];
1294         vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1295         vcpu->arch.hi = regs->hi;
1296         vcpu->arch.lo = regs->lo;
1297         vcpu->arch.pc = regs->pc;
1298
1299         return 0;
1300 }
1301
1302 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1303 {
1304         int i;
1305
1306         for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1307                 regs->gpr[i] = vcpu->arch.gprs[i];
1308
1309         regs->hi = vcpu->arch.hi;
1310         regs->lo = vcpu->arch.lo;
1311         regs->pc = vcpu->arch.pc;
1312
1313         return 0;
1314 }
1315
1316 static void kvm_mips_comparecount_func(unsigned long data)
1317 {
1318         struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1319
1320         kvm_mips_callbacks->queue_timer_int(vcpu);
1321
1322         vcpu->arch.wait = 0;
1323         if (swait_active(&vcpu->wq))
1324                 swake_up(&vcpu->wq);
1325 }
1326
1327 /* low level hrtimer wake routine */
1328 static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1329 {
1330         struct kvm_vcpu *vcpu;
1331
1332         vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1333         kvm_mips_comparecount_func((unsigned long) vcpu);
1334         return kvm_mips_count_timeout(vcpu);
1335 }
1336
1337 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1338 {
1339         int err;
1340
1341         err = kvm_mips_callbacks->vcpu_init(vcpu);
1342         if (err)
1343                 return err;
1344
1345         hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1346                      HRTIMER_MODE_REL);
1347         vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1348         return 0;
1349 }
1350
1351 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
1352 {
1353         kvm_mips_callbacks->vcpu_uninit(vcpu);
1354 }
1355
1356 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1357                                   struct kvm_translation *tr)
1358 {
1359         return 0;
1360 }
1361
1362 /* Initial guest state */
1363 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1364 {
1365         return kvm_mips_callbacks->vcpu_setup(vcpu);
1366 }
1367
1368 static void kvm_mips_set_c0_status(void)
1369 {
1370         u32 status = read_c0_status();
1371
1372         if (cpu_has_dsp)
1373                 status |= (ST0_MX);
1374
1375         write_c0_status(status);
1376         ehb();
1377 }
1378
1379 /*
1380  * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1381  */
1382 int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1383 {
1384         u32 cause = vcpu->arch.host_cp0_cause;
1385         u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1386         u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1387         unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1388         enum emulation_result er = EMULATE_DONE;
1389         u32 inst;
1390         int ret = RESUME_GUEST;
1391
1392         vcpu->mode = OUTSIDE_GUEST_MODE;
1393
1394         /* re-enable HTW before enabling interrupts */
1395         htw_start();
1396
1397         /* Set a default exit reason */
1398         run->exit_reason = KVM_EXIT_UNKNOWN;
1399         run->ready_for_interrupt_injection = 1;
1400
1401         /*
1402          * Set the appropriate status bits based on host CPU features,
1403          * before we hit the scheduler
1404          */
1405         kvm_mips_set_c0_status();
1406
1407         local_irq_enable();
1408
1409         kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1410                         cause, opc, run, vcpu);
1411         trace_kvm_exit(vcpu, exccode);
1412
1413         /*
1414          * Do a privilege check, if in UM most of these exit conditions end up
1415          * causing an exception to be delivered to the Guest Kernel
1416          */
1417         er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1418         if (er == EMULATE_PRIV_FAIL) {
1419                 goto skip_emul;
1420         } else if (er == EMULATE_FAIL) {
1421                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1422                 ret = RESUME_HOST;
1423                 goto skip_emul;
1424         }
1425
1426         switch (exccode) {
1427         case EXCCODE_INT:
1428                 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1429
1430                 ++vcpu->stat.int_exits;
1431
1432                 if (need_resched())
1433                         cond_resched();
1434
1435                 ret = RESUME_GUEST;
1436                 break;
1437
1438         case EXCCODE_CPU:
1439                 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1440
1441                 ++vcpu->stat.cop_unusable_exits;
1442                 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1443                 /* XXXKYMA: Might need to return to user space */
1444                 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1445                         ret = RESUME_HOST;
1446                 break;
1447
1448         case EXCCODE_MOD:
1449                 ++vcpu->stat.tlbmod_exits;
1450                 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1451                 break;
1452
1453         case EXCCODE_TLBS:
1454                 kvm_debug("TLB ST fault:  cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1455                           cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1456                           badvaddr);
1457
1458                 ++vcpu->stat.tlbmiss_st_exits;
1459                 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1460                 break;
1461
1462         case EXCCODE_TLBL:
1463                 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1464                           cause, opc, badvaddr);
1465
1466                 ++vcpu->stat.tlbmiss_ld_exits;
1467                 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1468                 break;
1469
1470         case EXCCODE_ADES:
1471                 ++vcpu->stat.addrerr_st_exits;
1472                 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1473                 break;
1474
1475         case EXCCODE_ADEL:
1476                 ++vcpu->stat.addrerr_ld_exits;
1477                 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1478                 break;
1479
1480         case EXCCODE_SYS:
1481                 ++vcpu->stat.syscall_exits;
1482                 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1483                 break;
1484
1485         case EXCCODE_RI:
1486                 ++vcpu->stat.resvd_inst_exits;
1487                 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1488                 break;
1489
1490         case EXCCODE_BP:
1491                 ++vcpu->stat.break_inst_exits;
1492                 ret = kvm_mips_callbacks->handle_break(vcpu);
1493                 break;
1494
1495         case EXCCODE_TR:
1496                 ++vcpu->stat.trap_inst_exits;
1497                 ret = kvm_mips_callbacks->handle_trap(vcpu);
1498                 break;
1499
1500         case EXCCODE_MSAFPE:
1501                 ++vcpu->stat.msa_fpe_exits;
1502                 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1503                 break;
1504
1505         case EXCCODE_FPE:
1506                 ++vcpu->stat.fpe_exits;
1507                 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1508                 break;
1509
1510         case EXCCODE_MSADIS:
1511                 ++vcpu->stat.msa_disabled_exits;
1512                 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1513                 break;
1514
1515         default:
1516                 if (cause & CAUSEF_BD)
1517                         opc += 1;
1518                 inst = 0;
1519                 kvm_get_badinstr(opc, vcpu, &inst);
1520                 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x  BadVaddr: %#lx Status: %#lx\n",
1521                         exccode, opc, inst, badvaddr,
1522                         kvm_read_c0_guest_status(vcpu->arch.cop0));
1523                 kvm_arch_vcpu_dump_regs(vcpu);
1524                 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1525                 ret = RESUME_HOST;
1526                 break;
1527
1528         }
1529
1530 skip_emul:
1531         local_irq_disable();
1532
1533         if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1534                 kvm_mips_deliver_interrupts(vcpu, cause);
1535
1536         if (!(ret & RESUME_HOST)) {
1537                 /* Only check for signals if not already exiting to userspace */
1538                 if (signal_pending(current)) {
1539                         run->exit_reason = KVM_EXIT_INTR;
1540                         ret = (-EINTR << 2) | RESUME_HOST;
1541                         ++vcpu->stat.signal_exits;
1542                         trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1543                 }
1544         }
1545
1546         if (ret == RESUME_GUEST) {
1547                 trace_kvm_reenter(vcpu);
1548
1549                 /*
1550                  * Make sure the read of VCPU requests in vcpu_reenter()
1551                  * callback is not reordered ahead of the write to vcpu->mode,
1552                  * or we could miss a TLB flush request while the requester sees
1553                  * the VCPU as outside of guest mode and not needing an IPI.
1554                  */
1555                 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
1556
1557                 kvm_mips_callbacks->vcpu_reenter(run, vcpu);
1558
1559                 /*
1560                  * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1561                  * is live), restore FCR31 / MSACSR.
1562                  *
1563                  * This should be before returning to the guest exception
1564                  * vector, as it may well cause an [MSA] FP exception if there
1565                  * are pending exception bits unmasked. (see
1566                  * kvm_mips_csr_die_notifier() for how that is handled).
1567                  */
1568                 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1569                     read_c0_status() & ST0_CU1)
1570                         __kvm_restore_fcsr(&vcpu->arch);
1571
1572                 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1573                     read_c0_config5() & MIPS_CONF5_MSAEN)
1574                         __kvm_restore_msacsr(&vcpu->arch);
1575         }
1576
1577         /* Disable HTW before returning to guest or host */
1578         htw_stop();
1579
1580         return ret;
1581 }
1582
1583 /* Enable FPU for guest and restore context */
1584 void kvm_own_fpu(struct kvm_vcpu *vcpu)
1585 {
1586         struct mips_coproc *cop0 = vcpu->arch.cop0;
1587         unsigned int sr, cfg5;
1588
1589         preempt_disable();
1590
1591         sr = kvm_read_c0_guest_status(cop0);
1592
1593         /*
1594          * If MSA state is already live, it is undefined how it interacts with
1595          * FR=0 FPU state, and we don't want to hit reserved instruction
1596          * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1597          * play it safe and save it first.
1598          *
1599          * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1600          * get called when guest CU1 is set, however we can't trust the guest
1601          * not to clobber the status register directly via the commpage.
1602          */
1603         if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1604             vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1605                 kvm_lose_fpu(vcpu);
1606
1607         /*
1608          * Enable FPU for guest
1609          * We set FR and FRE according to guest context
1610          */
1611         change_c0_status(ST0_CU1 | ST0_FR, sr);
1612         if (cpu_has_fre) {
1613                 cfg5 = kvm_read_c0_guest_config5(cop0);
1614                 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1615         }
1616         enable_fpu_hazard();
1617
1618         /* If guest FPU state not active, restore it now */
1619         if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1620                 __kvm_restore_fpu(&vcpu->arch);
1621                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1622                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1623         } else {
1624                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1625         }
1626
1627         preempt_enable();
1628 }
1629
1630 #ifdef CONFIG_CPU_HAS_MSA
1631 /* Enable MSA for guest and restore context */
1632 void kvm_own_msa(struct kvm_vcpu *vcpu)
1633 {
1634         struct mips_coproc *cop0 = vcpu->arch.cop0;
1635         unsigned int sr, cfg5;
1636
1637         preempt_disable();
1638
1639         /*
1640          * Enable FPU if enabled in guest, since we're restoring FPU context
1641          * anyway. We set FR and FRE according to guest context.
1642          */
1643         if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1644                 sr = kvm_read_c0_guest_status(cop0);
1645
1646                 /*
1647                  * If FR=0 FPU state is already live, it is undefined how it
1648                  * interacts with MSA state, so play it safe and save it first.
1649                  */
1650                 if (!(sr & ST0_FR) &&
1651                     (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1652                                 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1653                         kvm_lose_fpu(vcpu);
1654
1655                 change_c0_status(ST0_CU1 | ST0_FR, sr);
1656                 if (sr & ST0_CU1 && cpu_has_fre) {
1657                         cfg5 = kvm_read_c0_guest_config5(cop0);
1658                         change_c0_config5(MIPS_CONF5_FRE, cfg5);
1659                 }
1660         }
1661
1662         /* Enable MSA for guest */
1663         set_c0_config5(MIPS_CONF5_MSAEN);
1664         enable_fpu_hazard();
1665
1666         switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1667         case KVM_MIPS_AUX_FPU:
1668                 /*
1669                  * Guest FPU state already loaded, only restore upper MSA state
1670                  */
1671                 __kvm_restore_msa_upper(&vcpu->arch);
1672                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1673                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1674                 break;
1675         case 0:
1676                 /* Neither FPU or MSA already active, restore full MSA state */
1677                 __kvm_restore_msa(&vcpu->arch);
1678                 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1679                 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1680                         vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1681                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1682                               KVM_TRACE_AUX_FPU_MSA);
1683                 break;
1684         default:
1685                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1686                 break;
1687         }
1688
1689         preempt_enable();
1690 }
1691 #endif
1692
1693 /* Drop FPU & MSA without saving it */
1694 void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1695 {
1696         preempt_disable();
1697         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1698                 disable_msa();
1699                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1700                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1701         }
1702         if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1703                 clear_c0_status(ST0_CU1 | ST0_FR);
1704                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1705                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1706         }
1707         preempt_enable();
1708 }
1709
1710 /* Save and disable FPU & MSA */
1711 void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1712 {
1713         /*
1714          * FPU & MSA get disabled in root context (hardware) when it is disabled
1715          * in guest context (software), but the register state in the hardware
1716          * may still be in use. This is why we explicitly re-enable the hardware
1717          * before saving.
1718          */
1719
1720         preempt_disable();
1721         if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1722                 set_c0_config5(MIPS_CONF5_MSAEN);
1723                 enable_fpu_hazard();
1724
1725                 __kvm_save_msa(&vcpu->arch);
1726                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1727
1728                 /* Disable MSA & FPU */
1729                 disable_msa();
1730                 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1731                         clear_c0_status(ST0_CU1 | ST0_FR);
1732                         disable_fpu_hazard();
1733                 }
1734                 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1735         } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1736                 set_c0_status(ST0_CU1);
1737                 enable_fpu_hazard();
1738
1739                 __kvm_save_fpu(&vcpu->arch);
1740                 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1741                 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1742
1743                 /* Disable FPU */
1744                 clear_c0_status(ST0_CU1 | ST0_FR);
1745                 disable_fpu_hazard();
1746         }
1747         preempt_enable();
1748 }
1749
1750 /*
1751  * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1752  * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1753  * exception if cause bits are set in the value being written.
1754  */
1755 static int kvm_mips_csr_die_notify(struct notifier_block *self,
1756                                    unsigned long cmd, void *ptr)
1757 {
1758         struct die_args *args = (struct die_args *)ptr;
1759         struct pt_regs *regs = args->regs;
1760         unsigned long pc;
1761
1762         /* Only interested in FPE and MSAFPE */
1763         if (cmd != DIE_FP && cmd != DIE_MSAFP)
1764                 return NOTIFY_DONE;
1765
1766         /* Return immediately if guest context isn't active */
1767         if (!(current->flags & PF_VCPU))
1768                 return NOTIFY_DONE;
1769
1770         /* Should never get here from user mode */
1771         BUG_ON(user_mode(regs));
1772
1773         pc = instruction_pointer(regs);
1774         switch (cmd) {
1775         case DIE_FP:
1776                 /* match 2nd instruction in __kvm_restore_fcsr */
1777                 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1778                         return NOTIFY_DONE;
1779                 break;
1780         case DIE_MSAFP:
1781                 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1782                 if (!cpu_has_msa ||
1783                     pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1784                     pc > (unsigned long)&__kvm_restore_msacsr + 8)
1785                         return NOTIFY_DONE;
1786                 break;
1787         }
1788
1789         /* Move PC forward a little and continue executing */
1790         instruction_pointer(regs) += 4;
1791
1792         return NOTIFY_STOP;
1793 }
1794
1795 static struct notifier_block kvm_mips_csr_die_notifier = {
1796         .notifier_call = kvm_mips_csr_die_notify,
1797 };
1798
1799 static int __init kvm_mips_init(void)
1800 {
1801         int ret;
1802
1803         ret = kvm_mips_entry_setup();
1804         if (ret)
1805                 return ret;
1806
1807         ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1808
1809         if (ret)
1810                 return ret;
1811
1812         register_die_notifier(&kvm_mips_csr_die_notifier);
1813
1814         return 0;
1815 }
1816
1817 static void __exit kvm_mips_exit(void)
1818 {
1819         kvm_exit();
1820
1821         unregister_die_notifier(&kvm_mips_csr_die_notifier);
1822 }
1823
1824 module_init(kvm_mips_init);
1825 module_exit(kvm_mips_exit);
1826
1827 EXPORT_TRACEPOINT_SYMBOL(kvm_exit);