arch/mips/lantiq/xway/sysctrl.c

   1 /*
   2  *  This program is free software; you can redistribute it and/or modify it
   3  *  under the terms of the GNU General Public License version 2 as published
   4  *  by the Free Software Foundation.
   5  *
   6  *  Copyright (C) 2011-2012 John Crispin <blogic@openwrt.org>
   7  *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
   8  */
   9
  10 #include <linux/ioport.h>
  11 #include <linux/export.h>
  12 #include <linux/clkdev.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/of.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/of_address.h>
  17
  18 #include <lantiq_soc.h>
  19
  20 #include "../clk.h"
  21 #include "../prom.h"
  22
  23 /* clock control register for legacy */
  24 #define CGU_IFCCR       0x0018
  25 #define CGU_IFCCR_VR9   0x0024
  26 /* system clock register for legacy */
  27 #define CGU_SYS         0x0010
  28 /* pci control register */
  29 #define CGU_PCICR       0x0034
  30 #define CGU_PCICR_VR9   0x0038
  31 /* ephy configuration register */
  32 #define CGU_EPHY        0x10
  33
  34 /* Legacy PMU register for ar9, ase, danube */
  35 /* power control register */
  36 #define PMU_PWDCR       0x1C
  37 /* power status register */
  38 #define PMU_PWDSR       0x20
  39 /* power control register */
  40 #define PMU_PWDCR1      0x24
  41 /* power status register */
  42 #define PMU_PWDSR1      0x28
  43 /* power control register */
  44 #define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR))
  45 /* power status register */
  46 #define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
  47
  48
  49 /* PMU register for ar10 and grx390 */
  50
  51 /* First register set */
  52 #define PMU_CLK_SR      0x20 /* status */
  53 #define PMU_CLK_CR_A    0x24 /* Enable */
  54 #define PMU_CLK_CR_B    0x28 /* Disable */
  55 /* Second register set */
  56 #define PMU_CLK_SR1     0x30 /* status */
  57 #define PMU_CLK_CR1_A   0x34 /* Enable */
  58 #define PMU_CLK_CR1_B   0x38 /* Disable */
  59 /* Third register set */
  60 #define PMU_ANA_SR      0x40 /* status */
  61 #define PMU_ANA_CR_A    0x44 /* Enable */
  62 #define PMU_ANA_CR_B    0x48 /* Disable */
  63
  64 /* Status */
  65 static u32 pmu_clk_sr[] = {
  66         PMU_CLK_SR,
  67         PMU_CLK_SR1,
  68         PMU_ANA_SR,
  69 };
  70
  71 /* Enable */
  72 static u32 pmu_clk_cr_a[] = {
  73         PMU_CLK_CR_A,
  74         PMU_CLK_CR1_A,
  75         PMU_ANA_CR_A,
  76 };
  77
  78 /* Disable */
  79 static u32 pmu_clk_cr_b[] = {
  80         PMU_CLK_CR_B,
  81         PMU_CLK_CR1_B,
  82         PMU_ANA_CR_B,
  83 };
  84
  85 #define PWDCR_EN_XRX(x)         (pmu_clk_cr_a[(x)])
  86 #define PWDCR_DIS_XRX(x)        (pmu_clk_cr_b[(x)])
  87 #define PWDSR_XRX(x)            (pmu_clk_sr[(x)])
  88
  89 /* clock gates that we can en/disable */
  90 #define PMU_USB0_P      BIT(0)
  91 #define PMU_ASE_SDIO    BIT(2) /* ASE special */
  92 #define PMU_PCI         BIT(4)
  93 #define PMU_DMA         BIT(5)
  94 #define PMU_USB0        BIT(6)
  95 #define PMU_ASC0        BIT(7)
  96 #define PMU_EPHY        BIT(7)  /* ase */
  97 #define PMU_USIF        BIT(7) /* from vr9 until grx390 */
  98 #define PMU_SPI         BIT(8)
  99 #define PMU_DFE         BIT(9)
 100 #define PMU_EBU         BIT(10)
 101 #define PMU_STP         BIT(11)
 102 #define PMU_GPT         BIT(12)
 103 #define PMU_AHBS        BIT(13) /* vr9 */
 104 #define PMU_FPI         BIT(14)
 105 #define PMU_AHBM        BIT(15)
 106 #define PMU_SDIO        BIT(16) /* danube, ar9, vr9 */
 107 #define PMU_ASC1        BIT(17)
 108 #define PMU_PPE_QSB     BIT(18)
 109 #define PMU_PPE_SLL01   BIT(19)
 110 #define PMU_PPE_TC      BIT(21)
 111 #define PMU_PPE_EMA     BIT(22)
 112 #define PMU_PPE_DPLUM   BIT(23)
 113 #define PMU_PPE_DP      BIT(23)
 114 #define PMU_PPE_DPLUS   BIT(24)
 115 #define PMU_USB1_P      BIT(26)
 116 #define PMU_USB1        BIT(27)
 117 #define PMU_SWITCH      BIT(28)
 118 #define PMU_PPE_TOP     BIT(29)
 119 #define PMU_GPHY        BIT(30)
 120 #define PMU_PCIE_CLK    BIT(31)
 121
 122 #define PMU1_PCIE_PHY   BIT(0)  /* vr9-specific,moved in ar10/grx390 */
 123 #define PMU1_PCIE_CTL   BIT(1)
 124 #define PMU1_PCIE_PDI   BIT(4)
 125 #define PMU1_PCIE_MSI   BIT(5)
 126 #define PMU1_CKE        BIT(6)
 127 #define PMU1_PCIE1_CTL  BIT(17)
 128 #define PMU1_PCIE1_PDI  BIT(20)
 129 #define PMU1_PCIE1_MSI  BIT(21)
 130 #define PMU1_PCIE2_CTL  BIT(25)
 131 #define PMU1_PCIE2_PDI  BIT(26)
 132 #define PMU1_PCIE2_MSI  BIT(27)
 133
 134 #define PMU_ANALOG_USB0_P       BIT(0)
 135 #define PMU_ANALOG_USB1_P       BIT(1)
 136 #define PMU_ANALOG_PCIE0_P      BIT(8)
 137 #define PMU_ANALOG_PCIE1_P      BIT(9)
 138 #define PMU_ANALOG_PCIE2_P      BIT(10)
 139 #define PMU_ANALOG_DSL_AFE      BIT(16)
 140 #define PMU_ANALOG_DCDC_2V5     BIT(17)
 141 #define PMU_ANALOG_DCDC_1VX     BIT(18)
 142 #define PMU_ANALOG_DCDC_1V0     BIT(19)
 143
 144 #define pmu_w32(x, y)   ltq_w32((x), pmu_membase + (y))
 145 #define pmu_r32(x)      ltq_r32(pmu_membase + (x))
 146
 147 static void __iomem *pmu_membase;
 148 void __iomem *ltq_cgu_membase;
 149 void __iomem *ltq_ebu_membase;
 150
 151 static u32 ifccr = CGU_IFCCR;
 152 static u32 pcicr = CGU_PCICR;
 153
 154 static DEFINE_SPINLOCK(g_pmu_lock);
 155
 156 /* legacy function kept alive to ease clkdev transition */
 157 void ltq_pmu_enable(unsigned int module)
 158 {
 159         int retry = 1000000;
 160
 161         spin_lock(&g_pmu_lock);
 162         pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR);
 163         do {} while (--retry && (pmu_r32(PMU_PWDSR) & module));
 164         spin_unlock(&g_pmu_lock);
 165
 166         if (!retry)
 167                 panic("activating PMU module failed!");
 168 }
 169 EXPORT_SYMBOL(ltq_pmu_enable);
 170
 171 /* legacy function kept alive to ease clkdev transition */
 172 void ltq_pmu_disable(unsigned int module)
 173 {
 174         int retry = 1000000;
 175
 176         spin_lock(&g_pmu_lock);
 177         pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR);
 178         do {} while (--retry && (!(pmu_r32(PMU_PWDSR) & module)));
 179         spin_unlock(&g_pmu_lock);
 180
 181         if (!retry)
 182                 pr_warn("deactivating PMU module failed!");
 183 }
 184 EXPORT_SYMBOL(ltq_pmu_disable);
 185
 186 /* enable a hw clock */
 187 static int cgu_enable(struct clk *clk)
 188 {
 189         ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr);
 190         return 0;
 191 }
 192
 193 /* disable a hw clock */
 194 static void cgu_disable(struct clk *clk)
 195 {
 196         ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr);
 197 }
 198
 199 /* enable a clock gate */
 200 static int pmu_enable(struct clk *clk)
 201 {
 202         int retry = 1000000;
 203
 204         if (of_machine_is_compatible("lantiq,ar10")
 205             || of_machine_is_compatible("lantiq,grx390")) {
 206                 pmu_w32(clk->bits, PWDCR_EN_XRX(clk->module));
 207                 do {} while (--retry &&
 208                              (!(pmu_r32(PWDSR_XRX(clk->module)) & clk->bits)));
 209
 210         } else {
 211                 spin_lock(&g_pmu_lock);
 212                 pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits,
 213                                 PWDCR(clk->module));
 214                 do {} while (--retry &&
 215                              (pmu_r32(PWDSR(clk->module)) & clk->bits));
 216                 spin_unlock(&g_pmu_lock);
 217         }
 218
 219         if (!retry)
 220                 panic("activating PMU module failed!");
 221
 222         return 0;
 223 }
 224
 225 /* disable a clock gate */
 226 static void pmu_disable(struct clk *clk)
 227 {
 228         int retry = 1000000;
 229
 230         if (of_machine_is_compatible("lantiq,ar10")
 231             || of_machine_is_compatible("lantiq,grx390")) {
 232                 pmu_w32(clk->bits, PWDCR_DIS_XRX(clk->module));
 233                 do {} while (--retry &&
 234                              (pmu_r32(PWDSR_XRX(clk->module)) & clk->bits));
 235         } else {
 236                 spin_lock(&g_pmu_lock);
 237                 pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits,
 238                                 PWDCR(clk->module));
 239                 do {} while (--retry &&
 240                              (!(pmu_r32(PWDSR(clk->module)) & clk->bits)));
 241                 spin_unlock(&g_pmu_lock);
 242         }
 243
 244         if (!retry)
 245                 pr_warn("deactivating PMU module failed!");
 246 }
 247
 248 /* the pci enable helper */
 249 static int pci_enable(struct clk *clk)
 250 {
 251         unsigned int val = ltq_cgu_r32(ifccr);
 252         /* set bus clock speed */
 253         if (of_machine_is_compatible("lantiq,ar9") ||
 254                         of_machine_is_compatible("lantiq,vr9")) {
 255                 val &= ~0x1f00000;
 256                 if (clk->rate == CLOCK_33M)
 257                         val |= 0xe00000;
 258                 else
 259                         val |= 0x700000; /* 62.5M */
 260         } else {
 261                 val &= ~0xf00000;
 262                 if (clk->rate == CLOCK_33M)
 263                         val |= 0x800000;
 264                 else
 265                         val |= 0x400000; /* 62.5M */
 266         }
 267         ltq_cgu_w32(val, ifccr);
 268         pmu_enable(clk);
 269         return 0;
 270 }
 271
 272 /* enable the external clock as a source */
 273 static int pci_ext_enable(struct clk *clk)
 274 {
 275         ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr);
 276         ltq_cgu_w32((1 << 30), pcicr);
 277         return 0;
 278 }
 279
 280 /* disable the external clock as a source */
 281 static void pci_ext_disable(struct clk *clk)
 282 {
 283         ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr);
 284         ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
 285 }
 286
 287 /* enable a clockout source */
 288 static int clkout_enable(struct clk *clk)
 289 {
 290         int i;
 291
 292         /* get the correct rate */
 293         for (i = 0; i < 4; i++) {
 294                 if (clk->rates[i] == clk->rate) {
 295                         int shift = 14 - (2 * clk->module);
 296                         int enable = 7 - clk->module;
 297                         unsigned int val = ltq_cgu_r32(ifccr);
 298
 299                         val &= ~(3 << shift);
 300                         val |= i << shift;
 301                         val |= enable;
 302                         ltq_cgu_w32(val, ifccr);
 303                         return 0;
 304                 }
 305         }
 306         return -1;
 307 }
 308
 309 /* manage the clock gates via PMU */
 310 static void clkdev_add_pmu(const char *dev, const char *con, bool deactivate,
 311                            unsigned int module, unsigned int bits)
 312 {
 313         struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 314
 315         clk->cl.dev_id = dev;
 316         clk->cl.con_id = con;
 317         clk->cl.clk = clk;
 318         clk->enable = pmu_enable;
 319         clk->disable = pmu_disable;
 320         clk->module = module;
 321         clk->bits = bits;
 322         if (deactivate) {
 323                 /*
 324                  * Disable it during the initialization. Module should enable
 325                  * when used
 326                  */
 327                 pmu_disable(clk);
 328         }
 329         clkdev_add(&clk->cl);
 330 }
 331
 332 /* manage the clock generator */
 333 static void clkdev_add_cgu(const char *dev, const char *con,
 334                                         unsigned int bits)
 335 {
 336         struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 337
 338         clk->cl.dev_id = dev;
 339         clk->cl.con_id = con;
 340         clk->cl.clk = clk;
 341         clk->enable = cgu_enable;
 342         clk->disable = cgu_disable;
 343         clk->bits = bits;
 344         clkdev_add(&clk->cl);
 345 }
 346
 347 /* pci needs its own enable function as the setup is a bit more complex */
 348 static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0};
 349
 350 static void clkdev_add_pci(void)
 351 {
 352         struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 353         struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL);
 354
 355         /* main pci clock */
 356         clk->cl.dev_id = "17000000.pci";
 357         clk->cl.con_id = NULL;
 358         clk->cl.clk = clk;
 359         clk->rate = CLOCK_33M;
 360         clk->rates = valid_pci_rates;
 361         clk->enable = pci_enable;
 362         clk->disable = pmu_disable;
 363         clk->module = 0;
 364         clk->bits = PMU_PCI;
 365         clkdev_add(&clk->cl);
 366
 367         /* use internal/external bus clock */
 368         clk_ext->cl.dev_id = "17000000.pci";
 369         clk_ext->cl.con_id = "external";
 370         clk_ext->cl.clk = clk_ext;
 371         clk_ext->enable = pci_ext_enable;
 372         clk_ext->disable = pci_ext_disable;
 373         clkdev_add(&clk_ext->cl);
 374 }
 375
 376 /* xway socs can generate clocks on gpio pins */
 377 static unsigned long valid_clkout_rates[4][5] = {
 378         {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0},
 379         {CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0},
 380         {CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0},
 381         {CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0},
 382 };
 383
 384 static void clkdev_add_clkout(void)
 385 {
 386         int i;
 387
 388         for (i = 0; i < 4; i++) {
 389                 struct clk *clk;
 390                 char *name;
 391
 392                 name = kzalloc(sizeof("clkout0"), GFP_KERNEL);
 393                 sprintf(name, "clkout%d", i);
 394
 395                 clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
 396                 clk->cl.dev_id = "1f103000.cgu";
 397                 clk->cl.con_id = name;
 398                 clk->cl.clk = clk;
 399                 clk->rate = 0;
 400                 clk->rates = valid_clkout_rates[i];
 401                 clk->enable = clkout_enable;
 402                 clk->module = i;
 403                 clkdev_add(&clk->cl);
 404         }
 405 }
 406
 407 /* bring up all register ranges that we need for basic system control */
 408 void __init ltq_soc_init(void)
 409 {
 410         struct resource res_pmu, res_cgu, res_ebu;
 411         struct device_node *np_pmu =
 412                         of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway");
 413         struct device_node *np_cgu =
 414                         of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway");
 415         struct device_node *np_ebu =
 416                         of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway");
 417
 418         /* check if all the core register ranges are available */
 419         if (!np_pmu || !np_cgu || !np_ebu)
 420                 panic("Failed to load core nodes from devicetree");
 421
 422         if (of_address_to_resource(np_pmu, 0, &res_pmu) ||
 423                         of_address_to_resource(np_cgu, 0, &res_cgu) ||
 424                         of_address_to_resource(np_ebu, 0, &res_ebu))
 425                 panic("Failed to get core resources");
 426
 427         if ((request_mem_region(res_pmu.start, resource_size(&res_pmu),
 428                                 res_pmu.name) < 0) ||
 429                 (request_mem_region(res_cgu.start, resource_size(&res_cgu),
 430                                 res_cgu.name) < 0) ||
 431                 (request_mem_region(res_ebu.start, resource_size(&res_ebu),
 432                                 res_ebu.name) < 0))
 433                 pr_err("Failed to request core resources");
 434
 435         pmu_membase = ioremap_nocache(res_pmu.start, resource_size(&res_pmu));
 436         ltq_cgu_membase = ioremap_nocache(res_cgu.start,
 437                                                 resource_size(&res_cgu));
 438         ltq_ebu_membase = ioremap_nocache(res_ebu.start,
 439                                                 resource_size(&res_ebu));
 440         if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
 441                 panic("Failed to remap core resources");
 442
 443         /* make sure to unprotect the memory region where flash is located */
 444         ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
 445
 446         /* add our generic xway clocks */
 447         clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI);
 448         clkdev_add_pmu("1e100400.serial", NULL, 0, 0, PMU_ASC0);
 449         clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT);
 450         clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP);
 451         clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA);
 452         clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI);
 453         clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU);
 454         clkdev_add_clkout();
 455
 456         /* add the soc dependent clocks */
 457         if (of_machine_is_compatible("lantiq,vr9")) {
 458                 ifccr = CGU_IFCCR_VR9;
 459                 pcicr = CGU_PCICR_VR9;
 460         } else {
 461                 clkdev_add_pmu("1e180000.etop", NULL, 1, 0, PMU_PPE);
 462         }
 463
 464         if (!of_machine_is_compatible("lantiq,ase")) {
 465                 clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
 466                 clkdev_add_pci();
 467         }
 468
 469         if (of_machine_is_compatible("lantiq,grx390") ||
 470             of_machine_is_compatible("lantiq,ar10")) {
 471                 clkdev_add_pmu("1e101000.usb", "phy", 1, 2, PMU_ANALOG_USB0_P);
 472                 clkdev_add_pmu("1e106000.usb", "phy", 1, 2, PMU_ANALOG_USB1_P);
 473                 /* rc 0 */
 474                 clkdev_add_pmu("1d900000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
 475                 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
 476                 clkdev_add_pmu("1d900000.pcie", "pdi", 1, 1, PMU1_PCIE_PDI);
 477                 clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
 478                 /* rc 1 */
 479                 clkdev_add_pmu("19000000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE1_P);
 480                 clkdev_add_pmu("19000000.pcie", "msi", 1, 1, PMU1_PCIE1_MSI);
 481                 clkdev_add_pmu("19000000.pcie", "pdi", 1, 1, PMU1_PCIE1_PDI);
 482                 clkdev_add_pmu("19000000.pcie", "ctl", 1, 1, PMU1_PCIE1_CTL);
 483         }
 484
 485         if (of_machine_is_compatible("lantiq,ase")) {
 486                 if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
 487                         clkdev_add_static(CLOCK_266M, CLOCK_133M,
 488                                                 CLOCK_133M, CLOCK_266M);
 489                 else
 490                         clkdev_add_static(CLOCK_133M, CLOCK_133M,
 491                                                 CLOCK_133M, CLOCK_133M);
 492                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
 493                 clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
 494                 clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
 495                 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
 496                 clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
 497                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_ASE_SDIO);
 498         } else if (of_machine_is_compatible("lantiq,grx390")) {
 499                 clkdev_add_static(ltq_grx390_cpu_hz(), ltq_grx390_fpi_hz(),
 500                                   ltq_grx390_fpi_hz(), ltq_grx390_pp32_hz());
 501                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
 502                 clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
 503                 /* rc 2 */
 504                 clkdev_add_pmu("1a800000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE2_P);
 505                 clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI);
 506                 clkdev_add_pmu("1a800000.pcie", "pdi", 1, 1, PMU1_PCIE2_PDI);
 507                 clkdev_add_pmu("1a800000.pcie", "ctl", 1, 1, PMU1_PCIE2_CTL);
 508                 clkdev_add_pmu("1e108000.eth", NULL, 1, 0, PMU_SWITCH | PMU_PPE_DP);
 509                 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
 510         } else if (of_machine_is_compatible("lantiq,ar10")) {
 511                 clkdev_add_static(ltq_ar10_cpu_hz(), ltq_ar10_fpi_hz(),
 512                                   ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz());
 513                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
 514                 clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
 515                 clkdev_add_pmu("1e108000.eth", NULL, 1, 0, PMU_SWITCH |
 516                                PMU_PPE_DP | PMU_PPE_TC);
 517                 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
 518                 clkdev_add_pmu("1f203000.rcu", "gphy", 1, 0, PMU_GPHY);
 519         } else if (of_machine_is_compatible("lantiq,vr9")) {
 520                 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
 521                                 ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
 522                 clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
 523                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0 | PMU_AHBM);
 524                 clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
 525                 clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1 | PMU_AHBM);
 526                 clkdev_add_pmu("1d900000.pcie", "phy", 1, 1, PMU1_PCIE_PHY);
 527                 clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
 528                 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
 529                 clkdev_add_pmu("1d900000.pcie", "pdi", 1, 1, PMU1_PCIE_PDI);
 530                 clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
 531                 clkdev_add_pmu("1d900000.pcie", "ahb", 1, 0, PMU_AHBM | PMU_AHBS);
 532
 533                 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
 534                 clkdev_add_pmu("1e108000.eth", NULL, 1, 0,
 535                                 PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
 536                                 PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
 537                                 PMU_PPE_QSB | PMU_PPE_TOP);
 538                 clkdev_add_pmu("1f203000.rcu", "gphy", 1, 0, PMU_GPHY);
 539                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
 540         } else if (of_machine_is_compatible("lantiq,ar9")) {
 541                 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
 542                                 ltq_ar9_fpi_hz(), CLOCK_250M);
 543                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
 544                 clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
 545                 clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
 546                 clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
 547                 clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
 548                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
 549         } else {
 550                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
 551                                 ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
 552                 clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
 553                 clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
 554                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
 555         }
 556 }