2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 #include <linux/hardirq.h>
11 #include <linux/init.h>
12 #include <linux/highmem.h>
13 #include <linux/kernel.h>
14 #include <linux/linkage.h>
15 #include <linux/sched.h>
16 #include <linux/smp.h>
18 #include <linux/module.h>
19 #include <linux/bitops.h>
21 #include <asm/bcache.h>
22 #include <asm/bootinfo.h>
23 #include <asm/cache.h>
24 #include <asm/cacheops.h>
26 #include <asm/cpu-features.h>
29 #include <asm/pgtable.h>
30 #include <asm/r4kcache.h>
31 #include <asm/sections.h>
32 #include <asm/mmu_context.h>
34 #include <asm/cacheflush.h> /* for run_uncached() */
35 #include <asm/traps.h>
38 * Special Variant of smp_call_function for use by cache functions:
41 * o collapses to normal function call on UP kernels
42 * o collapses to normal function call on systems with a single shared
44 * o doesn't disable interrupts on the local CPU
46 static inline void r4k_on_each_cpu(void (*func) (void *info), void *info)
50 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
51 smp_call_function(func, info, 1);
57 #if defined(CONFIG_MIPS_CMP)
58 #define cpu_has_safe_index_cacheops 0
60 #define cpu_has_safe_index_cacheops 1
66 static unsigned long icache_size __read_mostly;
67 static unsigned long dcache_size __read_mostly;
68 static unsigned long scache_size __read_mostly;
71 * Dummy cache handling routines for machines without boardcaches
73 static void cache_noop(void) {}
75 static struct bcache_ops no_sc_ops = {
76 .bc_enable = (void *)cache_noop,
77 .bc_disable = (void *)cache_noop,
78 .bc_wback_inv = (void *)cache_noop,
79 .bc_inv = (void *)cache_noop
82 struct bcache_ops *bcops = &no_sc_ops;
84 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
85 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
87 #define R4600_HIT_CACHEOP_WAR_IMPL \
89 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
90 *(volatile unsigned long *)CKSEG1; \
91 if (R4600_V1_HIT_CACHEOP_WAR) \
92 __asm__ __volatile__("nop;nop;nop;nop"); \
95 static void (*r4k_blast_dcache_page)(unsigned long addr);
97 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
99 R4600_HIT_CACHEOP_WAR_IMPL;
100 blast_dcache32_page(addr);
103 static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
105 R4600_HIT_CACHEOP_WAR_IMPL;
106 blast_dcache64_page(addr);
109 static void __cpuinit r4k_blast_dcache_page_setup(void)
111 unsigned long dc_lsize = cpu_dcache_line_size();
114 r4k_blast_dcache_page = (void *)cache_noop;
115 else if (dc_lsize == 16)
116 r4k_blast_dcache_page = blast_dcache16_page;
117 else if (dc_lsize == 32)
118 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
119 else if (dc_lsize == 64)
120 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
123 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
125 static void __cpuinit r4k_blast_dcache_page_indexed_setup(void)
127 unsigned long dc_lsize = cpu_dcache_line_size();
130 r4k_blast_dcache_page_indexed = (void *)cache_noop;
131 else if (dc_lsize == 16)
132 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
133 else if (dc_lsize == 32)
134 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
135 else if (dc_lsize == 64)
136 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
139 static void (* r4k_blast_dcache)(void);
141 static void __cpuinit r4k_blast_dcache_setup(void)
143 unsigned long dc_lsize = cpu_dcache_line_size();
146 r4k_blast_dcache = (void *)cache_noop;
147 else if (dc_lsize == 16)
148 r4k_blast_dcache = blast_dcache16;
149 else if (dc_lsize == 32)
150 r4k_blast_dcache = blast_dcache32;
151 else if (dc_lsize == 64)
152 r4k_blast_dcache = blast_dcache64;
155 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
156 #define JUMP_TO_ALIGN(order) \
157 __asm__ __volatile__( \
159 ".align\t" #order "\n\t" \
162 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
163 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
165 static inline void blast_r4600_v1_icache32(void)
169 local_irq_save(flags);
171 local_irq_restore(flags);
174 static inline void tx49_blast_icache32(void)
176 unsigned long start = INDEX_BASE;
177 unsigned long end = start + current_cpu_data.icache.waysize;
178 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
179 unsigned long ws_end = current_cpu_data.icache.ways <<
180 current_cpu_data.icache.waybit;
181 unsigned long ws, addr;
183 CACHE32_UNROLL32_ALIGN2;
184 /* I'm in even chunk. blast odd chunks */
185 for (ws = 0; ws < ws_end; ws += ws_inc)
186 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
187 cache32_unroll32(addr|ws, Index_Invalidate_I);
188 CACHE32_UNROLL32_ALIGN;
189 /* I'm in odd chunk. blast even chunks */
190 for (ws = 0; ws < ws_end; ws += ws_inc)
191 for (addr = start; addr < end; addr += 0x400 * 2)
192 cache32_unroll32(addr|ws, Index_Invalidate_I);
195 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
199 local_irq_save(flags);
200 blast_icache32_page_indexed(page);
201 local_irq_restore(flags);
204 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
206 unsigned long indexmask = current_cpu_data.icache.waysize - 1;
207 unsigned long start = INDEX_BASE + (page & indexmask);
208 unsigned long end = start + PAGE_SIZE;
209 unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
210 unsigned long ws_end = current_cpu_data.icache.ways <<
211 current_cpu_data.icache.waybit;
212 unsigned long ws, addr;
214 CACHE32_UNROLL32_ALIGN2;
215 /* I'm in even chunk. blast odd chunks */
216 for (ws = 0; ws < ws_end; ws += ws_inc)
217 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
218 cache32_unroll32(addr|ws, Index_Invalidate_I);
219 CACHE32_UNROLL32_ALIGN;
220 /* I'm in odd chunk. blast even chunks */
221 for (ws = 0; ws < ws_end; ws += ws_inc)
222 for (addr = start; addr < end; addr += 0x400 * 2)
223 cache32_unroll32(addr|ws, Index_Invalidate_I);
226 static void (* r4k_blast_icache_page)(unsigned long addr);
228 static void __cpuinit r4k_blast_icache_page_setup(void)
230 unsigned long ic_lsize = cpu_icache_line_size();
233 r4k_blast_icache_page = (void *)cache_noop;
234 else if (ic_lsize == 16)
235 r4k_blast_icache_page = blast_icache16_page;
236 else if (ic_lsize == 32)
237 r4k_blast_icache_page = blast_icache32_page;
238 else if (ic_lsize == 64)
239 r4k_blast_icache_page = blast_icache64_page;
243 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
245 static void __cpuinit r4k_blast_icache_page_indexed_setup(void)
247 unsigned long ic_lsize = cpu_icache_line_size();
250 r4k_blast_icache_page_indexed = (void *)cache_noop;
251 else if (ic_lsize == 16)
252 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
253 else if (ic_lsize == 32) {
254 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
255 r4k_blast_icache_page_indexed =
256 blast_icache32_r4600_v1_page_indexed;
257 else if (TX49XX_ICACHE_INDEX_INV_WAR)
258 r4k_blast_icache_page_indexed =
259 tx49_blast_icache32_page_indexed;
261 r4k_blast_icache_page_indexed =
262 blast_icache32_page_indexed;
263 } else if (ic_lsize == 64)
264 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
267 static void (* r4k_blast_icache)(void);
269 static void __cpuinit r4k_blast_icache_setup(void)
271 unsigned long ic_lsize = cpu_icache_line_size();
274 r4k_blast_icache = (void *)cache_noop;
275 else if (ic_lsize == 16)
276 r4k_blast_icache = blast_icache16;
277 else if (ic_lsize == 32) {
278 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
279 r4k_blast_icache = blast_r4600_v1_icache32;
280 else if (TX49XX_ICACHE_INDEX_INV_WAR)
281 r4k_blast_icache = tx49_blast_icache32;
283 r4k_blast_icache = blast_icache32;
284 } else if (ic_lsize == 64)
285 r4k_blast_icache = blast_icache64;
288 static void (* r4k_blast_scache_page)(unsigned long addr);
290 static void __cpuinit r4k_blast_scache_page_setup(void)
292 unsigned long sc_lsize = cpu_scache_line_size();
294 if (scache_size == 0)
295 r4k_blast_scache_page = (void *)cache_noop;
296 else if (sc_lsize == 16)
297 r4k_blast_scache_page = blast_scache16_page;
298 else if (sc_lsize == 32)
299 r4k_blast_scache_page = blast_scache32_page;
300 else if (sc_lsize == 64)
301 r4k_blast_scache_page = blast_scache64_page;
302 else if (sc_lsize == 128)
303 r4k_blast_scache_page = blast_scache128_page;
306 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
308 static void __cpuinit r4k_blast_scache_page_indexed_setup(void)
310 unsigned long sc_lsize = cpu_scache_line_size();
312 if (scache_size == 0)
313 r4k_blast_scache_page_indexed = (void *)cache_noop;
314 else if (sc_lsize == 16)
315 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
316 else if (sc_lsize == 32)
317 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
318 else if (sc_lsize == 64)
319 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
320 else if (sc_lsize == 128)
321 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
324 static void (* r4k_blast_scache)(void);
326 static void __cpuinit r4k_blast_scache_setup(void)
328 unsigned long sc_lsize = cpu_scache_line_size();
330 if (scache_size == 0)
331 r4k_blast_scache = (void *)cache_noop;
332 else if (sc_lsize == 16)
333 r4k_blast_scache = blast_scache16;
334 else if (sc_lsize == 32)
335 r4k_blast_scache = blast_scache32;
336 else if (sc_lsize == 64)
337 r4k_blast_scache = blast_scache64;
338 else if (sc_lsize == 128)
339 r4k_blast_scache = blast_scache128;
342 static inline void local_r4k___flush_cache_all(void * args)
344 #if defined(CONFIG_CPU_LOONGSON2)
351 switch (current_cpu_type()) {
363 static void r4k___flush_cache_all(void)
365 r4k_on_each_cpu(local_r4k___flush_cache_all, NULL);
368 static inline int has_valid_asid(const struct mm_struct *mm)
370 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
373 for_each_online_cpu(i)
374 if (cpu_context(i, mm))
379 return cpu_context(smp_processor_id(), mm);
383 static void r4k__flush_cache_vmap(void)
388 static void r4k__flush_cache_vunmap(void)
393 static inline void local_r4k_flush_cache_range(void * args)
395 struct vm_area_struct *vma = args;
396 int exec = vma->vm_flags & VM_EXEC;
398 if (!(has_valid_asid(vma->vm_mm)))
406 static void r4k_flush_cache_range(struct vm_area_struct *vma,
407 unsigned long start, unsigned long end)
409 int exec = vma->vm_flags & VM_EXEC;
411 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
412 r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
415 static inline void local_r4k_flush_cache_mm(void * args)
417 struct mm_struct *mm = args;
419 if (!has_valid_asid(mm))
423 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
424 * only flush the primary caches but R10000 and R12000 behave sane ...
425 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
426 * caches, so we can bail out early.
428 if (current_cpu_type() == CPU_R4000SC ||
429 current_cpu_type() == CPU_R4000MC ||
430 current_cpu_type() == CPU_R4400SC ||
431 current_cpu_type() == CPU_R4400MC) {
439 static void r4k_flush_cache_mm(struct mm_struct *mm)
441 if (!cpu_has_dc_aliases)
444 r4k_on_each_cpu(local_r4k_flush_cache_mm, mm);
447 struct flush_cache_page_args {
448 struct vm_area_struct *vma;
453 static inline void local_r4k_flush_cache_page(void *args)
455 struct flush_cache_page_args *fcp_args = args;
456 struct vm_area_struct *vma = fcp_args->vma;
457 unsigned long addr = fcp_args->addr;
458 struct page *page = pfn_to_page(fcp_args->pfn);
459 int exec = vma->vm_flags & VM_EXEC;
460 struct mm_struct *mm = vma->vm_mm;
461 int map_coherent = 0;
469 * If ownes no valid ASID yet, cannot possibly have gotten
470 * this page into the cache.
472 if (!has_valid_asid(mm))
476 pgdp = pgd_offset(mm, addr);
477 pudp = pud_offset(pgdp, addr);
478 pmdp = pmd_offset(pudp, addr);
479 ptep = pte_offset(pmdp, addr);
482 * If the page isn't marked valid, the page cannot possibly be
485 if (!(pte_present(*ptep)))
488 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
492 * Use kmap_coherent or kmap_atomic to do flushes for
493 * another ASID than the current one.
495 map_coherent = (cpu_has_dc_aliases &&
496 page_mapped(page) && !Page_dcache_dirty(page));
498 vaddr = kmap_coherent(page, addr);
500 vaddr = kmap_atomic(page);
501 addr = (unsigned long)vaddr;
504 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
505 r4k_blast_dcache_page(addr);
506 if (exec && !cpu_icache_snoops_remote_store)
507 r4k_blast_scache_page(addr);
510 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
511 int cpu = smp_processor_id();
513 if (cpu_context(cpu, mm) != 0)
514 drop_mmu_context(mm, cpu);
516 r4k_blast_icache_page(addr);
523 kunmap_atomic(vaddr);
527 static void r4k_flush_cache_page(struct vm_area_struct *vma,
528 unsigned long addr, unsigned long pfn)
530 struct flush_cache_page_args args;
536 r4k_on_each_cpu(local_r4k_flush_cache_page, &args);
539 static inline void local_r4k_flush_data_cache_page(void * addr)
541 r4k_blast_dcache_page((unsigned long) addr);
544 static void r4k_flush_data_cache_page(unsigned long addr)
547 local_r4k_flush_data_cache_page((void *)addr);
549 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr);
552 struct flush_icache_range_args {
557 static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end)
559 if (!cpu_has_ic_fills_f_dc) {
560 if (end - start >= dcache_size) {
563 R4600_HIT_CACHEOP_WAR_IMPL;
564 protected_blast_dcache_range(start, end);
568 if (end - start > icache_size)
571 protected_blast_icache_range(start, end);
574 static inline void local_r4k_flush_icache_range_ipi(void *args)
576 struct flush_icache_range_args *fir_args = args;
577 unsigned long start = fir_args->start;
578 unsigned long end = fir_args->end;
580 local_r4k_flush_icache_range(start, end);
583 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
585 struct flush_icache_range_args args;
590 r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args);
591 instruction_hazard();
594 #ifdef CONFIG_DMA_NONCOHERENT
596 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
598 /* Catch bad driver code */
601 if (cpu_has_inclusive_pcaches) {
602 if (size >= scache_size)
605 blast_scache_range(addr, addr + size);
611 * Either no secondary cache or the available caches don't have the
612 * subset property so we have to flush the primary caches
615 if (cpu_has_safe_index_cacheops && size >= dcache_size) {
618 R4600_HIT_CACHEOP_WAR_IMPL;
619 blast_dcache_range(addr, addr + size);
622 bc_wback_inv(addr, size);
626 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
628 /* Catch bad driver code */
631 if (cpu_has_inclusive_pcaches) {
632 if (size >= scache_size)
636 * There is no clearly documented alignment requirement
637 * for the cache instruction on MIPS processors and
638 * some processors, among them the RM5200 and RM7000
639 * QED processors will throw an address error for cache
640 * hit ops with insufficient alignment. Solved by
641 * aligning the address to cache line size.
643 blast_inv_scache_range(addr, addr + size);
649 if (cpu_has_safe_index_cacheops && size >= dcache_size) {
652 R4600_HIT_CACHEOP_WAR_IMPL;
653 blast_inv_dcache_range(addr, addr + size);
659 #endif /* CONFIG_DMA_NONCOHERENT */
662 * While we're protected against bad userland addresses we don't care
663 * very much about what happens in that case. Usually a segmentation
664 * fault will dump the process later on anyway ...
666 static void local_r4k_flush_cache_sigtramp(void * arg)
668 unsigned long ic_lsize = cpu_icache_line_size();
669 unsigned long dc_lsize = cpu_dcache_line_size();
670 unsigned long sc_lsize = cpu_scache_line_size();
671 unsigned long addr = (unsigned long) arg;
673 R4600_HIT_CACHEOP_WAR_IMPL;
675 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
676 if (!cpu_icache_snoops_remote_store && scache_size)
677 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
679 protected_flush_icache_line(addr & ~(ic_lsize - 1));
680 if (MIPS4K_ICACHE_REFILL_WAR) {
681 __asm__ __volatile__ (
696 : "i" (Hit_Invalidate_I));
698 if (MIPS_CACHE_SYNC_WAR)
699 __asm__ __volatile__ ("sync");
702 static void r4k_flush_cache_sigtramp(unsigned long addr)
704 r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr);
707 static void r4k_flush_icache_all(void)
709 if (cpu_has_vtag_icache)
713 struct flush_kernel_vmap_range_args {
718 static inline void local_r4k_flush_kernel_vmap_range(void *args)
720 struct flush_kernel_vmap_range_args *vmra = args;
721 unsigned long vaddr = vmra->vaddr;
722 int size = vmra->size;
725 * Aliases only affect the primary caches so don't bother with
726 * S-caches or T-caches.
728 if (cpu_has_safe_index_cacheops && size >= dcache_size)
731 R4600_HIT_CACHEOP_WAR_IMPL;
732 blast_dcache_range(vaddr, vaddr + size);
736 static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
738 struct flush_kernel_vmap_range_args args;
740 args.vaddr = (unsigned long) vaddr;
743 r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args);
746 static inline void rm7k_erratum31(void)
748 const unsigned long ic_lsize = 32;
751 /* RM7000 erratum #31. The icache is screwed at startup. */
755 for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
756 __asm__ __volatile__ (
760 "cache\t%1, 0(%0)\n\t"
761 "cache\t%1, 0x1000(%0)\n\t"
762 "cache\t%1, 0x2000(%0)\n\t"
763 "cache\t%1, 0x3000(%0)\n\t"
764 "cache\t%2, 0(%0)\n\t"
765 "cache\t%2, 0x1000(%0)\n\t"
766 "cache\t%2, 0x2000(%0)\n\t"
767 "cache\t%2, 0x3000(%0)\n\t"
768 "cache\t%1, 0(%0)\n\t"
769 "cache\t%1, 0x1000(%0)\n\t"
770 "cache\t%1, 0x2000(%0)\n\t"
771 "cache\t%1, 0x3000(%0)\n\t"
774 : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
778 static inline void alias_74k_erratum(struct cpuinfo_mips *c)
781 * Early versions of the 74K do not update the cache tags on a
782 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
783 * aliases. In this case it is better to treat the cache as always
786 if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
787 c->dcache.flags |= MIPS_CACHE_VTAG;
788 if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
789 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
790 if (((c->processor_id & 0xff00) == PRID_IMP_1074K) &&
791 ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) {
792 c->dcache.flags |= MIPS_CACHE_VTAG;
793 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
797 static char *way_string[] __cpuinitdata = { NULL, "direct mapped", "2-way",
798 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
801 static void __cpuinit probe_pcache(void)
803 struct cpuinfo_mips *c = ¤t_cpu_data;
804 unsigned int config = read_c0_config();
805 unsigned int prid = read_c0_prid();
806 unsigned long config1;
809 switch (c->cputype) {
810 case CPU_R4600: /* QED style two way caches? */
814 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
815 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
817 c->icache.waybit = __ffs(icache_size/2);
819 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
820 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
822 c->dcache.waybit= __ffs(dcache_size/2);
824 c->options |= MIPS_CPU_CACHE_CDEX_P;
829 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
830 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
834 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
835 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
837 c->dcache.waybit = 0;
839 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
843 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
844 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
848 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
849 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
851 c->dcache.waybit = 0;
853 c->options |= MIPS_CPU_CACHE_CDEX_P;
854 c->options |= MIPS_CPU_PREFETCH;
864 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
865 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
867 c->icache.waybit = 0; /* doesn't matter */
869 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
870 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
872 c->dcache.waybit = 0; /* does not matter */
874 c->options |= MIPS_CPU_CACHE_CDEX_P;
880 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
881 c->icache.linesz = 64;
883 c->icache.waybit = 0;
885 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
886 c->dcache.linesz = 32;
888 c->dcache.waybit = 0;
890 c->options |= MIPS_CPU_PREFETCH;
894 write_c0_config(config & ~VR41_CONF_P4K);
896 /* Workaround for cache instruction bug of VR4131 */
897 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
898 c->processor_id == 0x0c82U) {
899 config |= 0x00400000U;
900 if (c->processor_id == 0x0c80U)
901 config |= VR41_CONF_BP;
902 write_c0_config(config);
904 c->options |= MIPS_CPU_CACHE_CDEX_P;
906 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
907 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
909 c->icache.waybit = __ffs(icache_size/2);
911 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
912 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
914 c->dcache.waybit = __ffs(dcache_size/2);
923 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
924 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
926 c->icache.waybit = 0; /* doesn't matter */
928 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
929 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
931 c->dcache.waybit = 0; /* does not matter */
933 c->options |= MIPS_CPU_CACHE_CDEX_P;
939 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
940 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
942 c->icache.waybit = __ffs(icache_size / c->icache.ways);
944 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
945 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
947 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
949 c->options |= MIPS_CPU_CACHE_CDEX_P;
950 c->options |= MIPS_CPU_PREFETCH;
954 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
955 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
960 c->icache.waybit = 0;
962 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
963 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
968 c->dcache.waybit = 0;
972 if (!(config & MIPS_CONF_M))
973 panic("Don't know how to probe P-caches on this cpu.");
976 * So we seem to be a MIPS32 or MIPS64 CPU
977 * So let's probe the I-cache ...
979 config1 = read_c0_config1();
981 if ((lsize = ((config1 >> 19) & 7)))
982 c->icache.linesz = 2 << lsize;
984 c->icache.linesz = lsize;
985 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
986 c->icache.ways = 1 + ((config1 >> 16) & 7);
988 icache_size = c->icache.sets *
991 c->icache.waybit = __ffs(icache_size/c->icache.ways);
993 if (config & 0x8) /* VI bit */
994 c->icache.flags |= MIPS_CACHE_VTAG;
997 * Now probe the MIPS32 / MIPS64 data cache.
1001 if ((lsize = ((config1 >> 10) & 7)))
1002 c->dcache.linesz = 2 << lsize;
1004 c->dcache.linesz= lsize;
1005 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
1006 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1008 dcache_size = c->dcache.sets *
1011 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
1013 c->options |= MIPS_CPU_PREFETCH;
1018 * Processor configuration sanity check for the R4000SC erratum
1019 * #5. With page sizes larger than 32kB there is no possibility
1020 * to get a VCE exception anymore so we don't care about this
1021 * misconfiguration. The case is rather theoretical anyway;
1022 * presumably no vendor is shipping his hardware in the "bad"
1025 if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
1026 !(config & CONF_SC) && c->icache.linesz != 16 &&
1027 PAGE_SIZE <= 0x8000)
1028 panic("Improper R4000SC processor configuration detected");
1030 /* compute a couple of other cache variables */
1031 c->icache.waysize = icache_size / c->icache.ways;
1032 c->dcache.waysize = dcache_size / c->dcache.ways;
1034 c->icache.sets = c->icache.linesz ?
1035 icache_size / (c->icache.linesz * c->icache.ways) : 0;
1036 c->dcache.sets = c->dcache.linesz ?
1037 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1040 * R10000 and R12000 P-caches are odd in a positive way. They're 32kB
1041 * 2-way virtually indexed so normally would suffer from aliases. So
1042 * normally they'd suffer from aliases but magic in the hardware deals
1043 * with that for us so we don't need to take care ourselves.
1045 switch (c->cputype) {
1051 c->dcache.flags |= MIPS_CACHE_PINDEX;
1065 if (c->cputype == CPU_74K)
1066 alias_74k_erratum(c);
1067 if ((read_c0_config7() & (1 << 16))) {
1068 /* effectively physically indexed dcache,
1069 thus no virtual aliases. */
1070 c->dcache.flags |= MIPS_CACHE_PINDEX;
1074 if (c->dcache.waysize > PAGE_SIZE)
1075 c->dcache.flags |= MIPS_CACHE_ALIASES;
1078 switch (c->cputype) {
1081 * Some older 20Kc chips doesn't have the 'VI' bit in
1082 * the config register.
1084 c->icache.flags |= MIPS_CACHE_VTAG;
1088 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1092 #ifdef CONFIG_CPU_LOONGSON2
1094 * LOONGSON2 has 4 way icache, but when using indexed cache op,
1095 * one op will act on all 4 ways
1100 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1102 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1103 way_string[c->icache.ways], c->icache.linesz);
1105 printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1106 dcache_size >> 10, way_string[c->dcache.ways],
1107 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1108 (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1109 "cache aliases" : "no aliases",
1114 * If you even _breathe_ on this function, look at the gcc output and make sure
1115 * it does not pop things on and off the stack for the cache sizing loop that
1116 * executes in KSEG1 space or else you will crash and burn badly. You have
1119 static int __cpuinit probe_scache(void)
1121 unsigned long flags, addr, begin, end, pow2;
1122 unsigned int config = read_c0_config();
1123 struct cpuinfo_mips *c = ¤t_cpu_data;
1125 if (config & CONF_SC)
1128 begin = (unsigned long) &_stext;
1129 begin &= ~((4 * 1024 * 1024) - 1);
1130 end = begin + (4 * 1024 * 1024);
1133 * This is such a bitch, you'd think they would make it easy to do
1134 * this. Away you daemons of stupidity!
1136 local_irq_save(flags);
1138 /* Fill each size-multiple cache line with a valid tag. */
1140 for (addr = begin; addr < end; addr = (begin + pow2)) {
1141 unsigned long *p = (unsigned long *) addr;
1142 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1146 /* Load first line with zero (therefore invalid) tag. */
1149 __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1150 cache_op(Index_Store_Tag_I, begin);
1151 cache_op(Index_Store_Tag_D, begin);
1152 cache_op(Index_Store_Tag_SD, begin);
1154 /* Now search for the wrap around point. */
1155 pow2 = (128 * 1024);
1156 for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1157 cache_op(Index_Load_Tag_SD, addr);
1158 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1159 if (!read_c0_taglo())
1163 local_irq_restore(flags);
1167 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1169 c->dcache.waybit = 0; /* does not matter */
1174 #if defined(CONFIG_CPU_LOONGSON2)
1175 static void __init loongson2_sc_init(void)
1177 struct cpuinfo_mips *c = ¤t_cpu_data;
1179 scache_size = 512*1024;
1180 c->scache.linesz = 32;
1182 c->scache.waybit = 0;
1183 c->scache.waysize = scache_size / (c->scache.ways);
1184 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1185 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1186 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1188 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1192 extern int r5k_sc_init(void);
1193 extern int rm7k_sc_init(void);
1194 extern int mips_sc_init(void);
1196 static void __cpuinit setup_scache(void)
1198 struct cpuinfo_mips *c = ¤t_cpu_data;
1199 unsigned int config = read_c0_config();
1203 * Do the probing thing on R4000SC and R4400SC processors. Other
1204 * processors don't have a S-cache that would be relevant to the
1205 * Linux memory management.
1207 switch (c->cputype) {
1212 sc_present = run_uncached(probe_scache);
1214 c->options |= MIPS_CPU_CACHE_CDEX_S;
1220 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1221 c->scache.linesz = 64 << ((config >> 13) & 1);
1223 c->scache.waybit= 0;
1229 #ifdef CONFIG_R5000_CPU_SCACHE
1235 #ifdef CONFIG_RM7000_CPU_SCACHE
1240 #if defined(CONFIG_CPU_LOONGSON2)
1242 loongson2_sc_init();
1246 /* don't need to worry about L2, fully coherent */
1250 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1251 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1252 #ifdef CONFIG_MIPS_CPU_SCACHE
1253 if (mips_sc_init ()) {
1254 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1255 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1257 way_string[c->scache.ways], c->scache.linesz);
1260 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1261 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1271 /* compute a couple of other cache variables */
1272 c->scache.waysize = scache_size / c->scache.ways;
1274 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1276 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1277 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1279 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1282 void au1x00_fixup_config_od(void)
1285 * c0_config.od (bit 19) was write only (and read as 0)
1286 * on the early revisions of Alchemy SOCs. It disables the bus
1287 * transaction overlapping and needs to be set to fix various errata.
1289 switch (read_c0_prid()) {
1290 case 0x00030100: /* Au1000 DA */
1291 case 0x00030201: /* Au1000 HA */
1292 case 0x00030202: /* Au1000 HB */
1293 case 0x01030200: /* Au1500 AB */
1295 * Au1100 errata actually keeps silence about this bit, so we set it
1296 * just in case for those revisions that require it to be set according
1297 * to the (now gone) cpu table.
1299 case 0x02030200: /* Au1100 AB */
1300 case 0x02030201: /* Au1100 BA */
1301 case 0x02030202: /* Au1100 BC */
1302 set_c0_config(1 << 19);
1307 /* CP0 hazard avoidance. */
1308 #define NXP_BARRIER() \
1309 __asm__ __volatile__( \
1310 ".set noreorder\n\t" \
1311 "nop; nop; nop; nop; nop; nop;\n\t" \
1314 static void nxp_pr4450_fixup_config(void)
1316 unsigned long config0;
1318 config0 = read_c0_config();
1320 /* clear all three cache coherency fields */
1321 config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1322 config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) |
1323 ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1324 ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1325 write_c0_config(config0);
1329 static int __cpuinitdata cca = -1;
1331 static int __init cca_setup(char *str)
1333 get_option(&str, &cca);
1338 early_param("cca", cca_setup);
1340 static void __cpuinit coherency_setup(void)
1342 if (cca < 0 || cca > 7)
1343 cca = read_c0_config() & CONF_CM_CMASK;
1344 _page_cachable_default = cca << _CACHE_SHIFT;
1346 pr_debug("Using cache attribute %d\n", cca);
1347 change_c0_config(CONF_CM_CMASK, cca);
1350 * c0_status.cu=0 specifies that updates by the sc instruction use
1351 * the coherency mode specified by the TLB; 1 means cachable
1352 * coherent update on write will be used. Not all processors have
1353 * this bit and; some wire it to zero, others like Toshiba had the
1354 * silly idea of putting something else there ...
1356 switch (current_cpu_type()) {
1363 clear_c0_config(CONF_CU);
1366 * We need to catch the early Alchemy SOCs with
1367 * the write-only co_config.od bit and set it back to one on:
1368 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
1371 au1x00_fixup_config_od();
1374 case PRID_IMP_PR4450:
1375 nxp_pr4450_fixup_config();
1380 #if defined(CONFIG_DMA_NONCOHERENT)
1382 static int __cpuinitdata coherentio;
1384 static int __init setcoherentio(char *str)
1391 early_param("coherentio", setcoherentio);
1394 static void __cpuinit r4k_cache_error_setup(void)
1396 extern char __weak except_vec2_generic;
1397 extern char __weak except_vec2_sb1;
1398 struct cpuinfo_mips *c = ¤t_cpu_data;
1400 switch (c->cputype) {
1403 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1407 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1412 void __cpuinit r4k_cache_init(void)
1414 extern void build_clear_page(void);
1415 extern void build_copy_page(void);
1416 struct cpuinfo_mips *c = ¤t_cpu_data;
1421 r4k_blast_dcache_page_setup();
1422 r4k_blast_dcache_page_indexed_setup();
1423 r4k_blast_dcache_setup();
1424 r4k_blast_icache_page_setup();
1425 r4k_blast_icache_page_indexed_setup();
1426 r4k_blast_icache_setup();
1427 r4k_blast_scache_page_setup();
1428 r4k_blast_scache_page_indexed_setup();
1429 r4k_blast_scache_setup();
1432 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1433 * This code supports virtually indexed processors and will be
1434 * unnecessarily inefficient on physically indexed processors.
1436 if (c->dcache.linesz)
1437 shm_align_mask = max_t( unsigned long,
1438 c->dcache.sets * c->dcache.linesz - 1,
1441 shm_align_mask = PAGE_SIZE-1;
1443 __flush_cache_vmap = r4k__flush_cache_vmap;
1444 __flush_cache_vunmap = r4k__flush_cache_vunmap;
1446 flush_cache_all = cache_noop;
1447 __flush_cache_all = r4k___flush_cache_all;
1448 flush_cache_mm = r4k_flush_cache_mm;
1449 flush_cache_page = r4k_flush_cache_page;
1450 flush_cache_range = r4k_flush_cache_range;
1452 __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1454 flush_cache_sigtramp = r4k_flush_cache_sigtramp;
1455 flush_icache_all = r4k_flush_icache_all;
1456 local_flush_data_cache_page = local_r4k_flush_data_cache_page;
1457 flush_data_cache_page = r4k_flush_data_cache_page;
1458 flush_icache_range = r4k_flush_icache_range;
1459 local_flush_icache_range = local_r4k_flush_icache_range;
1461 #if defined(CONFIG_DMA_NONCOHERENT)
1463 _dma_cache_wback_inv = (void *)cache_noop;
1464 _dma_cache_wback = (void *)cache_noop;
1465 _dma_cache_inv = (void *)cache_noop;
1467 _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
1468 _dma_cache_wback = r4k_dma_cache_wback_inv;
1469 _dma_cache_inv = r4k_dma_cache_inv;
1475 #if !defined(CONFIG_MIPS_CMP)
1476 local_r4k___flush_cache_all(NULL);
1479 board_cache_error_setup = r4k_cache_error_setup;