arch/mips/mm/uasm.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * A small micro-assembler. It is intentionally kept simple, does only
   7  * support a subset of instructions, and does not try to hide pipeline
   8  * effects like branch delay slots.
   9  *
  10  * Copyright (C) 2004, 2005, 2006, 2008  Thiemo Seufer
  11  * Copyright (C) 2005, 2007  Maciej W. Rozycki
  12  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
  13  * Copyright (C) 2012, 2013  MIPS Technologies, Inc.  All rights reserved.
  14  */
  15
  16 enum fields {
  17         RS = 0x001,
  18         RT = 0x002,
  19         RD = 0x004,
  20         RE = 0x008,
  21         SIMM = 0x010,
  22         UIMM = 0x020,
  23         BIMM = 0x040,
  24         JIMM = 0x080,
  25         FUNC = 0x100,
  26         SET = 0x200,
  27         SCIMM = 0x400,
  28         SIMM9 = 0x800,
  29 };
  30
  31 #define OP_MASK         0x3f
  32 #define OP_SH           26
  33 #define RD_MASK         0x1f
  34 #define RD_SH           11
  35 #define RE_MASK         0x1f
  36 #define RE_SH           6
  37 #define IMM_MASK        0xffff
  38 #define IMM_SH          0
  39 #define JIMM_MASK       0x3ffffff
  40 #define JIMM_SH         0
  41 #define FUNC_MASK       0x3f
  42 #define FUNC_SH         0
  43 #define SET_MASK        0x7
  44 #define SET_SH          0
  45 #define SIMM9_SH        7
  46 #define SIMM9_MASK      0x1ff
  47
  48 enum opcode {
  49         insn_invalid,
  50         insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
  51         insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
  52         insn_bne, insn_cache, insn_cfc1, insn_cfcmsa, insn_ctc1, insn_ctcmsa,
  53         insn_daddiu, insn_daddu, insn_dins, insn_dinsm, insn_divu, insn_dmfc0,
  54         insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll, insn_dsll32, insn_dsra,
  55         insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret, insn_ext, insn_ins,
  56         insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_ld, insn_ldx,
  57         insn_lh, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0,
  58         insn_mfhc0, insn_mfhi, insn_mflo, insn_mtc0, insn_mthc0, insn_mul,
  59         insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd,
  60         insn_sd, insn_sll, insn_sllv, insn_slt, insn_sltiu, insn_sltu, insn_sra,
  61         insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall,
  62         insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh,
  63         insn_xor, insn_xori, insn_yield, insn_lddir, insn_ldpte,
  64 };
  65
  66 struct insn {
  67         enum opcode opcode;
  68         u32 match;
  69         enum fields fields;
  70 };
  71
  72 static inline u32 build_rs(u32 arg)
  73 {
  74         WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");
  75
  76         return (arg & RS_MASK) << RS_SH;
  77 }
  78
  79 static inline u32 build_rt(u32 arg)
  80 {
  81         WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");
  82
  83         return (arg & RT_MASK) << RT_SH;
  84 }
  85
  86 static inline u32 build_rd(u32 arg)
  87 {
  88         WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");
  89
  90         return (arg & RD_MASK) << RD_SH;
  91 }
  92
  93 static inline u32 build_re(u32 arg)
  94 {
  95         WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");
  96
  97         return (arg & RE_MASK) << RE_SH;
  98 }
  99
 100 static inline u32 build_simm(s32 arg)
 101 {
 102         WARN(arg > 0x7fff || arg < -0x8000,
 103              KERN_WARNING "Micro-assembler field overflow\n");
 104
 105         return arg & 0xffff;
 106 }
 107
 108 static inline u32 build_uimm(u32 arg)
 109 {
 110         WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");
 111
 112         return arg & IMM_MASK;
 113 }
 114
 115 static inline u32 build_scimm(u32 arg)
 116 {
 117         WARN(arg & ~SCIMM_MASK,
 118              KERN_WARNING "Micro-assembler field overflow\n");
 119
 120         return (arg & SCIMM_MASK) << SCIMM_SH;
 121 }
 122
 123 static inline u32 build_scimm9(s32 arg)
 124 {
 125         WARN((arg > 0xff || arg < -0x100),
 126                KERN_WARNING "Micro-assembler field overflow\n");
 127
 128         return (arg & SIMM9_MASK) << SIMM9_SH;
 129 }
 130
 131 static inline u32 build_func(u32 arg)
 132 {
 133         WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");
 134
 135         return arg & FUNC_MASK;
 136 }
 137
 138 static inline u32 build_set(u32 arg)
 139 {
 140         WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");
 141
 142         return arg & SET_MASK;
 143 }
 144
 145 static void build_insn(u32 **buf, enum opcode opc, ...);
 146
 147 #define I_u1u2u3(op)                                    \
 148 Ip_u1u2u3(op)                                           \
 149 {                                                       \
 150         build_insn(buf, insn##op, a, b, c);             \
 151 }                                                       \
 152 UASM_EXPORT_SYMBOL(uasm_i##op);
 153
 154 #define I_s3s1s2(op)                                    \
 155 Ip_s3s1s2(op)                                           \
 156 {                                                       \
 157         build_insn(buf, insn##op, b, c, a);             \
 158 }                                                       \
 159 UASM_EXPORT_SYMBOL(uasm_i##op);
 160
 161 #define I_u2u1u3(op)                                    \
 162 Ip_u2u1u3(op)                                           \
 163 {                                                       \
 164         build_insn(buf, insn##op, b, a, c);             \
 165 }                                                       \
 166 UASM_EXPORT_SYMBOL(uasm_i##op);
 167
 168 #define I_u3u2u1(op)                                    \
 169 Ip_u3u2u1(op)                                           \
 170 {                                                       \
 171         build_insn(buf, insn##op, c, b, a);             \
 172 }                                                       \
 173 UASM_EXPORT_SYMBOL(uasm_i##op);
 174
 175 #define I_u3u1u2(op)                                    \
 176 Ip_u3u1u2(op)                                           \
 177 {                                                       \
 178         build_insn(buf, insn##op, b, c, a);             \
 179 }                                                       \
 180 UASM_EXPORT_SYMBOL(uasm_i##op);
 181
 182 #define I_u1u2s3(op)                                    \
 183 Ip_u1u2s3(op)                                           \
 184 {                                                       \
 185         build_insn(buf, insn##op, a, b, c);             \
 186 }                                                       \
 187 UASM_EXPORT_SYMBOL(uasm_i##op);
 188
 189 #define I_u2s3u1(op)                                    \
 190 Ip_u2s3u1(op)                                           \
 191 {                                                       \
 192         build_insn(buf, insn##op, c, a, b);             \
 193 }                                                       \
 194 UASM_EXPORT_SYMBOL(uasm_i##op);
 195
 196 #define I_u2u1s3(op)                                    \
 197 Ip_u2u1s3(op)                                           \
 198 {                                                       \
 199         build_insn(buf, insn##op, b, a, c);             \
 200 }                                                       \
 201 UASM_EXPORT_SYMBOL(uasm_i##op);
 202
 203 #define I_u2u1msbu3(op)                                 \
 204 Ip_u2u1msbu3(op)                                        \
 205 {                                                       \
 206         build_insn(buf, insn##op, b, a, c+d-1, c);      \
 207 }                                                       \
 208 UASM_EXPORT_SYMBOL(uasm_i##op);
 209
 210 #define I_u2u1msb32u3(op)                               \
 211 Ip_u2u1msbu3(op)                                        \
 212 {                                                       \
 213         build_insn(buf, insn##op, b, a, c+d-33, c);     \
 214 }                                                       \
 215 UASM_EXPORT_SYMBOL(uasm_i##op);
 216
 217 #define I_u2u1msbdu3(op)                                \
 218 Ip_u2u1msbu3(op)                                        \
 219 {                                                       \
 220         build_insn(buf, insn##op, b, a, d-1, c);        \
 221 }                                                       \
 222 UASM_EXPORT_SYMBOL(uasm_i##op);
 223
 224 #define I_u1u2(op)                                      \
 225 Ip_u1u2(op)                                             \
 226 {                                                       \
 227         build_insn(buf, insn##op, a, b);                \
 228 }                                                       \
 229 UASM_EXPORT_SYMBOL(uasm_i##op);
 230
 231 #define I_u2u1(op)                                      \
 232 Ip_u1u2(op)                                             \
 233 {                                                       \
 234         build_insn(buf, insn##op, b, a);                \
 235 }                                                       \
 236 UASM_EXPORT_SYMBOL(uasm_i##op);
 237
 238 #define I_u1s2(op)                                      \
 239 Ip_u1s2(op)                                             \
 240 {                                                       \
 241         build_insn(buf, insn##op, a, b);                \
 242 }                                                       \
 243 UASM_EXPORT_SYMBOL(uasm_i##op);
 244
 245 #define I_u1(op)                                        \
 246 Ip_u1(op)                                               \
 247 {                                                       \
 248         build_insn(buf, insn##op, a);                   \
 249 }                                                       \
 250 UASM_EXPORT_SYMBOL(uasm_i##op);
 251
 252 #define I_0(op)                                         \
 253 Ip_0(op)                                                \
 254 {                                                       \
 255         build_insn(buf, insn##op);                      \
 256 }                                                       \
 257 UASM_EXPORT_SYMBOL(uasm_i##op);
 258
 259 I_u2u1s3(_addiu)
 260 I_u3u1u2(_addu)
 261 I_u2u1u3(_andi)
 262 I_u3u1u2(_and)
 263 I_u1u2s3(_beq)
 264 I_u1u2s3(_beql)
 265 I_u1s2(_bgez)
 266 I_u1s2(_bgezl)
 267 I_u1s2(_bltz)
 268 I_u1s2(_bltzl)
 269 I_u1u2s3(_bne)
 270 I_u2s3u1(_cache)
 271 I_u1u2(_cfc1)
 272 I_u2u1(_cfcmsa)
 273 I_u1u2(_ctc1)
 274 I_u2u1(_ctcmsa)
 275 I_u1u2u3(_dmfc0)
 276 I_u1u2u3(_dmtc0)
 277 I_u2u1s3(_daddiu)
 278 I_u3u1u2(_daddu)
 279 I_u1u2(_divu)
 280 I_u2u1u3(_dsll)
 281 I_u2u1u3(_dsll32)
 282 I_u2u1u3(_dsra)
 283 I_u2u1u3(_dsrl)
 284 I_u2u1u3(_dsrl32)
 285 I_u2u1u3(_drotr)
 286 I_u2u1u3(_drotr32)
 287 I_u3u1u2(_dsubu)
 288 I_0(_eret)
 289 I_u2u1msbdu3(_ext)
 290 I_u2u1msbu3(_ins)
 291 I_u1(_j)
 292 I_u1(_jal)
 293 I_u2u1(_jalr)
 294 I_u1(_jr)
 295 I_u2s3u1(_lb)
 296 I_u2s3u1(_ld)
 297 I_u2s3u1(_lh)
 298 I_u2s3u1(_ll)
 299 I_u2s3u1(_lld)
 300 I_u1s2(_lui)
 301 I_u2s3u1(_lw)
 302 I_u1u2u3(_mfc0)
 303 I_u1u2u3(_mfhc0)
 304 I_u1(_mfhi)
 305 I_u1(_mflo)
 306 I_u1u2u3(_mtc0)
 307 I_u1u2u3(_mthc0)
 308 I_u3u1u2(_mul)
 309 I_u2u1u3(_ori)
 310 I_u3u1u2(_or)
 311 I_0(_rfe)
 312 I_u2s3u1(_sc)
 313 I_u2s3u1(_scd)
 314 I_u2s3u1(_sd)
 315 I_u2u1u3(_sll)
 316 I_u3u2u1(_sllv)
 317 I_s3s1s2(_slt)
 318 I_u2u1s3(_sltiu)
 319 I_u3u1u2(_sltu)
 320 I_u2u1u3(_sra)
 321 I_u2u1u3(_srl)
 322 I_u3u2u1(_srlv)
 323 I_u2u1u3(_rotr)
 324 I_u3u1u2(_subu)
 325 I_u2s3u1(_sw)
 326 I_u1(_sync)
 327 I_0(_tlbp)
 328 I_0(_tlbr)
 329 I_0(_tlbwi)
 330 I_0(_tlbwr)
 331 I_u1(_wait);
 332 I_u2u1(_wsbh)
 333 I_u3u1u2(_xor)
 334 I_u2u1u3(_xori)
 335 I_u2u1(_yield)
 336 I_u2u1msbu3(_dins);
 337 I_u2u1msb32u3(_dinsm);
 338 I_u1(_syscall);
 339 I_u1u2s3(_bbit0);
 340 I_u1u2s3(_bbit1);
 341 I_u3u1u2(_lwx)
 342 I_u3u1u2(_ldx)
 343 I_u1u2(_ldpte)
 344 I_u2u1u3(_lddir)
 345
 346 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 347 #include <asm/octeon/octeon.h>
 348 void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b,
 349                             unsigned int c)
 350 {
 351         if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR && a <= 24 && a != 5)
 352                 /*
 353                  * As per erratum Core-14449, replace prefetches 0-4,
 354                  * 6-24 with 'pref 28'.
 355                  */
 356                 build_insn(buf, insn_pref, c, 28, b);
 357         else
 358                 build_insn(buf, insn_pref, c, a, b);
 359 }
 360 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref));
 361 #else
 362 I_u2s3u1(_pref)
 363 #endif
 364
 365 /* Handle labels. */
 366 void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid)
 367 {
 368         (*lab)->addr = addr;
 369         (*lab)->lab = lid;
 370         (*lab)++;
 371 }
 372 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label));
 373
 374 int ISAFUNC(uasm_in_compat_space_p)(long addr)
 375 {
 376         /* Is this address in 32bit compat space? */
 377 #ifdef CONFIG_64BIT
 378         return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
 379 #else
 380         return 1;
 381 #endif
 382 }
 383 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p));
 384
 385 static int uasm_rel_highest(long val)
 386 {
 387 #ifdef CONFIG_64BIT
 388         return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
 389 #else
 390         return 0;
 391 #endif
 392 }
 393
 394 static int uasm_rel_higher(long val)
 395 {
 396 #ifdef CONFIG_64BIT
 397         return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
 398 #else
 399         return 0;
 400 #endif
 401 }
 402
 403 int ISAFUNC(uasm_rel_hi)(long val)
 404 {
 405         return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
 406 }
 407 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi));
 408
 409 int ISAFUNC(uasm_rel_lo)(long val)
 410 {
 411         return ((val & 0xffff) ^ 0x8000) - 0x8000;
 412 }
 413 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo));
 414
 415 void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr)
 416 {
 417         if (!ISAFUNC(uasm_in_compat_space_p)(addr)) {
 418                 ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr));
 419                 if (uasm_rel_higher(addr))
 420                         ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr));
 421                 if (ISAFUNC(uasm_rel_hi(addr))) {
 422                         ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
 423                         ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
 424                                         ISAFUNC(uasm_rel_hi)(addr));
 425                         ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
 426                 } else
 427                         ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0);
 428         } else
 429                 ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr)));
 430 }
 431 UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly));
 432
 433 void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr)
 434 {
 435         ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr);
 436         if (ISAFUNC(uasm_rel_lo(addr))) {
 437                 if (!ISAFUNC(uasm_in_compat_space_p)(addr))
 438                         ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
 439                                         ISAFUNC(uasm_rel_lo(addr)));
 440                 else
 441                         ISAFUNC(uasm_i_addiu)(buf, rs, rs,
 442                                         ISAFUNC(uasm_rel_lo(addr)));
 443         }
 444 }
 445 UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA));
 446
 447 /* Handle relocations. */
 448 void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid)
 449 {
 450         (*rel)->addr = addr;
 451         (*rel)->type = R_MIPS_PC16;
 452         (*rel)->lab = lid;
 453         (*rel)++;
 454 }
 455 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16));
 456
 457 static inline void __resolve_relocs(struct uasm_reloc *rel,
 458                                     struct uasm_label *lab);
 459
 460 void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel,
 461                                   struct uasm_label *lab)
 462 {
 463         struct uasm_label *l;
 464
 465         for (; rel->lab != UASM_LABEL_INVALID; rel++)
 466                 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
 467                         if (rel->lab == l->lab)
 468                                 __resolve_relocs(rel, l);
 469 }
 470 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs));
 471
 472 void ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end,
 473                                long off)
 474 {
 475         for (; rel->lab != UASM_LABEL_INVALID; rel++)
 476                 if (rel->addr >= first && rel->addr < end)
 477                         rel->addr += off;
 478 }
 479 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs));
 480
 481 void ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end,
 482                                long off)
 483 {
 484         for (; lab->lab != UASM_LABEL_INVALID; lab++)
 485                 if (lab->addr >= first && lab->addr < end)
 486                         lab->addr += off;
 487 }
 488 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels));
 489
 490 void ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab,
 491                                 u32 *first, u32 *end, u32 *target)
 492 {
 493         long off = (long)(target - first);
 494
 495         memcpy(target, first, (end - first) * sizeof(u32));
 496
 497         ISAFUNC(uasm_move_relocs(rel, first, end, off));
 498         ISAFUNC(uasm_move_labels(lab, first, end, off));
 499 }
 500 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler));
 501
 502 int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr)
 503 {
 504         for (; rel->lab != UASM_LABEL_INVALID; rel++) {
 505                 if (rel->addr == addr
 506                     && (rel->type == R_MIPS_PC16
 507                         || rel->type == R_MIPS_26))
 508                         return 1;
 509         }
 510
 511         return 0;
 512 }
 513 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay));
 514
 515 /* Convenience functions for labeled branches. */
 516 void ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 517                            int lid)
 518 {
 519         uasm_r_mips_pc16(r, *p, lid);
 520         ISAFUNC(uasm_i_bltz)(p, reg, 0);
 521 }
 522 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz));
 523
 524 void ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid)
 525 {
 526         uasm_r_mips_pc16(r, *p, lid);
 527         ISAFUNC(uasm_i_b)(p, 0);
 528 }
 529 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b));
 530
 531 void ISAFUNC(uasm_il_beq)(u32 **p, struct uasm_reloc **r, unsigned int r1,
 532                           unsigned int r2, int lid)
 533 {
 534         uasm_r_mips_pc16(r, *p, lid);
 535         ISAFUNC(uasm_i_beq)(p, r1, r2, 0);
 536 }
 537 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beq));
 538
 539 void ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 540                            int lid)
 541 {
 542         uasm_r_mips_pc16(r, *p, lid);
 543         ISAFUNC(uasm_i_beqz)(p, reg, 0);
 544 }
 545 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz));
 546
 547 void ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 548                             int lid)
 549 {
 550         uasm_r_mips_pc16(r, *p, lid);
 551         ISAFUNC(uasm_i_beqzl)(p, reg, 0);
 552 }
 553 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl));
 554
 555 void ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1,
 556                           unsigned int reg2, int lid)
 557 {
 558         uasm_r_mips_pc16(r, *p, lid);
 559         ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0);
 560 }
 561 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne));
 562
 563 void ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 564                            int lid)
 565 {
 566         uasm_r_mips_pc16(r, *p, lid);
 567         ISAFUNC(uasm_i_bnez)(p, reg, 0);
 568 }
 569 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez));
 570
 571 void ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 572                             int lid)
 573 {
 574         uasm_r_mips_pc16(r, *p, lid);
 575         ISAFUNC(uasm_i_bgezl)(p, reg, 0);
 576 }
 577 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl));
 578
 579 void ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 580                            int lid)
 581 {
 582         uasm_r_mips_pc16(r, *p, lid);
 583         ISAFUNC(uasm_i_bgez)(p, reg, 0);
 584 }
 585 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez));
 586
 587 void ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 588                             unsigned int bit, int lid)
 589 {
 590         uasm_r_mips_pc16(r, *p, lid);
 591         ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0);
 592 }
 593 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0));
 594
 595 void ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg,
 596                             unsigned int bit, int lid)
 597 {
 598         uasm_r_mips_pc16(r, *p, lid);
 599         ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0);
 600 }
 601 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1));