arch/mips/mti-malta/malta-init.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * PROM library initialisation code.
   7  *
   8  * Copyright (C) 1999,2000,2004,2005,2012  MIPS Technologies, Inc.
   9  * All rights reserved.
  10  * Authors: Carsten Langgaard <carstenl@mips.com>
  11  *         Maciej W. Rozycki <macro@mips.com>
  12  *          Steven J. Hill <sjhill@mips.com>
  13  */
  14 #include <linux/init.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/pci_regs.h>
  18 #include <linux/serial_core.h>
  19
  20 #include <asm/cacheflush.h>
  21 #include <asm/smp-ops.h>
  22 #include <asm/traps.h>
  23 #include <asm/fw/fw.h>
  24 #include <asm/mips-cps.h>
  25 #include <asm/mips-boards/generic.h>
  26 #include <asm/mips-boards/malta.h>
  27
  28 static int mips_revision_corid;
  29 int mips_revision_sconid;
  30
  31 /* Bonito64 system controller register base. */
  32 unsigned long _pcictrl_bonito;
  33 unsigned long _pcictrl_bonito_pcicfg;
  34
  35 /* GT64120 system controller register base */
  36 unsigned long _pcictrl_gt64120;
  37
  38 /* MIPS System controller register base */
  39 unsigned long _pcictrl_msc;
  40
  41 #ifdef CONFIG_SERIAL_8250_CONSOLE
  42 static void __init console_config(void)
  43 {
  44         char console_string[40];
  45         int baud = 0;
  46         char parity = '\0', bits = '\0', flow = '\0';
  47         char *s;
  48
  49         s = fw_getenv("modetty0");
  50         if (s) {
  51                 while (*s >= '0' && *s <= '9')
  52                         baud = baud*10 + *s++ - '0';
  53                 if (*s == ',')
  54                         s++;
  55                 if (*s)
  56                         parity = *s++;
  57                 if (*s == ',')
  58                         s++;
  59                 if (*s)
  60                         bits = *s++;
  61                 if (*s == ',')
  62                         s++;
  63                 if (*s == 'h')
  64                         flow = 'r';
  65         }
  66         if (baud == 0)
  67                 baud = 38400;
  68         if (parity != 'n' && parity != 'o' && parity != 'e')
  69                 parity = 'n';
  70         if (bits != '7' && bits != '8')
  71                 bits = '8';
  72         if (flow == '\0')
  73                 flow = 'r';
  74
  75         if ((strstr(fw_getcmdline(), "earlycon=")) == NULL) {
  76                 sprintf(console_string, "uart8250,io,0x3f8,%d%c%c", baud,
  77                         parity, bits);
  78                 setup_earlycon(console_string);
  79         }
  80
  81         if ((strstr(fw_getcmdline(), "console=")) == NULL) {
  82                 sprintf(console_string, " console=ttyS0,%d%c%c%c", baud,
  83                         parity, bits, flow);
  84                 strcat(fw_getcmdline(), console_string);
  85                 pr_info("Config serial console:%s\n", console_string);
  86         }
  87 }
  88 #endif
  89
  90 static void __init mips_nmi_setup(void)
  91 {
  92         void *base;
  93         extern char except_vec_nmi;
  94
  95         base = cpu_has_veic ?
  96                 (void *)(CAC_BASE + 0xa80) :
  97                 (void *)(CAC_BASE + 0x380);
  98         memcpy(base, &except_vec_nmi, 0x80);
  99         flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
 100 }
 101
 102 static void __init mips_ejtag_setup(void)
 103 {
 104         void *base;
 105         extern char except_vec_ejtag_debug;
 106
 107         base = cpu_has_veic ?
 108                 (void *)(CAC_BASE + 0xa00) :
 109                 (void *)(CAC_BASE + 0x300);
 110         memcpy(base, &except_vec_ejtag_debug, 0x80);
 111         flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
 112 }
 113
 114 phys_addr_t mips_cpc_default_phys_base(void)
 115 {
 116         return CPC_BASE_ADDR;
 117 }
 118
 119 void __init prom_init(void)
 120 {
 121         /*
 122          * early setup of _pcictrl_bonito so that we can determine
 123          * the system controller on a CORE_EMUL board
 124          */
 125         _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE);
 126
 127         mips_revision_corid = MIPS_REVISION_CORID;
 128
 129         if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) {
 130                 if (BONITO_PCIDID == 0x0001df53 ||
 131                     BONITO_PCIDID == 0x0003df53)
 132                         mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON;
 133                 else
 134                         mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC;
 135         }
 136
 137         mips_revision_sconid = MIPS_REVISION_SCONID;
 138         if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) {
 139                 switch (mips_revision_corid) {
 140                 case MIPS_REVISION_CORID_QED_RM5261:
 141                 case MIPS_REVISION_CORID_CORE_LV:
 142                 case MIPS_REVISION_CORID_CORE_FPGA:
 143                 case MIPS_REVISION_CORID_CORE_FPGAR2:
 144                         mips_revision_sconid = MIPS_REVISION_SCON_GT64120;
 145                         break;
 146                 case MIPS_REVISION_CORID_CORE_EMUL_BON:
 147                 case MIPS_REVISION_CORID_BONITO64:
 148                 case MIPS_REVISION_CORID_CORE_20K:
 149                         mips_revision_sconid = MIPS_REVISION_SCON_BONITO;
 150                         break;
 151                 case MIPS_REVISION_CORID_CORE_MSC:
 152                 case MIPS_REVISION_CORID_CORE_FPGA2:
 153                 case MIPS_REVISION_CORID_CORE_24K:
 154                         /*
 155                          * SOCit/ROCit support is essentially identical
 156                          * but make an attempt to distinguish them
 157                          */
 158                         mips_revision_sconid = MIPS_REVISION_SCON_SOCIT;
 159                         break;
 160                 case MIPS_REVISION_CORID_CORE_FPGA3:
 161                 case MIPS_REVISION_CORID_CORE_FPGA4:
 162                 case MIPS_REVISION_CORID_CORE_FPGA5:
 163                 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
 164                 default:
 165                         /* See above */
 166                         mips_revision_sconid = MIPS_REVISION_SCON_ROCIT;
 167                         break;
 168                 }
 169         }
 170
 171         switch (mips_revision_sconid) {
 172                 u32 start, map, mask, data;
 173
 174         case MIPS_REVISION_SCON_GT64120:
 175                 /*
 176                  * Setup the North bridge to do Master byte-lane swapping
 177                  * when running in bigendian.
 178                  */
 179                 _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000);
 180
 181 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 182                 GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT |
 183                          GT_PCI0_CMD_SBYTESWAP_BIT);
 184 #else
 185                 GT_WRITE(GT_PCI0_CMD_OFS, 0);
 186 #endif
 187                 /* Fix up PCI I/O mapping if necessary (for Atlas).  */
 188                 start = GT_READ(GT_PCI0IOLD_OFS);
 189                 map = GT_READ(GT_PCI0IOREMAP_OFS);
 190                 if ((start & map) != 0) {
 191                         map &= ~start;
 192                         GT_WRITE(GT_PCI0IOREMAP_OFS, map);
 193                 }
 194
 195                 set_io_port_base(MALTA_GT_PORT_BASE);
 196                 break;
 197
 198         case MIPS_REVISION_SCON_BONITO:
 199                 _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE);
 200
 201                 /*
 202                  * Disable Bonito IOBC.
 203                  */
 204                 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
 205                         ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
 206                           BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
 207
 208                 /*
 209                  * Setup the North bridge to do Master byte-lane swapping
 210                  * when running in bigendian.
 211                  */
 212 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 213                 BONITO_BONGENCFG = BONITO_BONGENCFG &
 214                         ~(BONITO_BONGENCFG_MSTRBYTESWAP |
 215                           BONITO_BONGENCFG_BYTESWAP);
 216 #else
 217                 BONITO_BONGENCFG = BONITO_BONGENCFG |
 218                         BONITO_BONGENCFG_MSTRBYTESWAP |
 219                         BONITO_BONGENCFG_BYTESWAP;
 220 #endif
 221
 222                 set_io_port_base(MALTA_BONITO_PORT_BASE);
 223                 break;
 224
 225         case MIPS_REVISION_SCON_SOCIT:
 226         case MIPS_REVISION_SCON_ROCIT:
 227                 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);
 228 mips_pci_controller:
 229                 mb();
 230                 MSC_READ(MSC01_PCI_CFG, data);
 231                 MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT);
 232                 wmb();
 233
 234                 /* Fix up lane swapping.  */
 235 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 236                 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);
 237 #else
 238                 MSC_WRITE(MSC01_PCI_SWAP,
 239                           MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF |
 240                           MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |
 241                           MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
 242 #endif
 243
 244                 /*
 245                  * Setup the Malta max (2GB) memory for PCI DMA in host bridge
 246                  * in transparent addressing mode.
 247                  */
 248                 mask = PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_PREFETCH;
 249                 MSC_WRITE(MSC01_PCI_BAR0, mask);
 250                 MSC_WRITE(MSC01_PCI_HEAD4, mask);
 251
 252                 mask &= MSC01_PCI_BAR0_SIZE_MSK;
 253                 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask);
 254                 MSC_WRITE(MSC01_PCI_P2SCMAPL, mask);
 255
 256                 /* Don't handle target retries indefinitely.  */
 257                 if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
 258                     MSC01_PCI_CFG_MAXRTRY_MSK)
 259                         data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK <<
 260                                          MSC01_PCI_CFG_MAXRTRY_SHF)) |
 261                                ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) <<
 262                                 MSC01_PCI_CFG_MAXRTRY_SHF);
 263
 264                 wmb();
 265                 MSC_WRITE(MSC01_PCI_CFG, data);
 266                 mb();
 267
 268                 set_io_port_base(MALTA_MSC_PORT_BASE);
 269                 break;
 270
 271         case MIPS_REVISION_SCON_SOCITSC:
 272         case MIPS_REVISION_SCON_SOCITSCP:
 273                 _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000);
 274                 goto mips_pci_controller;
 275
 276         default:
 277                 /* Unknown system controller */
 278                 while (1);      /* We die here... */
 279         }
 280         board_nmi_handler_setup = mips_nmi_setup;
 281         board_ejtag_handler_setup = mips_ejtag_setup;
 282
 283         fw_init_cmdline();
 284         fw_meminit();
 285 #ifdef CONFIG_SERIAL_8250_CONSOLE
 286         console_config();
 287 #endif
 288         /* Early detection of CMP support */
 289         mips_cpc_probe();
 290
 291         if (!register_cps_smp_ops())
 292                 return;
 293         if (!register_cmp_smp_ops())
 294                 return;
 295         if (!register_vsmp_smp_ops())
 296                 return;
 297         register_up_smp_ops();
 298 }