1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2003 Christoph Hellwig (hch@lst.de)
4 * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
5 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
7 #include <linux/kernel.h>
8 #include <linux/export.h>
10 #include <linux/smp.h>
11 #include <linux/dma-direct.h>
12 #include <linux/platform_device.h>
13 #include <linux/platform_data/xtalk-bridge.h>
14 #include <linux/nvmem-consumer.h>
15 #include <linux/crc16.h>
17 #include <asm/pci/bridge.h>
18 #include <asm/paccess.h>
19 #include <asm/sn/irq_alloc.h>
20 #include <asm/sn/ioc3.h>
23 #define CRC16_VALID 0xb001
26 * Common phys<->dma mapping for platforms using pci xtalk bridge
28 dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
30 struct pci_dev *pdev = to_pci_dev(dev);
31 struct bridge_controller *bc = BRIDGE_CONTROLLER(pdev->bus);
33 return bc->baddr + paddr;
36 phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr)
38 return dma_addr & ~(0xffUL << 56);
42 * Most of the IOC3 PCI config register aren't present
43 * we emulate what is needed for a normal PCI enumeration
45 static int ioc3_cfg_rd(void *addr, int where, int size, u32 *value, u32 sid)
52 if (get_dbe(cf, (u32 *)addr))
53 return PCIBIOS_DEVICE_NOT_FOUND;
59 /* emulate sane interrupt pin value */
66 shift = (where & 3) << 3;
67 mask = 0xffffffffU >> ((4 - size) << 3);
68 *value = (cf >> shift) & mask;
70 return PCIBIOS_SUCCESSFUL;
73 static int ioc3_cfg_wr(void *addr, int where, int size, u32 value)
75 u32 cf, shift, mask, smask;
77 if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
78 return PCIBIOS_SUCCESSFUL;
80 if (get_dbe(cf, (u32 *)addr))
81 return PCIBIOS_DEVICE_NOT_FOUND;
83 shift = ((where & 3) << 3);
84 mask = (0xffffffffU >> ((4 - size) << 3));
85 smask = mask << shift;
87 cf = (cf & ~smask) | ((value & mask) << shift);
88 if (put_dbe(cf, (u32 *)addr))
89 return PCIBIOS_DEVICE_NOT_FOUND;
91 return PCIBIOS_SUCCESSFUL;
94 static void bridge_disable_swapping(struct pci_dev *dev)
96 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
97 int slot = PCI_SLOT(dev->devfn);
99 /* Turn off byte swapping */
100 bridge_clr(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
101 bridge_read(bc, b_widget.w_tflush); /* Flush */
104 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
105 bridge_disable_swapping);
109 * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
110 * not really documented, so right now I can't write code which uses it.
111 * Therefore we use type 0 accesses for now even though they won't work
112 * correctly for PCI-to-PCI bridges.
114 * The function is complicated by the ultimate brokenness of the IOC3 chip
115 * which is used in SGI systems. The IOC3 can only handle 32-bit PCI
116 * accesses and does only decode parts of it's address space.
118 static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
119 int where, int size, u32 *value)
121 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
122 struct bridge_regs *bridge = bc->base;
123 int slot = PCI_SLOT(devfn);
124 int fn = PCI_FUNC(devfn);
129 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
130 if (get_dbe(cf, (u32 *)addr))
131 return PCIBIOS_DEVICE_NOT_FOUND;
134 * IOC3 is broken beyond belief ... Don't even give the
135 * generic PCI code a chance to look at it for real ...
137 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
138 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
139 return ioc3_cfg_rd(addr, where, size, value,
143 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
146 res = get_dbe(*value, (u8 *)addr);
148 res = get_dbe(*value, (u16 *)addr);
150 res = get_dbe(*value, (u32 *)addr);
152 return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
155 static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
156 int where, int size, u32 *value)
158 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
159 struct bridge_regs *bridge = bc->base;
160 int busno = bus->number;
161 int slot = PCI_SLOT(devfn);
162 int fn = PCI_FUNC(devfn);
167 bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
168 addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
169 if (get_dbe(cf, (u32 *)addr))
170 return PCIBIOS_DEVICE_NOT_FOUND;
173 * IOC3 is broken beyond belief ... Don't even give the
174 * generic PCI code a chance to look at it for real ...
176 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
177 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where & ~3)];
178 return ioc3_cfg_rd(addr, where, size, value,
182 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
185 res = get_dbe(*value, (u8 *)addr);
187 res = get_dbe(*value, (u16 *)addr);
189 res = get_dbe(*value, (u32 *)addr);
191 return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
194 static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
195 int where, int size, u32 *value)
197 if (!pci_is_root_bus(bus))
198 return pci_conf1_read_config(bus, devfn, where, size, value);
200 return pci_conf0_read_config(bus, devfn, where, size, value);
203 static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
204 int where, int size, u32 value)
206 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
207 struct bridge_regs *bridge = bc->base;
208 int slot = PCI_SLOT(devfn);
209 int fn = PCI_FUNC(devfn);
214 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
215 if (get_dbe(cf, (u32 *)addr))
216 return PCIBIOS_DEVICE_NOT_FOUND;
219 * IOC3 is broken beyond belief ... Don't even give the
220 * generic PCI code a chance to look at it for real ...
222 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
223 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
224 return ioc3_cfg_wr(addr, where, size, value);
227 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
230 res = put_dbe(value, (u8 *)addr);
232 res = put_dbe(value, (u16 *)addr);
234 res = put_dbe(value, (u32 *)addr);
237 return PCIBIOS_DEVICE_NOT_FOUND;
239 return PCIBIOS_SUCCESSFUL;
242 static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
243 int where, int size, u32 value)
245 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
246 struct bridge_regs *bridge = bc->base;
247 int slot = PCI_SLOT(devfn);
248 int fn = PCI_FUNC(devfn);
249 int busno = bus->number;
254 bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
255 addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
256 if (get_dbe(cf, (u32 *)addr))
257 return PCIBIOS_DEVICE_NOT_FOUND;
260 * IOC3 is broken beyond belief ... Don't even give the
261 * generic PCI code a chance to look at it for real ...
263 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
264 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
265 return ioc3_cfg_wr(addr, where, size, value);
268 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
271 res = put_dbe(value, (u8 *)addr);
273 res = put_dbe(value, (u16 *)addr);
275 res = put_dbe(value, (u32 *)addr);
278 return PCIBIOS_DEVICE_NOT_FOUND;
280 return PCIBIOS_SUCCESSFUL;
283 static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
284 int where, int size, u32 value)
286 if (!pci_is_root_bus(bus))
287 return pci_conf1_write_config(bus, devfn, where, size, value);
289 return pci_conf0_write_config(bus, devfn, where, size, value);
292 static struct pci_ops bridge_pci_ops = {
293 .read = pci_read_config,
294 .write = pci_write_config,
297 struct bridge_irq_chip_data {
298 struct bridge_controller *bc;
302 static int bridge_set_affinity(struct irq_data *d, const struct cpumask *mask,
306 struct bridge_irq_chip_data *data = d->chip_data;
307 int bit = d->parent_data->hwirq;
312 ret = irq_chip_set_affinity_parent(d, mask, force);
314 cpu = cpumask_first_and(mask, cpu_online_mask);
315 nasid = cpu_to_node(cpu);
316 bridge_write(data->bc, b_int_addr[pin].addr,
317 (((data->bc->intr_addr >> 30) & 0x30000) |
318 bit | (nasid << 8)));
319 bridge_read(data->bc, b_wid_tflush);
323 return irq_chip_set_affinity_parent(d, mask, force);
327 struct irq_chip bridge_irq_chip = {
329 .irq_mask = irq_chip_mask_parent,
330 .irq_unmask = irq_chip_unmask_parent,
331 .irq_set_affinity = bridge_set_affinity
334 static int bridge_domain_alloc(struct irq_domain *domain, unsigned int virq,
335 unsigned int nr_irqs, void *arg)
337 struct bridge_irq_chip_data *data;
338 struct irq_alloc_info *info = arg;
341 if (nr_irqs > 1 || !info)
344 data = kzalloc(sizeof(*data), GFP_KERNEL);
348 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
350 data->bc = info->ctrl;
351 data->nasid = info->nasid;
352 irq_domain_set_info(domain, virq, info->pin, &bridge_irq_chip,
353 data, handle_level_irq, NULL, NULL);
361 static void bridge_domain_free(struct irq_domain *domain, unsigned int virq,
362 unsigned int nr_irqs)
364 struct irq_data *irqd = irq_domain_get_irq_data(domain, virq);
369 kfree(irqd->chip_data);
370 irq_domain_free_irqs_top(domain, virq, nr_irqs);
373 static int bridge_domain_activate(struct irq_domain *domain,
374 struct irq_data *irqd, bool reserve)
376 struct bridge_irq_chip_data *data = irqd->chip_data;
377 struct bridge_controller *bc = data->bc;
378 int bit = irqd->parent_data->hwirq;
379 int pin = irqd->hwirq;
382 bridge_write(bc, b_int_addr[pin].addr,
383 (((bc->intr_addr >> 30) & 0x30000) |
384 bit | (data->nasid << 8)));
385 bridge_set(bc, b_int_enable, (1 << pin));
386 bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */
389 * Enable sending of an interrupt clear packt to the hub on a high to
390 * low transition of the interrupt pin.
392 * IRIX sets additional bits in the address which are documented as
393 * reserved in the bridge docs.
395 bridge_set(bc, b_int_mode, (1UL << pin));
398 * We assume the bridge to have a 1:1 mapping between devices
399 * (slots) and intr pins.
401 device = bridge_read(bc, b_int_device);
402 device &= ~(7 << (pin*3));
403 device |= (pin << (pin*3));
404 bridge_write(bc, b_int_device, device);
406 bridge_read(bc, b_wid_tflush);
410 static void bridge_domain_deactivate(struct irq_domain *domain,
411 struct irq_data *irqd)
413 struct bridge_irq_chip_data *data = irqd->chip_data;
415 bridge_clr(data->bc, b_int_enable, (1 << irqd->hwirq));
416 bridge_read(data->bc, b_wid_tflush);
419 static const struct irq_domain_ops bridge_domain_ops = {
420 .alloc = bridge_domain_alloc,
421 .free = bridge_domain_free,
422 .activate = bridge_domain_activate,
423 .deactivate = bridge_domain_deactivate
427 * All observed requests have pin == 1. We could have a global here, that
428 * gets incremented and returned every time - unfortunately, pci_map_irq
429 * may be called on the same device over and over, and need to return the
430 * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
432 * A given PCI device, in general, should be able to intr any of the cpus
433 * on any one of the hubs connected to its xbow.
435 static int bridge_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
437 struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
438 struct irq_alloc_info info;
441 irq = bc->pci_int[slot];
444 info.nasid = bc->nasid;
447 irq = irq_domain_alloc_irqs(bc->domain, 1, bc->nasid, &info);
451 bc->pci_int[slot] = irq;
456 #define IOC3_SID(sid) (PCI_VENDOR_ID_SGI << 16 | (sid))
458 static void bridge_setup_ip27_baseio6g(struct bridge_controller *bc)
460 bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP27_BASEIO6G);
461 bc->ioc3_sid[6] = IOC3_SID(IOC3_SUBSYS_IP27_MIO);
464 static void bridge_setup_ip27_baseio(struct bridge_controller *bc)
466 bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP27_BASEIO);
469 static void bridge_setup_ip29_baseio(struct bridge_controller *bc)
471 bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP29_SYSBOARD);
474 static void bridge_setup_ip30_sysboard(struct bridge_controller *bc)
476 bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP30_SYSBOARD);
479 static void bridge_setup_menet(struct bridge_controller *bc)
481 bc->ioc3_sid[0] = IOC3_SID(IOC3_SUBSYS_MENET);
482 bc->ioc3_sid[1] = IOC3_SID(IOC3_SUBSYS_MENET);
483 bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_MENET);
484 bc->ioc3_sid[3] = IOC3_SID(IOC3_SUBSYS_MENET4);
487 #define BRIDGE_BOARD_SETUP(_partno, _setup) \
488 { .match = _partno, .setup = _setup }
490 static const struct {
492 void (*setup)(struct bridge_controller *bc);
493 } bridge_ioc3_devid[] = {
494 BRIDGE_BOARD_SETUP("030-0734-", bridge_setup_ip27_baseio6g),
495 BRIDGE_BOARD_SETUP("030-0880-", bridge_setup_ip27_baseio6g),
496 BRIDGE_BOARD_SETUP("030-1023-", bridge_setup_ip27_baseio),
497 BRIDGE_BOARD_SETUP("030-1124-", bridge_setup_ip27_baseio),
498 BRIDGE_BOARD_SETUP("030-1025-", bridge_setup_ip29_baseio),
499 BRIDGE_BOARD_SETUP("030-1244-", bridge_setup_ip29_baseio),
500 BRIDGE_BOARD_SETUP("030-1389-", bridge_setup_ip29_baseio),
501 BRIDGE_BOARD_SETUP("030-0887-", bridge_setup_ip30_sysboard),
502 BRIDGE_BOARD_SETUP("030-1467-", bridge_setup_ip30_sysboard),
503 BRIDGE_BOARD_SETUP("030-0873-", bridge_setup_menet),
506 static void bridge_setup_board(struct bridge_controller *bc, char *partnum)
510 for (i = 0; i < ARRAY_SIZE(bridge_ioc3_devid); i++)
511 if (!strncmp(partnum, bridge_ioc3_devid[i].match,
512 strlen(bridge_ioc3_devid[i].match))) {
513 bridge_ioc3_devid[i].setup(bc);
517 static int bridge_nvmem_match(struct device *dev, const void *data)
519 const char *name = dev_name(dev);
520 const char *prefix = data;
522 if (strlen(name) < strlen(prefix))
525 return memcmp(prefix, dev_name(dev), strlen(prefix)) == 0;
528 static int bridge_get_partnum(u64 baddr, char *partnum)
530 struct nvmem_device *nvmem;
536 snprintf(prefix, sizeof(prefix), "bridge-%012llx-0b-", baddr);
538 nvmem = nvmem_device_find(prefix, bridge_nvmem_match);
540 return PTR_ERR(nvmem);
542 ret = nvmem_device_read(nvmem, 0, 64, prom);
543 nvmem_device_put(nvmem);
548 if (crc16(CRC16_INIT, prom, 32) != CRC16_VALID ||
549 crc16(CRC16_INIT, prom + 32, 32) != CRC16_VALID)
552 /* Assemble part number */
554 for (i = 0; i < 19; i++)
555 if (prom[i + 11] != ' ')
556 partnum[j++] = prom[i + 11];
558 for (i = 0; i < 6; i++)
559 if (prom[i + 32] != ' ')
560 partnum[j++] = prom[i + 32];
567 static int bridge_probe(struct platform_device *pdev)
569 struct xtalk_bridge_platform_data *bd = dev_get_platdata(&pdev->dev);
570 struct device *dev = &pdev->dev;
571 struct bridge_controller *bc;
572 struct pci_host_bridge *host;
573 struct irq_domain *domain, *parent;
574 struct fwnode_handle *fn;
579 /* get part number from one wire prom */
580 if (bridge_get_partnum(virt_to_phys((void *)bd->bridge_addr), partnum))
581 return -EPROBE_DEFER; /* not available yet */
583 parent = irq_get_default_host();
586 fn = irq_domain_alloc_named_fwnode("BRIDGE");
589 domain = irq_domain_create_hierarchy(parent, 0, 8, fn,
590 &bridge_domain_ops, NULL);
591 irq_domain_free_fwnode(fn);
595 pci_set_flags(PCI_PROBE_ONLY);
597 host = devm_pci_alloc_host_bridge(dev, sizeof(*bc));
600 goto err_remove_domain;
603 bc = pci_host_bridge_priv(host);
605 bc->busn.name = "Bridge PCI busn";
608 bc->busn.flags = IORESOURCE_BUS;
612 pci_add_resource_offset(&host->windows, &bd->mem, bd->mem_offset);
613 pci_add_resource_offset(&host->windows, &bd->io, bd->io_offset);
614 pci_add_resource(&host->windows, &bc->busn);
616 err = devm_request_pci_bus_resources(dev, &host->windows);
618 goto err_free_resource;
620 bc->nasid = bd->nasid;
622 bc->baddr = (u64)bd->masterwid << 60 | PCI64_ATTR_BAR;
623 bc->base = (struct bridge_regs *)bd->bridge_addr;
624 bc->intr_addr = bd->intr_addr;
627 * Clear all pending interrupts.
629 bridge_write(bc, b_int_rst_stat, BRIDGE_IRR_ALL_CLR);
632 * Until otherwise set up, assume all interrupts are from slot 0
634 bridge_write(bc, b_int_device, 0x0);
637 * disable swapping for big windows
639 bridge_clr(bc, b_wid_control,
640 BRIDGE_CTRL_IO_SWAP | BRIDGE_CTRL_MEM_SWAP);
641 #ifdef CONFIG_PAGE_SIZE_4KB
642 bridge_clr(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
643 #else /* 16kB or larger */
644 bridge_set(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
648 * Hmm... IRIX sets additional bits in the address which
649 * are documented as reserved in the bridge docs.
651 bridge_write(bc, b_wid_int_upper,
652 ((bc->intr_addr >> 32) & 0xffff) | (bd->masterwid << 16));
653 bridge_write(bc, b_wid_int_lower, bc->intr_addr & 0xffffffff);
654 bridge_write(bc, b_dir_map, (bd->masterwid << 20)); /* DMA */
655 bridge_write(bc, b_int_enable, 0);
657 for (slot = 0; slot < 8; slot++) {
658 bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
659 bc->pci_int[slot] = -1;
661 bridge_read(bc, b_wid_tflush); /* wait until Bridge PIO complete */
663 bridge_setup_board(bc, partnum);
665 host->dev.parent = dev;
668 host->ops = &bridge_pci_ops;
669 host->map_irq = bridge_map_irq;
670 host->swizzle_irq = pci_common_swizzle;
672 err = pci_scan_root_bus_bridge(host);
674 goto err_free_resource;
676 pci_bus_claim_resources(host->bus);
677 pci_bus_add_devices(host->bus);
679 platform_set_drvdata(pdev, host->bus);
684 pci_free_resource_list(&host->windows);
686 irq_domain_remove(domain);
690 static int bridge_remove(struct platform_device *pdev)
692 struct pci_bus *bus = platform_get_drvdata(pdev);
693 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
695 irq_domain_remove(bc->domain);
696 pci_lock_rescan_remove();
697 pci_stop_root_bus(bus);
698 pci_remove_root_bus(bus);
699 pci_unlock_rescan_remove();
704 static struct platform_driver bridge_driver = {
705 .probe = bridge_probe,
706 .remove = bridge_remove,
708 .name = "xtalk-bridge",
712 builtin_platform_driver(bridge_driver);