1 // SPDX-License-Identifier: GPL-2.0-only
3 * Setting up the clock on MSP SOCs. No RTC typically.
5 * Carsten Langgaard, carstenl@mips.com
6 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
8 * ########################################################################
10 * ########################################################################
13 #include <linux/init.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/sched.h>
16 #include <linux/spinlock.h>
17 #include <linux/ptrace.h>
19 #include <asm/cevt-r4k.h>
20 #include <asm/mipsregs.h>
27 #define get_current_vpe() \
28 ((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE)
30 static struct irqaction timer_vpe1;
31 static int tim_installed;
33 void __init plat_time_init(void)
36 unsigned long cpu_rate = 0;
39 s = prom_getenv("clkfreqhz");
40 cpu_rate = simple_strtoul(s, &endp, 10);
41 if (endp != NULL && *endp != 0) {
43 "Clock rate in Hz parse error: %s\n", s);
49 s = prom_getenv("clkfreq");
50 cpu_rate = 1000 * simple_strtoul(s, &endp, 10);
51 if (endp != NULL && *endp != 0) {
53 "Clock rate in MHz parse error: %s\n", s);
59 #if defined(CONFIG_PMC_MSP7120_EVAL) \
60 || defined(CONFIG_PMC_MSP7120_GW)
62 #elif defined(CONFIG_PMC_MSP7120_FPGA)
68 "Failed to determine CPU clock rate, "
69 "assuming %ld hz ...\n", cpu_rate);
72 printk(KERN_WARNING "Clock rate set to %ld\n", cpu_rate);
74 /* timer frequency is 1/2 clock rate */
75 mips_hpt_frequency = cpu_rate/2;
78 unsigned int get_c0_compare_int(void)
80 /* MIPS_MT modes may want timer for second VPE */
81 if ((get_current_vpe()) && !tim_installed) {
82 memcpy(&timer_vpe1, &c0_compare_irqaction, sizeof(timer_vpe1));
83 setup_irq(MSP_INT_VPE1_TIMER, &timer_vpe1);
87 return get_current_vpe() ? MSP_INT_VPE1_TIMER : MSP_INT_VPE0_TIMER;