1 # SPDX-License-Identifier: GPL-2.0
3 # For a description of the syntax of this configuration file,
4 # see Documentation/kbuild/kconfig-language.txt.
9 select ARCH_32BIT_OFF_T
10 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
12 select OF_EARLY_FLATTREE
14 select HANDLE_DOMAIN_IRQ
16 select HAVE_ARCH_TRACEHOOK
18 select GENERIC_IRQ_CHIP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
22 select GENERIC_CPU_DEVICES
24 select GENERIC_ATOMIC64
25 select GENERIC_CLOCKEVENTS
26 select GENERIC_CLOCKEVENTS_BROADCAST
27 select GENERIC_STRNCPY_FROM_USER
28 select GENERIC_STRNLEN_USER
29 select GENERIC_SMP_IDLE_THREAD
30 select MODULES_USE_ELF_RELA
31 select HAVE_DEBUG_STACKOVERFLOW
33 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
34 select ARCH_USE_QUEUED_SPINLOCKS
35 select ARCH_USE_QUEUED_RWLOCKS
37 select ARCH_WANT_FRAME_POINTERS
38 select GENERIC_IRQ_MULTI_HANDLER
46 config GENERIC_HWEIGHT
52 config TRACE_IRQFLAGS_SUPPORT
55 # For now, use generic checksum functions
56 #These can be reimplemented in assembly later if so inclined
60 config STACKTRACE_SUPPORT
63 config LOCKDEP_SUPPORT
66 menu "Processor type and features"
69 prompt "Subarchitecture"
75 Generic OpenRISC 1200 architecture
79 config DCACHE_WRITETHROUGH
80 bool "Have write through data caches"
83 Select this if your implementation features write through data caches.
84 Selecting 'N' here will allow the kernel to force flushing of data
85 caches at relevant times. Most OpenRISC implementations support write-
90 config OPENRISC_BUILTIN_DTB
94 menu "Class II Instructions"
96 config OPENRISC_HAVE_INST_FF1
97 bool "Have instruction l.ff1"
100 Select this if your implementation has the Class II instruction l.ff1
102 config OPENRISC_HAVE_INST_FL1
103 bool "Have instruction l.fl1"
106 Select this if your implementation has the Class II instruction l.fl1
108 config OPENRISC_HAVE_INST_MUL
109 bool "Have instruction l.mul for hardware multiply"
112 Select this if your implementation has a hardware multiply instruction
114 config OPENRISC_HAVE_INST_DIV
115 bool "Have instruction l.div for hardware divide"
118 Select this if your implementation has a hardware divide instruction
122 int "Maximum number of CPUs (2-32)"
128 bool "Symmetric Multi-Processing support"
130 This enables support for systems with more than one CPU. If you have
131 a system with only one CPU, say N. If you have a system with more
134 If you don't know what to do here, say N.
136 source "kernel/Kconfig.hz"
138 config OPENRISC_NO_SPR_SR_DSX
139 bool "use SPR_SR_DSX software emulation" if OR1K_1200
142 SPR_SR_DSX bit is status register bit indicating whether
143 the last exception has happened in delay slot.
145 OpenRISC architecture makes it optional to have it implemented
146 in hardware and the OR1200 does not have it.
148 Say N here if you know that your OpenRISC processor has
149 SPR_SR_DSX bit implemented. Say Y if you are unsure.
151 config OPENRISC_HAVE_SHADOW_GPRS
152 bool "Support for shadow gpr files" if !SMP
155 Say Y here if your OpenRISC processor features shadowed
156 register files. They will in such case be used as a
157 scratch reg storage on exception entry.
159 On SMP systems, this feature is mandatory.
160 On a unicore system it's safe to say N here if you are unsure.
163 string "Default kernel command string"
166 On some architectures there is currently no way for the boot loader
167 to pass arguments to the kernel. For these architectures, you should
168 supply some command-line options at build time by entering them
171 menu "Debugging options"
173 config JUMP_UPON_UNHANDLED_EXCEPTION
174 bool "Try to die gracefully"
177 Now this puts kernel into infinite loop after first oops. Till
178 your kernel crashes this doesn't have any influence.
180 Say Y if you are unsure.
182 config OPENRISC_ESR_EXCEPTION_BUG_CHECK
183 bool "Check for possible ESR exception bug"
186 This option enables some checks that might expose some problems
189 Say N if you are unsure.