2 * Linux/PA-RISC Project (http://www.parisc-linux.org/)
4 * kernel entry points (interruptions, system call wrappers)
5 * Copyright (C) 1999,2000 Philipp Rumpf
6 * Copyright (C) 1999 SuSE GmbH Nuernberg
7 * Copyright (C) 2000 Hewlett-Packard (John Marvin)
8 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <asm/asm-offsets.h>
27 /* we have the following possibilities to act on an interruption:
28 * - handle in assembly and use shadowed registers only
29 * - save registers to kernel stack and handle in assembly or C */
33 #include <asm/cache.h> /* for L1_CACHE_SHIFT */
34 #include <asm/assembly.h> /* for LDREG/STREG defines */
35 #include <asm/pgtable.h>
36 #include <asm/signal.h>
37 #include <asm/unistd.h>
39 #include <asm/traps.h>
40 #include <asm/thread_info.h>
42 #include <linux/linkage.h>
50 .import pa_tlb_lock,data
51 .macro load_pa_tlb_lock reg
52 #if __PA_LDCW_ALIGNMENT > 4
53 load32 PA(pa_tlb_lock) + __PA_LDCW_ALIGNMENT-1, \reg
54 depi 0,31,__PA_LDCW_ALIGN_ORDER, \reg
56 load32 PA(pa_tlb_lock), \reg
60 /* space_to_prot macro creates a prot id from a space id */
62 #if (SPACEID_SHIFT) == 0
63 .macro space_to_prot spc prot
64 depd,z \spc,62,31,\prot
67 .macro space_to_prot spc prot
68 extrd,u \spc,(64 - (SPACEID_SHIFT)),32,\prot
72 /* Switch to virtual mapping, trashing only %r1 */
75 rsm PSW_SM_I, %r0 /* barrier for "Relied upon Translation */
80 load32 KERNEL_PSW, %r1
82 rsm PSW_SM_QUIET,%r0 /* second "heavy weight" ctl op */
83 mtctl %r0, %cr17 /* Clear IIASQ tail */
84 mtctl %r0, %cr17 /* Clear IIASQ head */
87 mtctl %r1, %cr18 /* Set IIAOQ tail */
89 mtctl %r1, %cr18 /* Set IIAOQ head */
96 * The "get_stack" macros are responsible for determining the
100 * Already using a kernel stack, so call the
101 * get_stack_use_r30 macro to push a pt_regs structure
102 * on the stack, and store registers there.
104 * Need to set up a kernel stack, so call the
105 * get_stack_use_cr30 macro to set up a pointer
106 * to the pt_regs structure contained within the
107 * task pointer pointed to by cr30. Set the stack
108 * pointer to point to the end of the task structure.
110 * Note that we use shadowed registers for temps until
111 * we can save %r26 and %r29. %r26 is used to preserve
112 * %r8 (a shadowed register) which temporarily contained
113 * either the fault type ("code") or the eirr. We need
114 * to use a non-shadowed register to carry the value over
115 * the rfir in virt_map. We use %r26 since this value winds
116 * up being passed as the argument to either do_cpu_irq_mask
117 * or handle_interruption. %r29 is used to hold a pointer
118 * the register save area, and once again, it needs to
119 * be a non-shadowed register so that it survives the rfir.
121 * N.B. TASK_SZ_ALGN and PT_SZ_ALGN include space for a stack frame.
124 .macro get_stack_use_cr30
126 /* we save the registers in the task struct */
130 ldo THREAD_SZ_ALGN(%r1), %r30
134 LDREG TI_TASK(%r9), %r1 /* thread_info -> task_struct */
136 ldo TASK_REGS(%r9),%r9
137 STREG %r17,PT_GR30(%r9)
138 STREG %r29,PT_GR29(%r9)
139 STREG %r26,PT_GR26(%r9)
140 STREG %r16,PT_SR7(%r9)
144 .macro get_stack_use_r30
146 /* we put a struct pt_regs on the stack and save the registers there */
150 ldo PT_SZ_ALGN(%r30),%r30
151 STREG %r1,PT_GR30(%r9)
152 STREG %r29,PT_GR29(%r9)
153 STREG %r26,PT_GR26(%r9)
154 STREG %r16,PT_SR7(%r9)
159 LDREG PT_GR1(%r29), %r1
160 LDREG PT_GR30(%r29),%r30
161 LDREG PT_GR29(%r29),%r29
164 /* default interruption handler
165 * (calls traps.c:handle_interruption) */
172 /* Interrupt interruption handler
173 * (calls irq.c:do_cpu_irq_mask) */
180 .import os_hpmc, code
184 nop /* must be a NOP, will be patched later */
185 load32 PA(os_hpmc), %r3
188 .word 0 /* checksum (will be patched) */
189 .word 0 /* address of handler */
190 .word 0 /* length of handler */
194 * Performance Note: Instructions will be moved up into
195 * this part of the code later on, once we are sure
196 * that the tlb miss handlers are close to final form.
199 /* Register definitions for tlb miss handler macros */
201 va = r8 /* virtual address for which the trap occurred */
202 spc = r24 /* space for which the trap occurred */
207 * itlb miss interruption handler (parisc 1.1 - 32 bit)
221 * itlb miss interruption handler (parisc 2.0)
238 * naitlb miss interruption handler (parisc 1.1 - 32 bit)
241 .macro naitlb_11 code
252 * naitlb miss interruption handler (parisc 2.0)
255 .macro naitlb_20 code
270 * dtlb miss interruption handler (parisc 1.1 - 32 bit)
284 * dtlb miss interruption handler (parisc 2.0)
301 /* nadtlb miss interruption handler (parisc 1.1 - 32 bit) */
303 .macro nadtlb_11 code
313 /* nadtlb miss interruption handler (parisc 2.0) */
315 .macro nadtlb_20 code
330 * dirty bit trap interruption handler (parisc 1.1 - 32 bit)
344 * dirty bit trap interruption handler (parisc 2.0)
360 /* In LP64, the space contains part of the upper 32 bits of the
361 * fault. We have to extract this and place it in the va,
362 * zeroing the corresponding bits in the space register */
363 .macro space_adjust spc,va,tmp
365 extrd,u \spc,63,SPACEID_SHIFT,\tmp
366 depd %r0,63,SPACEID_SHIFT,\spc
367 depd \tmp,31,SPACEID_SHIFT,\va
371 .import swapper_pg_dir,code
373 /* Get the pgd. For faults on space zero (kernel space), this
374 * is simply swapper_pg_dir. For user space faults, the
375 * pgd is stored in %cr25 */
376 .macro get_pgd spc,reg
377 ldil L%PA(swapper_pg_dir),\reg
378 ldo R%PA(swapper_pg_dir)(\reg),\reg
379 or,COND(=) %r0,\spc,%r0
384 space_check(spc,tmp,fault)
386 spc - The space we saw the fault with.
387 tmp - The place to store the current space.
388 fault - Function to call on failure.
390 Only allow faults on different spaces from the
391 currently active one if we're the kernel
394 .macro space_check spc,tmp,fault
396 or,COND(<>) %r0,\spc,%r0 /* user may execute gateway page
397 * as kernel, so defeat the space
400 or,COND(=) %r0,\tmp,%r0 /* nullify if executing as kernel */
401 cmpb,COND(<>),n \tmp,\spc,\fault
404 /* Look up a PTE in a 2-Level scheme (faulting at each
405 * level if the entry isn't present
407 * NOTE: we use ldw even for LP64, since the short pointers
408 * can address up to 1TB
410 .macro L2_ptep pmd,pte,index,va,fault
411 #if CONFIG_PGTABLE_LEVELS == 3
412 extru \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index
414 # if defined(CONFIG_64BIT)
415 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
417 # if PAGE_SIZE > 4096
418 extru \va,31-ASM_PGDIR_SHIFT,32-ASM_PGDIR_SHIFT,\index
420 extru \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
424 dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */
426 ldw,s \index(\pmd),\pmd
427 bb,>=,n \pmd,_PxD_PRESENT_BIT,\fault
428 dep %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */
430 SHLREG %r9,PxD_VALUE_SHIFT,\pmd
431 extru \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
432 dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */
433 shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd /* pmd is now pte */
436 /* Look up PTE in a 3-Level scheme.
438 * Here we implement a Hybrid L2/L3 scheme: we allocate the
439 * first pmd adjacent to the pgd. This means that we can
440 * subtract a constant offset to get to it. The pmd and pgd
441 * sizes are arranged so that a single pmd covers 4GB (giving
442 * a full LP64 process access to 8TB) so our lookups are
443 * effectively L2 for the first 4GB of the kernel (i.e. for
444 * all ILP32 processes and all the kernel for machines with
445 * under 4GB of memory) */
446 .macro L3_ptep pgd,pte,index,va,fault
447 #if CONFIG_PGTABLE_LEVELS == 3 /* we might have a 2-Level scheme, e.g. with 16kb page size */
448 extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
450 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
451 ldw,s \index(\pgd),\pgd
452 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
453 bb,>=,n \pgd,_PxD_PRESENT_BIT,\fault
454 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
455 shld \pgd,PxD_VALUE_SHIFT,\index
456 extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
458 extrd,u,*<> \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
459 ldo ASM_PGD_PMD_OFFSET(\pgd),\pgd
461 L2_ptep \pgd,\pte,\index,\va,\fault
464 /* Acquire pa_tlb_lock lock and check page is present. */
465 .macro tlb_lock spc,ptp,pte,tmp,tmp1,fault
467 cmpib,COND(=),n 0,\spc,2f
468 load_pa_tlb_lock \tmp
469 1: LDCW 0(\tmp),\tmp1
470 cmpib,COND(=) 0,\tmp1,1b
473 bb,<,n \pte,_PAGE_PRESENT_BIT,3f
477 2: LDREG 0(\ptp),\pte
478 bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault
482 /* Release pa_tlb_lock lock without reloading lock address. */
483 .macro tlb_unlock0 spc,tmp
485 or,COND(=) %r0,\spc,%r0
490 /* Release pa_tlb_lock lock. */
491 .macro tlb_unlock1 spc,tmp
493 load_pa_tlb_lock \tmp
494 tlb_unlock0 \spc,\tmp
498 /* Set the _PAGE_ACCESSED bit of the PTE. Be clever and
499 * don't needlessly dirty the cache line if it was already set */
500 .macro update_accessed ptp,pte,tmp,tmp1
501 ldi _PAGE_ACCESSED,\tmp1
503 and,COND(<>) \tmp1,\pte,%r0
507 /* Set the dirty bit (and accessed bit). No need to be
508 * clever, this is only used from the dirty fault */
509 .macro update_dirty ptp,pte,tmp
510 ldi _PAGE_ACCESSED|_PAGE_DIRTY,\tmp
515 /* We have (depending on the page size):
516 * - 38 to 52-bit Physical Page Number
517 * - 12 to 26-bit page offset
519 /* bitshift difference between a PFN (based on kernel's PAGE_SIZE)
520 * to a CPU TLB 4k PFN (4k => 12 bits to shift) */
521 #define PAGE_ADD_SHIFT (PAGE_SHIFT-12)
522 #define PAGE_ADD_HUGE_SHIFT (REAL_HPAGE_SHIFT-12)
524 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
525 .macro convert_for_tlb_insert20 pte,tmp
526 #ifdef CONFIG_HUGETLB_PAGE
528 extrd,u \tmp,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\
529 64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte
531 depdi _PAGE_SIZE_ENCODING_DEFAULT,63,\
532 (63-58)+PAGE_ADD_SHIFT,\pte
533 extrd,u,*= \tmp,_PAGE_HPAGE_BIT+32,1,%r0
534 depdi _HUGE_PAGE_SIZE_ENCODING_DEFAULT,63,\
535 (63-58)+PAGE_ADD_HUGE_SHIFT,\pte
536 #else /* Huge pages disabled */
537 extrd,u \pte,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\
538 64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte
539 depdi _PAGE_SIZE_ENCODING_DEFAULT,63,\
540 (63-58)+PAGE_ADD_SHIFT,\pte
544 /* Convert the pte and prot to tlb insertion values. How
545 * this happens is quite subtle, read below */
546 .macro make_insert_tlb spc,pte,prot,tmp
547 space_to_prot \spc \prot /* create prot id from space */
548 /* The following is the real subtlety. This is depositing
549 * T <-> _PAGE_REFTRAP
551 * B <-> _PAGE_DMB (memory break)
553 * Then incredible subtlety: The access rights are
554 * _PAGE_GATEWAY, _PAGE_EXEC and _PAGE_WRITE
555 * See 3-14 of the parisc 2.0 manual
557 * Finally, _PAGE_READ goes in the top bit of PL1 (so we
558 * trigger an access rights trap in user space if the user
559 * tries to read an unreadable page */
562 /* PAGE_USER indicates the page can be read with user privileges,
563 * so deposit X1|11 to PL1|PL2 (remember the upper bit of PL1
564 * contains _PAGE_READ) */
565 extrd,u,*= \pte,_PAGE_USER_BIT+32,1,%r0
567 /* If we're a gateway page, drop PL2 back to zero for promotion
568 * to kernel privilege (so we can execute the page as kernel).
569 * Any privilege promotion page always denys read and write */
570 extrd,u,*= \pte,_PAGE_GATEWAY_BIT+32,1,%r0
571 depd %r0,11,2,\prot /* If Gateway, Set PL2 to 0 */
573 /* Enforce uncacheable pages.
574 * This should ONLY be use for MMIO on PA 2.0 machines.
575 * Memory/DMA is cache coherent on all PA2.0 machines we support
576 * (that means T-class is NOT supported) and the memory controllers
577 * on most of those machines only handles cache transactions.
579 extrd,u,*= \pte,_PAGE_NO_CACHE_BIT+32,1,%r0
582 /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
583 convert_for_tlb_insert20 \pte \tmp
586 /* Identical macro to make_insert_tlb above, except it
587 * makes the tlb entry for the differently formatted pa11
588 * insertion instructions */
589 .macro make_insert_tlb_11 spc,pte,prot
590 zdep \spc,30,15,\prot
592 extru,= \pte,_PAGE_NO_CACHE_BIT,1,%r0
594 extru,= \pte,_PAGE_USER_BIT,1,%r0
595 depi 7,11,3,\prot /* Set for user space (1 rsvd for read) */
596 extru,= \pte,_PAGE_GATEWAY_BIT,1,%r0
597 depi 0,11,2,\prot /* If Gateway, Set PL2 to 0 */
599 /* Get rid of prot bits and convert to page addr for iitlba */
601 depi 0,31,ASM_PFN_PTE_SHIFT,\pte
602 SHRREG \pte,(ASM_PFN_PTE_SHIFT-(31-26)),\pte
605 /* This is for ILP32 PA2.0 only. The TLB insertion needs
606 * to extend into I/O space if the address is 0xfXXXXXXX
607 * so we extend the f's into the top word of the pte in
609 .macro f_extend pte,tmp
610 extrd,s \pte,42,4,\tmp
612 extrd,s \pte,63,25,\pte
615 /* The alias region is an 8MB aligned 16MB to do clear and
616 * copy user pages at addresses congruent with the user
619 * To use the alias page, you set %r26 up with the to TLB
620 * entry (identifying the physical page) and %r23 up with
621 * the from tlb entry (or nothing if only a to entry---for
622 * clear_user_page_asm) */
623 .macro do_alias spc,tmp,tmp1,va,pte,prot,fault,patype
624 cmpib,COND(<>),n 0,\spc,\fault
625 ldil L%(TMPALIAS_MAP_START),\tmp
626 #if defined(CONFIG_64BIT) && (TMPALIAS_MAP_START >= 0x80000000)
627 /* on LP64, ldi will sign extend into the upper 32 bits,
628 * which is behaviour we don't want */
633 cmpb,COND(<>),n \tmp,\tmp1,\fault
634 mfctl %cr19,\tmp /* iir */
635 /* get the opcode (first six bits) into \tmp */
636 extrw,u \tmp,5,6,\tmp
638 * Only setting the T bit prevents data cache movein
639 * Setting access rights to zero prevents instruction cache movein
641 * Note subtlety here: _PAGE_GATEWAY, _PAGE_EXEC and _PAGE_WRITE go
642 * to type field and _PAGE_READ goes to top bit of PL1
644 ldi (_PAGE_REFTRAP|_PAGE_READ|_PAGE_WRITE),\prot
646 * so if the opcode is one (i.e. this is a memory management
647 * instruction) nullify the next load so \prot is only T.
648 * Otherwise this is a normal data operation
650 cmpiclr,= 0x01,\tmp,%r0
651 ldi (_PAGE_DIRTY|_PAGE_READ|_PAGE_WRITE),\prot
653 depd,z \prot,8,7,\prot
656 depw,z \prot,8,7,\prot
658 .error "undefined PA type to do_alias"
662 * OK, it is in the temp alias region, check whether "from" or "to".
663 * Check "subtle" note in pacache.S re: r23/r26.
666 extrd,u,*= \va,41,1,%r0
668 extrw,u,= \va,9,1,%r0
670 or,COND(tr) %r23,%r0,\pte
676 * Fault_vectors are architecturally required to be aligned on a 2K
683 ENTRY(fault_vector_20)
684 /* First vector is invalid (0) */
685 .ascii "cows can fly"
694 itlb_20 PARISC_ITLB_TRAP
726 ENTRY(fault_vector_11)
727 /* First vector is invalid (0) */
728 .ascii "cows can fly"
737 itlb_11 PARISC_ITLB_TRAP
766 /* Fault vector is separately protected and *must* be on its own page */
769 .import handle_interruption,code
770 .import do_cpu_irq_mask,code
775 * copy_thread moved args into task save area.
778 ENTRY(ret_from_kernel_thread)
779 /* Call schedule_tail first though */
780 BL schedule_tail, %r2
783 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
784 LDREG TASK_PT_GR25(%r1), %r26
786 LDREG TASK_PT_GR27(%r1), %r27
788 LDREG TASK_PT_GR26(%r1), %r1
791 b finish_child_return
793 END(ret_from_kernel_thread)
797 * struct task_struct *_switch_to(struct task_struct *prev,
798 * struct task_struct *next)
800 * switch kernel stacks and return prev */
801 ENTRY_CFI(_switch_to)
802 STREG %r2, -RP_OFFSET(%r30)
807 load32 _switch_to_ret, %r2
809 STREG %r2, TASK_PT_KPC(%r26)
810 LDREG TASK_PT_KPC(%r25), %r2
812 STREG %r30, TASK_PT_KSP(%r26)
813 LDREG TASK_PT_KSP(%r25), %r30
814 LDREG TASK_THREAD_INFO(%r25), %r25
818 ENTRY(_switch_to_ret)
819 mtctl %r0, %cr0 /* Needed for single stepping */
823 LDREG -RP_OFFSET(%r30), %r2
826 ENDPROC_CFI(_switch_to)
829 * Common rfi return path for interruptions, kernel execve, and
830 * sys_rt_sigreturn (sometimes). The sys_rt_sigreturn syscall will
831 * return via this path if the signal was received when the process
832 * was running; if the process was blocked on a syscall then the
833 * normal syscall_exit path is used. All syscalls for traced
834 * proceses exit via intr_restore.
836 * XXX If any syscalls that change a processes space id ever exit
837 * this way, then we will need to copy %sr3 in to PT_SR[3..7], and
844 ENTRY_CFI(syscall_exit_rfi)
846 LDREG TI_TASK(%r16), %r16 /* thread_info -> task_struct */
847 ldo TASK_REGS(%r16),%r16
848 /* Force iaoq to userspace, as the user has had access to our current
849 * context via sigcontext. Also Filter the PSW for the same reason.
851 LDREG PT_IAOQ0(%r16),%r19
853 STREG %r19,PT_IAOQ0(%r16)
854 LDREG PT_IAOQ1(%r16),%r19
856 STREG %r19,PT_IAOQ1(%r16)
857 LDREG PT_PSW(%r16),%r19
858 load32 USER_PSW_MASK,%r1
860 load32 USER_PSW_HI_MASK,%r20
863 and %r19,%r1,%r19 /* Mask out bits that user shouldn't play with */
865 or %r19,%r1,%r19 /* Make sure default USER_PSW bits are set */
866 STREG %r19,PT_PSW(%r16)
869 * If we aren't being traced, we never saved space registers
870 * (we don't store them in the sigcontext), so set them
871 * to "proper" values now (otherwise we'll wind up restoring
872 * whatever was last stored in the task structure, which might
873 * be inconsistent if an interrupt occurred while on the gateway
874 * page). Note that we may be "trashing" values the user put in
875 * them, but we don't support the user changing them.
878 STREG %r0,PT_SR2(%r16)
880 STREG %r19,PT_SR0(%r16)
881 STREG %r19,PT_SR1(%r16)
882 STREG %r19,PT_SR3(%r16)
883 STREG %r19,PT_SR4(%r16)
884 STREG %r19,PT_SR5(%r16)
885 STREG %r19,PT_SR6(%r16)
886 STREG %r19,PT_SR7(%r16)
889 /* check for reschedule */
891 LDREG TI_FLAGS(%r1),%r19 /* sched.h: TIF_NEED_RESCHED */
892 bb,<,n %r19,31-TIF_NEED_RESCHED,intr_do_resched /* forward */
894 .import do_notify_resume,code
898 LDREG TI_FLAGS(%r1),%r19
899 ldi (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME), %r20
900 and,COND(<>) %r19, %r20, %r0
901 b,n intr_restore /* skip past if we've nothing to do */
903 /* This check is critical to having LWS
904 * working. The IASQ is zero on the gateway
905 * page and we cannot deliver any signals until
906 * we get off the gateway page.
908 * Only do signals if we are returning to user space
910 LDREG PT_IASQ0(%r16), %r20
911 cmpib,COND(=),n 0,%r20,intr_restore /* backward */
912 LDREG PT_IASQ1(%r16), %r20
913 cmpib,COND(=),n 0,%r20,intr_restore /* backward */
915 /* NOTE: We need to enable interrupts if we have to deliver
916 * signals. We used to do this earlier but it caused kernel
917 * stack overflows. */
920 copy %r0, %r25 /* long in_syscall = 0 */
922 ldo -16(%r30),%r29 /* Reference param save area */
925 BL do_notify_resume,%r2
926 copy %r16, %r26 /* struct pt_regs *regs */
932 ldo PT_FR31(%r29),%r1
936 /* inverse of virt_map */
938 rsm PSW_SM_QUIET,%r0 /* prepare for rfi */
941 /* Restore space id's and special cr's from PT_REGS
942 * structure pointed to by r29
946 /* IMPORTANT: rest_stack restores r29 last (we are using it)!
947 * It also restores r1 and r30.
954 #ifndef CONFIG_PREEMPT
955 # define intr_do_preempt intr_restore
956 #endif /* !CONFIG_PREEMPT */
958 .import schedule,code
960 /* Only call schedule on return to userspace. If we're returning
961 * to kernel space, we may schedule if CONFIG_PREEMPT, otherwise
962 * we jump back to intr_restore.
964 LDREG PT_IASQ0(%r16), %r20
965 cmpib,COND(=) 0, %r20, intr_do_preempt
967 LDREG PT_IASQ1(%r16), %r20
968 cmpib,COND(=) 0, %r20, intr_do_preempt
971 /* NOTE: We need to enable interrupts if we schedule. We used
972 * to do this earlier but it caused kernel stack overflows. */
976 ldo -16(%r30),%r29 /* Reference param save area */
979 ldil L%intr_check_sig, %r2
983 load32 schedule, %r20
986 ldo R%intr_check_sig(%r2), %r2
988 /* preempt the current task on returning to kernel
989 * mode from an interrupt, iff need_resched is set,
990 * and preempt_count is 0. otherwise, we continue on
991 * our merry way back to the current running task.
993 #ifdef CONFIG_PREEMPT
994 .import preempt_schedule_irq,code
996 rsm PSW_SM_I, %r0 /* disable interrupts */
998 /* current_thread_info()->preempt_count */
1000 LDREG TI_PRE_COUNT(%r1), %r19
1001 cmpib,COND(<>) 0, %r19, intr_restore /* if preempt_count > 0 */
1002 nop /* prev insn branched backwards */
1004 /* check if we interrupted a critical path */
1005 LDREG PT_PSW(%r16), %r20
1006 bb,<,n %r20, 31 - PSW_SM_I, intr_restore
1009 BL preempt_schedule_irq, %r2
1012 b,n intr_restore /* ssm PSW_SM_I done by intr_restore */
1013 #endif /* CONFIG_PREEMPT */
1016 * External interrupts.
1020 cmpib,COND(=),n 0,%r16,1f
1032 ldo PT_FR0(%r29), %r24
1037 copy %r29, %r26 /* arg0 is pt_regs */
1038 copy %r29, %r16 /* save pt_regs */
1040 ldil L%intr_return, %r2
1043 ldo -16(%r30),%r29 /* Reference param save area */
1047 ldo R%intr_return(%r2), %r2 /* return to intr_return, not here */
1048 ENDPROC_CFI(syscall_exit_rfi)
1051 /* Generic interruptions (illegal insn, unaligned, page fault, etc) */
1053 ENTRY_CFI(intr_save) /* for os_hpmc */
1055 cmpib,COND(=),n 0,%r16,1f
1067 /* If this trap is a itlb miss, skip saving/adjusting isr/ior */
1068 cmpib,COND(=),n PARISC_ITLB_TRAP,%r26,skip_save_ior
1072 nop /* serialize mfctl on PA 2.0 to avoid 4 cycle penalty */
1078 * If the interrupted code was running with W bit off (32 bit),
1079 * clear the b bits (bits 0 & 1) in the ior.
1080 * save_specials left ipsw value in r8 for us to test.
1082 extrd,u,*<> %r8,PSW_W_BIT,1,%r0
1085 /* adjust isr/ior: get high bits from isr and deposit in ior */
1086 space_adjust %r16,%r17,%r1
1088 STREG %r16, PT_ISR(%r29)
1089 STREG %r17, PT_IOR(%r29)
1091 #if 0 && defined(CONFIG_64BIT)
1092 /* Revisit when we have 64-bit code above 4Gb */
1096 /* We have a itlb miss, and when executing code above 4 Gb on ILP64, we
1097 * need to adjust iasq/iaoq here in the same way we adjusted isr/ior
1100 extrd,u,* %r8,PSW_W_BIT,1,%r1
1101 cmpib,COND(=),n 1,%r1,intr_save2
1102 LDREG PT_IASQ0(%r29), %r16
1103 LDREG PT_IAOQ0(%r29), %r17
1104 /* adjust iasq/iaoq */
1105 space_adjust %r16,%r17,%r1
1106 STREG %r16, PT_IASQ0(%r29)
1107 STREG %r17, PT_IAOQ0(%r29)
1116 ldo PT_FR0(%r29), %r25
1121 copy %r29, %r25 /* arg1 is pt_regs */
1123 ldo -16(%r30),%r29 /* Reference param save area */
1126 ldil L%intr_check_sig, %r2
1127 copy %r25, %r16 /* save pt_regs */
1129 b handle_interruption
1130 ldo R%intr_check_sig(%r2), %r2
1131 ENDPROC_CFI(intr_save)
1135 * Note for all tlb miss handlers:
1137 * cr24 contains a pointer to the kernel address space
1140 * cr25 contains a pointer to the current user address
1141 * space page directory.
1143 * sr3 will contain the space id of the user address space
1144 * of the current running thread while that thread is
1145 * running in the kernel.
1149 * register number allocations. Note that these are all
1150 * in the shadowed registers
1153 t0 = r1 /* temporary register 0 */
1154 va = r8 /* virtual address for which the trap occurred */
1155 t1 = r9 /* temporary register 1 */
1156 pte = r16 /* pte/phys page # */
1157 prot = r17 /* prot bits */
1158 spc = r24 /* space for which the trap occurred */
1159 ptp = r25 /* page directory/page table pointer */
1164 space_adjust spc,va,t0
1166 space_check spc,t0,dtlb_fault
1168 L3_ptep ptp,pte,t0,va,dtlb_check_alias_20w
1170 tlb_lock spc,ptp,pte,t0,t1,dtlb_check_alias_20w
1171 update_accessed ptp,pte,t0,t1
1173 make_insert_tlb spc,pte,prot,t1
1181 dtlb_check_alias_20w:
1182 do_alias spc,t0,t1,va,pte,prot,dtlb_fault,20
1190 space_adjust spc,va,t0
1192 space_check spc,t0,nadtlb_fault
1194 L3_ptep ptp,pte,t0,va,nadtlb_check_alias_20w
1196 tlb_lock spc,ptp,pte,t0,t1,nadtlb_check_alias_20w
1197 update_accessed ptp,pte,t0,t1
1199 make_insert_tlb spc,pte,prot,t1
1207 nadtlb_check_alias_20w:
1208 do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,20
1220 space_check spc,t0,dtlb_fault
1222 L2_ptep ptp,pte,t0,va,dtlb_check_alias_11
1224 tlb_lock spc,ptp,pte,t0,t1,dtlb_check_alias_11
1225 update_accessed ptp,pte,t0,t1
1227 make_insert_tlb_11 spc,pte,prot
1229 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1232 idtlba pte,(%sr1,va)
1233 idtlbp prot,(%sr1,va)
1235 mtsp t1, %sr1 /* Restore sr1 */
1241 dtlb_check_alias_11:
1242 do_alias spc,t0,t1,va,pte,prot,dtlb_fault,11
1253 space_check spc,t0,nadtlb_fault
1255 L2_ptep ptp,pte,t0,va,nadtlb_check_alias_11
1257 tlb_lock spc,ptp,pte,t0,t1,nadtlb_check_alias_11
1258 update_accessed ptp,pte,t0,t1
1260 make_insert_tlb_11 spc,pte,prot
1262 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1265 idtlba pte,(%sr1,va)
1266 idtlbp prot,(%sr1,va)
1268 mtsp t1, %sr1 /* Restore sr1 */
1274 nadtlb_check_alias_11:
1275 do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,11
1284 space_adjust spc,va,t0
1286 space_check spc,t0,dtlb_fault
1288 L2_ptep ptp,pte,t0,va,dtlb_check_alias_20
1290 tlb_lock spc,ptp,pte,t0,t1,dtlb_check_alias_20
1291 update_accessed ptp,pte,t0,t1
1293 make_insert_tlb spc,pte,prot,t1
1303 dtlb_check_alias_20:
1304 do_alias spc,t0,t1,va,pte,prot,dtlb_fault,20
1314 space_check spc,t0,nadtlb_fault
1316 L2_ptep ptp,pte,t0,va,nadtlb_check_alias_20
1318 tlb_lock spc,ptp,pte,t0,t1,nadtlb_check_alias_20
1319 update_accessed ptp,pte,t0,t1
1321 make_insert_tlb spc,pte,prot,t1
1331 nadtlb_check_alias_20:
1332 do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,20
1344 * Non access misses can be caused by fdc,fic,pdc,lpa,probe and
1345 * probei instructions. We don't want to fault for these
1346 * instructions (not only does it not make sense, it can cause
1347 * deadlocks, since some flushes are done with the mmap
1348 * semaphore held). If the translation doesn't exist, we can't
1349 * insert a translation, so have to emulate the side effects
1350 * of the instruction. Since we don't insert a translation
1351 * we can get a lot of faults during a flush loop, so it makes
1352 * sense to try to do it here with minimum overhead. We only
1353 * emulate fdc,fic,pdc,probew,prober instructions whose base
1354 * and index registers are not shadowed. We defer everything
1355 * else to the "slow" path.
1358 mfctl %cr19,%r9 /* Get iir */
1360 /* PA 2.0 Arch Ref. Book pg 382 has a good description of the insn bits.
1361 Checks for fdc,fdce,pdc,"fic,4f",prober,probeir,probew, probeiw */
1363 /* Checks for fdc,fdce,pdc,"fic,4f" only */
1366 cmpb,<>,n %r16,%r17,nadtlb_probe_check
1367 bb,>=,n %r9,26,nadtlb_nullify /* m bit not set, just nullify */
1368 BL get_register,%r25
1369 extrw,u %r9,15,5,%r8 /* Get index register # */
1370 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1372 BL get_register,%r25
1373 extrw,u %r9,10,5,%r8 /* Get base register # */
1374 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1375 BL set_register,%r25
1376 add,l %r1,%r24,%r1 /* doesn't affect c/b bits */
1381 or %r8,%r9,%r8 /* Set PSW_N */
1388 When there is no translation for the probe address then we
1389 must nullify the insn and return zero in the target register.
1390 This will indicate to the calling code that it does not have
1391 write/read privileges to this address.
1393 This should technically work for prober and probew in PA 1.1,
1394 and also probe,r and probe,w in PA 2.0
1396 WARNING: USE ONLY NON-SHADOW REGISTERS WITH PROBE INSN!
1397 THE SLOW-PATH EMULATION HAS NOT BEEN WRITTEN YET.
1403 cmpb,<>,n %r16,%r17,nadtlb_fault /* Must be probe,[rw]*/
1404 BL get_register,%r25 /* Find the target register */
1405 extrw,u %r9,31,5,%r8 /* Get target register */
1406 cmpib,COND(=),n -1,%r1,nadtlb_fault /* have to use slow path */
1407 BL set_register,%r25
1408 copy %r0,%r1 /* Write zero to target register */
1409 b nadtlb_nullify /* Nullify return insn */
1417 * I miss is a little different, since we allow users to fault
1418 * on the gateway page which is in the kernel address space.
1421 space_adjust spc,va,t0
1423 space_check spc,t0,itlb_fault
1425 L3_ptep ptp,pte,t0,va,itlb_fault
1427 tlb_lock spc,ptp,pte,t0,t1,itlb_fault
1428 update_accessed ptp,pte,t0,t1
1430 make_insert_tlb spc,pte,prot,t1
1441 * I miss is a little different, since we allow users to fault
1442 * on the gateway page which is in the kernel address space.
1445 space_adjust spc,va,t0
1447 space_check spc,t0,naitlb_fault
1449 L3_ptep ptp,pte,t0,va,naitlb_check_alias_20w
1451 tlb_lock spc,ptp,pte,t0,t1,naitlb_check_alias_20w
1452 update_accessed ptp,pte,t0,t1
1454 make_insert_tlb spc,pte,prot,t1
1462 naitlb_check_alias_20w:
1463 do_alias spc,t0,t1,va,pte,prot,naitlb_fault,20
1475 space_check spc,t0,itlb_fault
1477 L2_ptep ptp,pte,t0,va,itlb_fault
1479 tlb_lock spc,ptp,pte,t0,t1,itlb_fault
1480 update_accessed ptp,pte,t0,t1
1482 make_insert_tlb_11 spc,pte,prot
1484 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1487 iitlba pte,(%sr1,va)
1488 iitlbp prot,(%sr1,va)
1490 mtsp t1, %sr1 /* Restore sr1 */
1499 space_check spc,t0,naitlb_fault
1501 L2_ptep ptp,pte,t0,va,naitlb_check_alias_11
1503 tlb_lock spc,ptp,pte,t0,t1,naitlb_check_alias_11
1504 update_accessed ptp,pte,t0,t1
1506 make_insert_tlb_11 spc,pte,prot
1508 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1511 iitlba pte,(%sr1,va)
1512 iitlbp prot,(%sr1,va)
1514 mtsp t1, %sr1 /* Restore sr1 */
1520 naitlb_check_alias_11:
1521 do_alias spc,t0,t1,va,pte,prot,itlb_fault,11
1523 iitlba pte,(%sr0, va)
1524 iitlbp prot,(%sr0, va)
1533 space_check spc,t0,itlb_fault
1535 L2_ptep ptp,pte,t0,va,itlb_fault
1537 tlb_lock spc,ptp,pte,t0,t1,itlb_fault
1538 update_accessed ptp,pte,t0,t1
1540 make_insert_tlb spc,pte,prot,t1
1553 space_check spc,t0,naitlb_fault
1555 L2_ptep ptp,pte,t0,va,naitlb_check_alias_20
1557 tlb_lock spc,ptp,pte,t0,t1,naitlb_check_alias_20
1558 update_accessed ptp,pte,t0,t1
1560 make_insert_tlb spc,pte,prot,t1
1570 naitlb_check_alias_20:
1571 do_alias spc,t0,t1,va,pte,prot,naitlb_fault,20
1583 space_adjust spc,va,t0
1585 space_check spc,t0,dbit_fault
1587 L3_ptep ptp,pte,t0,va,dbit_fault
1589 tlb_lock spc,ptp,pte,t0,t1,dbit_fault
1590 update_dirty ptp,pte,t1
1592 make_insert_tlb spc,pte,prot,t1
1605 space_check spc,t0,dbit_fault
1607 L2_ptep ptp,pte,t0,va,dbit_fault
1609 tlb_lock spc,ptp,pte,t0,t1,dbit_fault
1610 update_dirty ptp,pte,t1
1612 make_insert_tlb_11 spc,pte,prot
1614 mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
1617 idtlba pte,(%sr1,va)
1618 idtlbp prot,(%sr1,va)
1620 mtsp t1, %sr1 /* Restore sr1 */
1629 space_check spc,t0,dbit_fault
1631 L2_ptep ptp,pte,t0,va,dbit_fault
1633 tlb_lock spc,ptp,pte,t0,t1,dbit_fault
1634 update_dirty ptp,pte,t1
1636 make_insert_tlb spc,pte,prot,t1
1647 .import handle_interruption,code
1651 ldi 31,%r8 /* Use an unused code */
1659 ldi PARISC_ITLB_TRAP,%r8
1673 /* Register saving semantics for system calls:
1675 %r1 clobbered by system call macro in userspace
1676 %r2 saved in PT_REGS by gateway page
1677 %r3 - %r18 preserved by C code (saved by signal code)
1678 %r19 - %r20 saved in PT_REGS by gateway page
1679 %r21 - %r22 non-standard syscall args
1680 stored in kernel stack by gateway page
1681 %r23 - %r26 arg3-arg0, saved in PT_REGS by gateway page
1682 %r27 - %r30 saved in PT_REGS by gateway page
1683 %r31 syscall return pointer
1686 /* Floating point registers (FIXME: what do we do with these?)
1688 %fr0 - %fr3 status/exception, not preserved
1689 %fr4 - %fr7 arguments
1690 %fr8 - %fr11 not preserved by C code
1691 %fr12 - %fr21 preserved by C code
1692 %fr22 - %fr31 not preserved by C code
1695 .macro reg_save regs
1696 STREG %r3, PT_GR3(\regs)
1697 STREG %r4, PT_GR4(\regs)
1698 STREG %r5, PT_GR5(\regs)
1699 STREG %r6, PT_GR6(\regs)
1700 STREG %r7, PT_GR7(\regs)
1701 STREG %r8, PT_GR8(\regs)
1702 STREG %r9, PT_GR9(\regs)
1703 STREG %r10,PT_GR10(\regs)
1704 STREG %r11,PT_GR11(\regs)
1705 STREG %r12,PT_GR12(\regs)
1706 STREG %r13,PT_GR13(\regs)
1707 STREG %r14,PT_GR14(\regs)
1708 STREG %r15,PT_GR15(\regs)
1709 STREG %r16,PT_GR16(\regs)
1710 STREG %r17,PT_GR17(\regs)
1711 STREG %r18,PT_GR18(\regs)
1714 .macro reg_restore regs
1715 LDREG PT_GR3(\regs), %r3
1716 LDREG PT_GR4(\regs), %r4
1717 LDREG PT_GR5(\regs), %r5
1718 LDREG PT_GR6(\regs), %r6
1719 LDREG PT_GR7(\regs), %r7
1720 LDREG PT_GR8(\regs), %r8
1721 LDREG PT_GR9(\regs), %r9
1722 LDREG PT_GR10(\regs),%r10
1723 LDREG PT_GR11(\regs),%r11
1724 LDREG PT_GR12(\regs),%r12
1725 LDREG PT_GR13(\regs),%r13
1726 LDREG PT_GR14(\regs),%r14
1727 LDREG PT_GR15(\regs),%r15
1728 LDREG PT_GR16(\regs),%r16
1729 LDREG PT_GR17(\regs),%r17
1730 LDREG PT_GR18(\regs),%r18
1733 .macro fork_like name
1734 ENTRY_CFI(sys_\name\()_wrapper)
1735 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1736 ldo TASK_REGS(%r1),%r1
1739 ldil L%sys_\name, %r31
1740 be R%sys_\name(%sr4,%r31)
1741 STREG %r28, PT_CR27(%r1)
1742 ENDPROC_CFI(sys_\name\()_wrapper)
1749 /* Set the return value for the child */
1751 BL schedule_tail, %r2
1753 finish_child_return:
1754 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30), %r1
1755 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1757 LDREG PT_CR27(%r1), %r3
1764 ENTRY_CFI(sys_rt_sigreturn_wrapper)
1765 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r26
1766 ldo TASK_REGS(%r26),%r26 /* get pt regs */
1767 /* Don't save regs, we are going to restore them from sigcontext. */
1768 STREG %r2, -RP_OFFSET(%r30)
1770 ldo FRAME_SIZE(%r30), %r30
1771 BL sys_rt_sigreturn,%r2
1772 ldo -16(%r30),%r29 /* Reference param save area */
1774 BL sys_rt_sigreturn,%r2
1775 ldo FRAME_SIZE(%r30), %r30
1778 ldo -FRAME_SIZE(%r30), %r30
1779 LDREG -RP_OFFSET(%r30), %r2
1781 /* FIXME: I think we need to restore a few more things here. */
1782 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1783 ldo TASK_REGS(%r1),%r1 /* get pt regs */
1786 /* If the signal was received while the process was blocked on a
1787 * syscall, then r2 will take us to syscall_exit; otherwise r2 will
1788 * take us to syscall_exit_rfi and on to intr_return.
1791 LDREG PT_GR28(%r1),%r28 /* reload original r28 for syscall_exit */
1792 ENDPROC_CFI(sys_rt_sigreturn_wrapper)
1795 /* NOTE: Not all syscalls exit this way. rt_sigreturn will exit
1796 * via syscall_exit_rfi if the signal was received while the process
1800 /* save return value now */
1803 LDREG TI_TASK(%r1),%r1
1804 STREG %r28,TASK_PT_GR28(%r1)
1806 /* Seems to me that dp could be wrong here, if the syscall involved
1807 * calling a module, and nothing got round to restoring dp on return.
1811 syscall_check_resched:
1813 /* check for reschedule */
1815 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19 /* long */
1816 bb,<,n %r19, 31-TIF_NEED_RESCHED, syscall_do_resched /* forward */
1818 .import do_signal,code
1820 LDREG TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19
1821 ldi (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME), %r26
1822 and,COND(<>) %r19, %r26, %r0
1823 b,n syscall_restore /* skip past if we've nothing to do */
1826 /* Save callee-save registers (for sigcontext).
1827 * FIXME: After this point the process structure should be
1828 * consistent with all the relevant state of the process
1829 * before the syscall. We need to verify this.
1831 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1832 ldo TASK_REGS(%r1), %r26 /* struct pt_regs *regs */
1836 ldo -16(%r30),%r29 /* Reference param save area */
1839 BL do_notify_resume,%r2
1840 ldi 1, %r25 /* long in_syscall = 1 */
1842 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1843 ldo TASK_REGS(%r1), %r20 /* reload pt_regs */
1846 b,n syscall_check_sig
1849 LDREG TI_TASK-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r1
1851 /* Are we being ptraced? */
1852 ldw TASK_FLAGS(%r1),%r19
1853 ldi _TIF_SYSCALL_TRACE_MASK,%r2
1854 and,COND(=) %r19,%r2,%r0
1855 b,n syscall_restore_rfi
1857 ldo TASK_PT_FR31(%r1),%r19 /* reload fpregs */
1860 LDREG TASK_PT_SAR(%r1),%r19 /* restore SAR */
1863 LDREG TASK_PT_GR2(%r1),%r2 /* restore user rp */
1864 LDREG TASK_PT_GR19(%r1),%r19
1865 LDREG TASK_PT_GR20(%r1),%r20
1866 LDREG TASK_PT_GR21(%r1),%r21
1867 LDREG TASK_PT_GR22(%r1),%r22
1868 LDREG TASK_PT_GR23(%r1),%r23
1869 LDREG TASK_PT_GR24(%r1),%r24
1870 LDREG TASK_PT_GR25(%r1),%r25
1871 LDREG TASK_PT_GR26(%r1),%r26
1872 LDREG TASK_PT_GR27(%r1),%r27 /* restore user dp */
1873 LDREG TASK_PT_GR28(%r1),%r28 /* syscall return value */
1874 LDREG TASK_PT_GR29(%r1),%r29
1875 LDREG TASK_PT_GR31(%r1),%r31 /* restore syscall rp */
1877 /* NOTE: We use rsm/ssm pair to make this operation atomic */
1878 LDREG TASK_PT_GR30(%r1),%r1 /* Get user sp */
1880 copy %r1,%r30 /* Restore user sp */
1881 mfsp %sr3,%r1 /* Get user space id */
1882 mtsp %r1,%sr7 /* Restore sr7 */
1885 /* Set sr2 to zero for userspace syscalls to work. */
1887 mtsp %r1,%sr4 /* Restore sr4 */
1888 mtsp %r1,%sr5 /* Restore sr5 */
1889 mtsp %r1,%sr6 /* Restore sr6 */
1891 depi 3,31,2,%r31 /* ensure return to user mode. */
1894 /* decide whether to reset the wide mode bit
1896 * For a syscall, the W bit is stored in the lowest bit
1897 * of sp. Extract it and reset W if it is zero */
1898 extrd,u,*<> %r30,63,1,%r1
1900 /* now reset the lowest bit of sp if it was set */
1903 be,n 0(%sr3,%r31) /* return to user space */
1905 /* We have to return via an RFI, so that PSW T and R bits can be set
1907 * This sets up pt_regs so we can return via intr_restore, which is not
1908 * the most efficient way of doing things, but it works.
1910 syscall_restore_rfi:
1911 ldo -1(%r0),%r2 /* Set recovery cntr to -1 */
1912 mtctl %r2,%cr0 /* for immediate trap */
1913 LDREG TASK_PT_PSW(%r1),%r2 /* Get old PSW */
1914 ldi 0x0b,%r20 /* Create new PSW */
1915 depi -1,13,1,%r20 /* C, Q, D, and I bits */
1917 /* The values of SINGLESTEP_BIT and BLOCKSTEP_BIT are
1918 * set in thread_info.h and converted to PA bitmap
1919 * numbers in asm-offsets.c */
1921 /* if ((%r19.SINGLESTEP_BIT)) { %r20.27=1} */
1922 extru,= %r19,TIF_SINGLESTEP_PA_BIT,1,%r0
1923 depi -1,27,1,%r20 /* R bit */
1925 /* if ((%r19.BLOCKSTEP_BIT)) { %r20.7=1} */
1926 extru,= %r19,TIF_BLOCKSTEP_PA_BIT,1,%r0
1927 depi -1,7,1,%r20 /* T bit */
1929 STREG %r20,TASK_PT_PSW(%r1)
1931 /* Always store space registers, since sr3 can be changed (e.g. fork) */
1934 STREG %r25,TASK_PT_SR3(%r1)
1935 STREG %r25,TASK_PT_SR4(%r1)
1936 STREG %r25,TASK_PT_SR5(%r1)
1937 STREG %r25,TASK_PT_SR6(%r1)
1938 STREG %r25,TASK_PT_SR7(%r1)
1939 STREG %r25,TASK_PT_IASQ0(%r1)
1940 STREG %r25,TASK_PT_IASQ1(%r1)
1943 /* Now if old D bit is clear, it means we didn't save all registers
1944 * on syscall entry, so do that now. This only happens on TRACEME
1945 * calls, or if someone attached to us while we were on a syscall.
1946 * We could make this more efficient by not saving r3-r18, but
1947 * then we wouldn't be able to use the common intr_restore path.
1948 * It is only for traced processes anyway, so performance is not
1951 bb,< %r2,30,pt_regs_ok /* Branch if D set */
1952 ldo TASK_REGS(%r1),%r25
1953 reg_save %r25 /* Save r3 to r18 */
1955 /* Save the current sr */
1957 STREG %r2,TASK_PT_SR0(%r1)
1959 /* Save the scratch sr */
1961 STREG %r2,TASK_PT_SR1(%r1)
1963 /* sr2 should be set to zero for userspace syscalls */
1964 STREG %r0,TASK_PT_SR2(%r1)
1966 LDREG TASK_PT_GR31(%r1),%r2
1967 depi 3,31,2,%r2 /* ensure return to user mode. */
1968 STREG %r2,TASK_PT_IAOQ0(%r1)
1970 STREG %r2,TASK_PT_IAOQ1(%r1)
1975 LDREG TASK_PT_IAOQ0(%r1),%r2
1976 depi 3,31,2,%r2 /* ensure return to user mode. */
1977 STREG %r2,TASK_PT_IAOQ0(%r1)
1978 LDREG TASK_PT_IAOQ1(%r1),%r2
1980 STREG %r2,TASK_PT_IAOQ1(%r1)
1985 load32 syscall_check_resched,%r2 /* if resched, we start over again */
1986 load32 schedule,%r19
1987 bv %r0(%r19) /* jumps to schedule() */
1989 ldo -16(%r30),%r29 /* Reference param save area */
1996 #ifdef CONFIG_FUNCTION_TRACER
1998 .import ftrace_function_trampoline,code
1999 .align L1_CACHE_BYTES
2000 ENTRY_CFI(mcount, caller)
2002 .export _mcount,data
2004 * The 64bit mcount() function pointer needs 4 dwords, of which the
2005 * first two are free. We optimize it here and put 2 instructions for
2006 * calling mcount(), and 2 instructions for ftrace_stub(). That way we
2007 * have all on one L1 cacheline.
2009 b ftrace_function_trampoline
2010 copy %r3, %arg2 /* caller original %sp */
2013 .type ftrace_stub, @function
2022 .dword 0 /* code in head.S puts value of global gp here */
2026 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2028 ENTRY_CFI(return_to_handler, caller,frame=FRAME_SIZE)
2029 .export parisc_return_to_handler,data
2030 parisc_return_to_handler:
2032 STREG %r0,-RP_OFFSET(%sp) /* store 0 as %rp */
2034 STREGM %r1,FRAME_SIZE(%sp)
2042 /* call ftrace_return_to_handler(0) */
2043 .import ftrace_return_to_handler,code
2044 load32 ftrace_return_to_handler,%ret0
2045 load32 .Lftrace_ret,%r2
2047 ldo -16(%sp),%ret1 /* Reference param save area */
2056 /* restore original return values */
2060 /* return from function */
2066 LDREGM -FRAME_SIZE(%sp),%r3
2067 ENDPROC_CFI(return_to_handler)
2069 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
2071 #endif /* CONFIG_FUNCTION_TRACER */
2073 #ifdef CONFIG_IRQSTACKS
2074 /* void call_on_stack(unsigned long param1, void *func,
2075 unsigned long new_stack) */
2076 ENTRY_CFI(call_on_stack, FRAME=2*FRAME_SIZE,CALLS,SAVE_RP,SAVE_SP)
2077 ENTRY(_call_on_stack)
2080 /* Regarding the HPPA calling conventions for function pointers,
2081 we assume the PIC register is not changed across call. For
2082 CONFIG_64BIT, the argument pointer is left to point at the
2083 argument region allocated for the call to call_on_stack. */
2085 /* Switch to new stack. We allocate two frames. */
2086 ldo 2*FRAME_SIZE(%arg2), %sp
2087 # ifdef CONFIG_64BIT
2088 /* Save previous stack pointer and return pointer in frame marker */
2089 STREG %rp, -FRAME_SIZE-RP_OFFSET(%sp)
2090 /* Calls always use function descriptor */
2091 LDREG 16(%arg1), %arg1
2093 STREG %r1, -FRAME_SIZE-REG_SZ(%sp)
2094 LDREG -FRAME_SIZE-RP_OFFSET(%sp), %rp
2096 LDREG -FRAME_SIZE-REG_SZ(%sp), %sp
2098 /* Save previous stack pointer and return pointer in frame marker */
2099 STREG %r1, -FRAME_SIZE-REG_SZ(%sp)
2100 STREG %rp, -FRAME_SIZE-RP_OFFSET(%sp)
2101 /* Calls use function descriptor if PLABEL bit is set */
2102 bb,>=,n %arg1, 30, 1f
2104 LDREG 0(%arg1), %arg1
2106 be,l 0(%sr4,%arg1), %sr0, %r31
2108 LDREG -FRAME_SIZE-RP_OFFSET(%sp), %rp
2110 LDREG -FRAME_SIZE-REG_SZ(%sp), %sp
2111 # endif /* CONFIG_64BIT */
2112 ENDPROC_CFI(call_on_stack)
2113 #endif /* CONFIG_IRQSTACKS */
2115 ENTRY_CFI(get_register)
2117 * get_register is used by the non access tlb miss handlers to
2118 * copy the value of the general register specified in r8 into
2119 * r1. This routine can't be used for shadowed registers, since
2120 * the rfir will restore the original value. So, for the shadowed
2121 * registers we put a -1 into r1 to indicate that the register
2122 * should not be used (the register being copied could also have
2123 * a -1 in it, but that is OK, it just means that we will have
2124 * to use the slow path instead).
2128 bv %r0(%r25) /* r0 */
2130 bv %r0(%r25) /* r1 - shadowed */
2132 bv %r0(%r25) /* r2 */
2134 bv %r0(%r25) /* r3 */
2136 bv %r0(%r25) /* r4 */
2138 bv %r0(%r25) /* r5 */
2140 bv %r0(%r25) /* r6 */
2142 bv %r0(%r25) /* r7 */
2144 bv %r0(%r25) /* r8 - shadowed */
2146 bv %r0(%r25) /* r9 - shadowed */
2148 bv %r0(%r25) /* r10 */
2150 bv %r0(%r25) /* r11 */
2152 bv %r0(%r25) /* r12 */
2154 bv %r0(%r25) /* r13 */
2156 bv %r0(%r25) /* r14 */
2158 bv %r0(%r25) /* r15 */
2160 bv %r0(%r25) /* r16 - shadowed */
2162 bv %r0(%r25) /* r17 - shadowed */
2164 bv %r0(%r25) /* r18 */
2166 bv %r0(%r25) /* r19 */
2168 bv %r0(%r25) /* r20 */
2170 bv %r0(%r25) /* r21 */
2172 bv %r0(%r25) /* r22 */
2174 bv %r0(%r25) /* r23 */
2176 bv %r0(%r25) /* r24 - shadowed */
2178 bv %r0(%r25) /* r25 - shadowed */
2180 bv %r0(%r25) /* r26 */
2182 bv %r0(%r25) /* r27 */
2184 bv %r0(%r25) /* r28 */
2186 bv %r0(%r25) /* r29 */
2188 bv %r0(%r25) /* r30 */
2190 bv %r0(%r25) /* r31 */
2192 ENDPROC_CFI(get_register)
2195 ENTRY_CFI(set_register)
2197 * set_register is used by the non access tlb miss handlers to
2198 * copy the value of r1 into the general register specified in
2203 bv %r0(%r25) /* r0 (silly, but it is a place holder) */
2205 bv %r0(%r25) /* r1 */
2207 bv %r0(%r25) /* r2 */
2209 bv %r0(%r25) /* r3 */
2211 bv %r0(%r25) /* r4 */
2213 bv %r0(%r25) /* r5 */
2215 bv %r0(%r25) /* r6 */
2217 bv %r0(%r25) /* r7 */
2219 bv %r0(%r25) /* r8 */
2221 bv %r0(%r25) /* r9 */
2223 bv %r0(%r25) /* r10 */
2225 bv %r0(%r25) /* r11 */
2227 bv %r0(%r25) /* r12 */
2229 bv %r0(%r25) /* r13 */
2231 bv %r0(%r25) /* r14 */
2233 bv %r0(%r25) /* r15 */
2235 bv %r0(%r25) /* r16 */
2237 bv %r0(%r25) /* r17 */
2239 bv %r0(%r25) /* r18 */
2241 bv %r0(%r25) /* r19 */
2243 bv %r0(%r25) /* r20 */
2245 bv %r0(%r25) /* r21 */
2247 bv %r0(%r25) /* r22 */
2249 bv %r0(%r25) /* r23 */
2251 bv %r0(%r25) /* r24 */
2253 bv %r0(%r25) /* r25 */
2255 bv %r0(%r25) /* r26 */
2257 bv %r0(%r25) /* r27 */
2259 bv %r0(%r25) /* r28 */
2261 bv %r0(%r25) /* r29 */
2263 bv %r0(%r25) /* r30 */
2265 bv %r0(%r25) /* r31 */
2267 ENDPROC_CFI(set_register)