1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_PGTABLE_RADIX_H
3 #define _ASM_POWERPC_PGTABLE_RADIX_H
6 #include <asm/cmpxchg.h>
9 #ifdef CONFIG_PPC_64K_PAGES
10 #include <asm/book3s/64/radix-64k.h>
12 #include <asm/book3s/64/radix-4k.h>
16 #include <asm/book3s/64/tlbflush-radix.h>
17 #include <asm/cpu_has_feature.h>
20 /* An empty PTE can still have a R or C writeback */
21 #define RADIX_PTE_NONE_MASK (_PAGE_DIRTY | _PAGE_ACCESSED)
23 /* Bits to set in a RPMD/RPUD/RPGD */
24 #define RADIX_PMD_VAL_BITS (0x8000000000000000UL | RADIX_PTE_INDEX_SIZE)
25 #define RADIX_PUD_VAL_BITS (0x8000000000000000UL | RADIX_PMD_INDEX_SIZE)
26 #define RADIX_PGD_VAL_BITS (0x8000000000000000UL | RADIX_PUD_INDEX_SIZE)
28 /* Don't have anything in the reserved bits and leaf bits */
29 #define RADIX_PMD_BAD_BITS 0x60000000000000e0UL
30 #define RADIX_PUD_BAD_BITS 0x60000000000000e0UL
31 #define RADIX_PGD_BAD_BITS 0x60000000000000e0UL
34 * Size of EA range mapped by our pagetables.
36 #define RADIX_PGTABLE_EADDR_SIZE (RADIX_PTE_INDEX_SIZE + RADIX_PMD_INDEX_SIZE + \
37 RADIX_PUD_INDEX_SIZE + RADIX_PGD_INDEX_SIZE + PAGE_SHIFT)
38 #define RADIX_PGTABLE_RANGE (ASM_CONST(1) << RADIX_PGTABLE_EADDR_SIZE)
41 * We support 52 bit address space, Use top bit for kernel
42 * virtual mapping. Also make sure kernel fit in the top
45 * +------------------+
46 * +------------------+ Kernel virtual map (0xc008000000000000)
50 * 0b11......+------------------+ Kernel linear map (0xc....)
54 * 0b10......+------------------+
58 * 0b01......+------------------+
62 * 0b00......+------------------+
65 * 3rd quadrant expanded:
66 * +------------------------------+
70 * +------------------------------+ Kernel IO map end (0xc010000000000000)
73 * | 1/2 of virtual map |
76 * +------------------------------+ Kernel IO map start
78 * | 1/4 of virtual map |
80 * +------------------------------+ Kernel vmemap start
82 * | 1/4 of virtual map |
84 * +------------------------------+ Kernel virt start (0xc008000000000000)
88 * +------------------------------+ Kernel linear (0xc.....)
91 #define RADIX_KERN_VIRT_START ASM_CONST(0xc008000000000000)
92 #define RADIX_KERN_VIRT_SIZE ASM_CONST(0x0008000000000000)
95 * The vmalloc space starts at the beginning of that region, and
96 * occupies a quarter of it on radix config.
97 * (we keep a quarter for the virtual memmap)
99 #define RADIX_VMALLOC_START RADIX_KERN_VIRT_START
100 #define RADIX_VMALLOC_SIZE (RADIX_KERN_VIRT_SIZE >> 2)
101 #define RADIX_VMALLOC_END (RADIX_VMALLOC_START + RADIX_VMALLOC_SIZE)
103 * Defines the address of the vmemap area, in its own region on
106 #define RADIX_VMEMMAP_BASE (RADIX_VMALLOC_END)
108 #define RADIX_KERN_IO_START (RADIX_KERN_VIRT_START + (RADIX_KERN_VIRT_SIZE >> 1))
111 #define RADIX_PTE_TABLE_SIZE (sizeof(pte_t) << RADIX_PTE_INDEX_SIZE)
112 #define RADIX_PMD_TABLE_SIZE (sizeof(pmd_t) << RADIX_PMD_INDEX_SIZE)
113 #define RADIX_PUD_TABLE_SIZE (sizeof(pud_t) << RADIX_PUD_INDEX_SIZE)
114 #define RADIX_PGD_TABLE_SIZE (sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE)
116 #ifdef CONFIG_STRICT_KERNEL_RWX
117 extern void radix__mark_rodata_ro(void);
118 extern void radix__mark_initmem_nx(void);
121 extern void radix__ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep,
122 pte_t entry, unsigned long address,
125 static inline unsigned long __radix_pte_update(pte_t *ptep, unsigned long clr,
128 __be64 old_be, tmp_be;
130 __asm__ __volatile__(
131 "1: ldarx %0,0,%3 # pte_update\n"
136 : "=&r" (old_be), "=&r" (tmp_be), "=m" (*ptep)
137 : "r" (ptep), "r" (cpu_to_be64(set)), "r" (cpu_to_be64(clr))
140 return be64_to_cpu(old_be);
143 static inline unsigned long radix__pte_update(struct mm_struct *mm,
145 pte_t *ptep, unsigned long clr,
149 unsigned long old_pte;
151 old_pte = __radix_pte_update(ptep, clr, set);
153 assert_pte_locked(mm, addr);
158 static inline pte_t radix__ptep_get_and_clear_full(struct mm_struct *mm,
160 pte_t *ptep, int full)
162 unsigned long old_pte;
165 old_pte = pte_val(*ptep);
168 old_pte = radix__pte_update(mm, addr, ptep, ~0ul, 0, 0);
170 return __pte(old_pte);
173 static inline int radix__pte_same(pte_t pte_a, pte_t pte_b)
175 return ((pte_raw(pte_a) ^ pte_raw(pte_b)) == 0);
178 static inline int radix__pte_none(pte_t pte)
180 return (pte_val(pte) & ~RADIX_PTE_NONE_MASK) == 0;
183 static inline void radix__set_pte_at(struct mm_struct *mm, unsigned long addr,
184 pte_t *ptep, pte_t pte, int percpu)
189 * The architecture suggests a ptesync after setting the pte, which
190 * orders the store that updates the pte with subsequent page table
191 * walk accesses which may load the pte. Without this it may be
192 * possible for a subsequent access to result in spurious fault.
194 * This is not necessary for correctness, because a spurious fault
195 * is tolerated by the page fault handler, and this store will
196 * eventually be seen. In testing, there was no noticable increase
197 * in user faults on POWER9. Avoiding ptesync here is a significant
198 * win for things like fork. If a future microarchitecture benefits
199 * from ptesync, it should probably go into update_mmu_cache, rather
200 * than set_pte_at (which is used to set ptes unrelated to faults).
202 * Spurious faults to vmalloc region are not tolerated, so there is
203 * a ptesync in flush_cache_vmap.
207 static inline int radix__pmd_bad(pmd_t pmd)
209 return !!(pmd_val(pmd) & RADIX_PMD_BAD_BITS);
212 static inline int radix__pmd_same(pmd_t pmd_a, pmd_t pmd_b)
214 return ((pmd_raw(pmd_a) ^ pmd_raw(pmd_b)) == 0);
217 static inline int radix__pud_bad(pud_t pud)
219 return !!(pud_val(pud) & RADIX_PUD_BAD_BITS);
223 static inline int radix__pgd_bad(pgd_t pgd)
225 return !!(pgd_val(pgd) & RADIX_PGD_BAD_BITS);
228 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
230 static inline int radix__pmd_trans_huge(pmd_t pmd)
232 return (pmd_val(pmd) & (_PAGE_PTE | _PAGE_DEVMAP)) == _PAGE_PTE;
235 static inline pmd_t radix__pmd_mkhuge(pmd_t pmd)
237 return __pmd(pmd_val(pmd) | _PAGE_PTE);
240 extern unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
241 pmd_t *pmdp, unsigned long clr,
243 extern pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma,
244 unsigned long address, pmd_t *pmdp);
245 extern void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
247 extern pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
248 extern pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
249 unsigned long addr, pmd_t *pmdp);
250 extern int radix__has_transparent_hugepage(void);
253 extern int __meminit radix__vmemmap_create_mapping(unsigned long start,
254 unsigned long page_size,
256 extern void radix__vmemmap_remove_mapping(unsigned long start,
257 unsigned long page_size);
259 extern int radix__map_kernel_page(unsigned long ea, unsigned long pa,
260 pgprot_t flags, unsigned int psz);
262 static inline unsigned long radix__get_tree_size(void)
264 unsigned long rts_field;
266 * We support 52 bits, hence:
267 * bits 52 - 31 = 21, 0b10101
268 * RTS encoding details
269 * bits 0 - 3 of rts -> bits 6 - 8 unsigned long
270 * bits 4 - 5 of rts -> bits 62 - 63 of unsigned long
272 rts_field = (0x5UL << 5); /* 6 - 8 bits */
273 rts_field |= (0x2UL << 61);
278 #ifdef CONFIG_MEMORY_HOTPLUG
279 int radix__create_section_mapping(unsigned long start, unsigned long end, int nid);
280 int radix__remove_section_mapping(unsigned long start, unsigned long end);
281 #endif /* CONFIG_MEMORY_HOTPLUG */
282 #endif /* __ASSEMBLY__ */