1 #ifndef _ASM_POWERPC_PGTABLE_RADIX_H
2 #define _ASM_POWERPC_PGTABLE_RADIX_H
5 #include <asm/cmpxchg.h>
8 #ifdef CONFIG_PPC_64K_PAGES
9 #include <asm/book3s/64/radix-64k.h>
11 #include <asm/book3s/64/radix-4k.h>
14 /* An empty PTE can still have a R or C writeback */
15 #define RADIX_PTE_NONE_MASK (_PAGE_DIRTY | _PAGE_ACCESSED)
17 /* Bits to set in a RPMD/RPUD/RPGD */
18 #define RADIX_PMD_VAL_BITS (0x8000000000000000UL | RADIX_PTE_INDEX_SIZE)
19 #define RADIX_PUD_VAL_BITS (0x8000000000000000UL | RADIX_PMD_INDEX_SIZE)
20 #define RADIX_PGD_VAL_BITS (0x8000000000000000UL | RADIX_PUD_INDEX_SIZE)
22 /* Don't have anything in the reserved bits and leaf bits */
23 #define RADIX_PMD_BAD_BITS 0x60000000000000e0UL
24 #define RADIX_PUD_BAD_BITS 0x60000000000000e0UL
25 #define RADIX_PGD_BAD_BITS 0x60000000000000e0UL
28 * Size of EA range mapped by our pagetables.
30 #define RADIX_PGTABLE_EADDR_SIZE (RADIX_PTE_INDEX_SIZE + RADIX_PMD_INDEX_SIZE + \
31 RADIX_PUD_INDEX_SIZE + RADIX_PGD_INDEX_SIZE + PAGE_SHIFT)
32 #define RADIX_PGTABLE_RANGE (ASM_CONST(1) << RADIX_PGTABLE_EADDR_SIZE)
35 * We support 52 bit address space, Use top bit for kernel
36 * virtual mapping. Also make sure kernel fit in the top
39 * +------------------+
40 * +------------------+ Kernel virtual map (0xc008000000000000)
44 * 0b11......+------------------+ Kernel linear map (0xc....)
48 * 0b10......+------------------+
52 * 0b01......+------------------+
56 * 0b00......+------------------+
59 * 3rd quadrant expanded:
60 * +------------------------------+
64 * +------------------------------+ Kernel IO map end (0xc010000000000000)
67 * | 1/2 of virtual map |
70 * +------------------------------+ Kernel IO map start
72 * | 1/4 of virtual map |
74 * +------------------------------+ Kernel vmemap start
76 * | 1/4 of virtual map |
78 * +------------------------------+ Kernel virt start (0xc008000000000000)
82 * +------------------------------+ Kernel linear (0xc.....)
85 #define RADIX_KERN_VIRT_START ASM_CONST(0xc008000000000000)
86 #define RADIX_KERN_VIRT_SIZE ASM_CONST(0x0008000000000000)
89 * The vmalloc space starts at the beginning of that region, and
90 * occupies a quarter of it on radix config.
91 * (we keep a quarter for the virtual memmap)
93 #define RADIX_VMALLOC_START RADIX_KERN_VIRT_START
94 #define RADIX_VMALLOC_SIZE (RADIX_KERN_VIRT_SIZE >> 2)
95 #define RADIX_VMALLOC_END (RADIX_VMALLOC_START + RADIX_VMALLOC_SIZE)
97 * Defines the address of the vmemap area, in its own region on
100 #define RADIX_VMEMMAP_BASE (RADIX_VMALLOC_END)
103 #define RADIX_PTE_TABLE_SIZE (sizeof(pte_t) << RADIX_PTE_INDEX_SIZE)
104 #define RADIX_PMD_TABLE_SIZE (sizeof(pmd_t) << RADIX_PMD_INDEX_SIZE)
105 #define RADIX_PUD_TABLE_SIZE (sizeof(pud_t) << RADIX_PUD_INDEX_SIZE)
106 #define RADIX_PGD_TABLE_SIZE (sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE)
108 static inline unsigned long radix__pte_update(struct mm_struct *mm,
110 pte_t *ptep, unsigned long clr,
115 unsigned long old_pte, new_pte;
118 pte = READ_ONCE(*ptep);
119 old_pte = pte_val(pte);
120 new_pte = (old_pte | set) & ~clr;
122 } while (!pte_xchg(ptep, __pte(old_pte), __pte(new_pte)));
124 /* We already do a sync in cmpxchg, is ptesync needed ?*/
125 asm volatile("ptesync" : : : "memory");
126 /* huge pages use the old page table lock */
128 assert_pte_locked(mm, addr);
134 * Set the dirty and/or accessed bits atomically in a linux PTE, this
135 * function doesn't need to invalidate tlb.
137 static inline void radix__ptep_set_access_flags(pte_t *ptep, pte_t entry)
140 unsigned long old_pte, new_pte;
141 unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED |
142 _PAGE_RW | _PAGE_EXEC);
144 pte = READ_ONCE(*ptep);
145 old_pte = pte_val(pte);
146 new_pte = old_pte | set;
148 } while (!pte_xchg(ptep, __pte(old_pte), __pte(new_pte)));
150 /* We already do a sync in cmpxchg, is ptesync needed ?*/
151 asm volatile("ptesync" : : : "memory");
154 static inline int radix__pte_same(pte_t pte_a, pte_t pte_b)
156 return ((pte_raw(pte_a) ^ pte_raw(pte_b)) == 0);
159 static inline int radix__pte_none(pte_t pte)
161 return (pte_val(pte) & ~RADIX_PTE_NONE_MASK) == 0;
164 static inline void radix__set_pte_at(struct mm_struct *mm, unsigned long addr,
165 pte_t *ptep, pte_t pte, int percpu)
168 asm volatile("ptesync" : : : "memory");
171 static inline int radix__pmd_bad(pmd_t pmd)
173 return !!(pmd_val(pmd) & RADIX_PMD_BAD_BITS);
176 static inline int radix__pmd_same(pmd_t pmd_a, pmd_t pmd_b)
178 return ((pmd_raw(pmd_a) ^ pmd_raw(pmd_b)) == 0);
181 static inline int radix__pud_bad(pud_t pud)
183 return !!(pud_val(pud) & RADIX_PUD_BAD_BITS);
187 static inline int radix__pgd_bad(pgd_t pgd)
189 return !!(pgd_val(pgd) & RADIX_PGD_BAD_BITS);
192 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
194 static inline int radix__pmd_trans_huge(pmd_t pmd)
196 return !!(pmd_val(pmd) & _PAGE_PTE);
199 static inline pmd_t radix__pmd_mkhuge(pmd_t pmd)
201 return __pmd(pmd_val(pmd) | _PAGE_PTE);
203 static inline void radix__pmdp_huge_split_prepare(struct vm_area_struct *vma,
204 unsigned long address, pmd_t *pmdp)
206 /* Nothing to do for radix. */
210 extern unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
211 pmd_t *pmdp, unsigned long clr,
213 extern pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma,
214 unsigned long address, pmd_t *pmdp);
215 extern void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
217 extern pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
218 extern pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
219 unsigned long addr, pmd_t *pmdp);
220 extern int radix__has_transparent_hugepage(void);
223 extern int __meminit radix__vmemmap_create_mapping(unsigned long start,
224 unsigned long page_size,
226 extern void radix__vmemmap_remove_mapping(unsigned long start,
227 unsigned long page_size);
229 extern int radix__map_kernel_page(unsigned long ea, unsigned long pa,
230 pgprot_t flags, unsigned int psz);
232 static inline unsigned long radix__get_tree_size(void)
234 unsigned long rts_field;
236 * we support 52 bits, hence 52-31 = 21, 0b10101
237 * RTS encoding details
238 * bits 0 - 3 of rts -> bits 6 - 8 unsigned long
239 * bits 4 - 5 of rts -> bits 62 - 63 of unsigned long
241 rts_field = (0x5UL << 5); /* 6 - 8 bits */
242 rts_field |= (0x2UL << 61);
246 #endif /* __ASSEMBLY__ */