1 #ifndef _ASM_POWERPC_IO_H
2 #define _ASM_POWERPC_IO_H
5 #define ARCH_HAS_IOREMAP_WC
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
14 /* Check of existence of legacy devices */
15 extern int check_legacy_ioport(unsigned long base_port);
16 #define I8042_DATA_REG 0x60
17 #define FDC_BASE 0x3f0
19 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
20 extern struct pci_dev *isa_bridge_pcidev;
22 * has legacy ISA devices ?
24 #define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special)
27 #include <linux/device.h>
28 #include <linux/compiler.h>
30 #include <asm/byteorder.h>
31 #include <asm/synch.h>
32 #include <asm/delay.h>
34 #include <asm/ppc_asm.h>
40 #define SIO_CONFIG_RA 0x398
41 #define SIO_CONFIG_RD 0x399
45 /* 32 bits uses slightly different variables for the various IO
46 * bases. Most of this file only uses _IO_BASE though which we
47 * define properly based on the platform
51 #define _ISA_MEM_BASE 0
52 #define PCI_DRAM_OFFSET 0
53 #elif defined(CONFIG_PPC32)
54 #define _IO_BASE isa_io_base
55 #define _ISA_MEM_BASE isa_mem_base
56 #define PCI_DRAM_OFFSET pci_dram_offset
58 #define _IO_BASE pci_io_base
59 #define _ISA_MEM_BASE isa_mem_base
60 #define PCI_DRAM_OFFSET 0
63 extern unsigned long isa_io_base;
64 extern unsigned long pci_io_base;
65 extern unsigned long pci_dram_offset;
67 extern resource_size_t isa_mem_base;
69 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE
70 * is not set or addresses cannot be translated to MMIO. This is typically
71 * set when the platform supports "special" PIO accesses via a non memory
72 * mapped mechanism, and allows things like the early udbg UART code to
75 extern bool isa_io_special;
78 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
79 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
85 * Low level MMIO accessors
87 * This provides the non-bus specific accessors to MMIO. Those are PowerPC
88 * specific and thus shouldn't be used in generic code. The accessors
91 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
92 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
93 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
95 * Those operate directly on a kernel virtual address. Note that the prototype
96 * for the out_* accessors has the arguments in opposite order from the usual
97 * linux PCI accessors. Unlike those, they take the address first and the value
100 * Note: I might drop the _ns suffix on the stream operations soon as it is
101 * simply normal for stream operations to not swap in the first place.
106 #define IO_SET_SYNC_FLAG() do { local_paca->io_sync = 1; } while(0)
108 #define IO_SET_SYNC_FLAG()
111 /* gcc 4.0 and older doesn't have 'Z' constraint */
112 #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0)
113 #define DEF_MMIO_IN_X(name, size, insn) \
114 static inline u##size name(const volatile u##size __iomem *addr) \
117 __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \
118 : "=r" (ret) : "r" (addr), "m" (*addr) : "memory"); \
122 #define DEF_MMIO_OUT_X(name, size, insn) \
123 static inline void name(volatile u##size __iomem *addr, u##size val) \
125 __asm__ __volatile__("sync;"#insn" %1,0,%2" \
126 : "=m" (*addr) : "r" (val), "r" (addr) : "memory"); \
127 IO_SET_SYNC_FLAG(); \
129 #else /* newer gcc */
130 #define DEF_MMIO_IN_X(name, size, insn) \
131 static inline u##size name(const volatile u##size __iomem *addr) \
134 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
135 : "=r" (ret) : "Z" (*addr) : "memory"); \
139 #define DEF_MMIO_OUT_X(name, size, insn) \
140 static inline void name(volatile u##size __iomem *addr, u##size val) \
142 __asm__ __volatile__("sync;"#insn" %1,%y0" \
143 : "=Z" (*addr) : "r" (val) : "memory"); \
144 IO_SET_SYNC_FLAG(); \
148 #define DEF_MMIO_IN_D(name, size, insn) \
149 static inline u##size name(const volatile u##size __iomem *addr) \
152 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
153 : "=r" (ret) : "m" (*addr) : "memory"); \
157 #define DEF_MMIO_OUT_D(name, size, insn) \
158 static inline void name(volatile u##size __iomem *addr, u##size val) \
160 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \
161 : "=m" (*addr) : "r" (val) : "memory"); \
162 IO_SET_SYNC_FLAG(); \
165 DEF_MMIO_IN_D(in_8, 8, lbz);
166 DEF_MMIO_OUT_D(out_8, 8, stb);
168 #ifdef __BIG_ENDIAN__
169 DEF_MMIO_IN_D(in_be16, 16, lhz);
170 DEF_MMIO_IN_D(in_be32, 32, lwz);
171 DEF_MMIO_IN_X(in_le16, 16, lhbrx);
172 DEF_MMIO_IN_X(in_le32, 32, lwbrx);
174 DEF_MMIO_OUT_D(out_be16, 16, sth);
175 DEF_MMIO_OUT_D(out_be32, 32, stw);
176 DEF_MMIO_OUT_X(out_le16, 16, sthbrx);
177 DEF_MMIO_OUT_X(out_le32, 32, stwbrx);
179 DEF_MMIO_IN_X(in_be16, 16, lhbrx);
180 DEF_MMIO_IN_X(in_be32, 32, lwbrx);
181 DEF_MMIO_IN_D(in_le16, 16, lhz);
182 DEF_MMIO_IN_D(in_le32, 32, lwz);
184 DEF_MMIO_OUT_X(out_be16, 16, sthbrx);
185 DEF_MMIO_OUT_X(out_be32, 32, stwbrx);
186 DEF_MMIO_OUT_D(out_le16, 16, sth);
187 DEF_MMIO_OUT_D(out_le32, 32, stw);
189 #endif /* __BIG_ENDIAN */
193 #ifdef __BIG_ENDIAN__
194 DEF_MMIO_OUT_D(out_be64, 64, std);
195 DEF_MMIO_IN_D(in_be64, 64, ld);
197 /* There is no asm instructions for 64 bits reverse loads and stores */
198 static inline u64 in_le64(const volatile u64 __iomem *addr)
200 return swab64(in_be64(addr));
203 static inline void out_le64(volatile u64 __iomem *addr, u64 val)
205 out_be64(addr, swab64(val));
208 DEF_MMIO_OUT_D(out_le64, 64, std);
209 DEF_MMIO_IN_D(in_le64, 64, ld);
211 /* There is no asm instructions for 64 bits reverse loads and stores */
212 static inline u64 in_be64(const volatile u64 __iomem *addr)
214 return swab64(in_le64(addr));
217 static inline void out_be64(volatile u64 __iomem *addr, u64 val)
219 out_le64(addr, swab64(val));
223 #endif /* __powerpc64__ */
226 * Low level IO stream instructions are defined out of line for now
228 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
229 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
230 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
231 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
232 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
233 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
235 /* The _ns naming is historical and will be removed. For now, just #define
236 * the non _ns equivalent names
238 #define _insw _insw_ns
239 #define _insl _insl_ns
240 #define _outsw _outsw_ns
241 #define _outsl _outsl_ns
245 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
248 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
249 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
251 extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
256 * PCI and standard ISA accessors
258 * Those are globally defined linux accessors for devices on PCI or ISA
259 * busses. They follow the Linux defined semantics. The current implementation
260 * for PowerPC is as close as possible to the x86 version of these, and thus
261 * provides fairly heavy weight barriers for the non-raw versions
263 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
264 * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
265 * own implementation of some or all of the accessors.
269 * Include the EEH definitions when EEH is enabled only so they don't get
270 * in the way when building for 32 bits
276 /* Shortcut to the MMIO argument pointer */
277 #define PCI_IO_ADDR volatile void __iomem *
279 /* Indirect IO address tokens:
281 * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
282 * on all MMIOs. (Note that this is all 64 bits only for now)
284 * To help platforms who may need to differentiate MMIO addresses in
285 * their hooks, a bitfield is reserved for use by the platform near the
286 * top of MMIO addresses (not PIO, those have to cope the hard way).
288 * This bit field is 12 bits and is at the top of the IO virtual
289 * addresses PCI_IO_INDIRECT_TOKEN_MASK.
291 * The kernel virtual space is thus:
293 * 0xD000000000000000 : vmalloc
294 * 0xD000080000000000 : PCI PHB IO space
295 * 0xD000080080000000 : ioremap
296 * 0xD0000fffffffffff : end of ioremap region
298 * Since the top 4 bits are reserved as the region ID, we use thus
299 * the next 12 bits and keep 4 bits available for the future if the
300 * virtual address space is ever to be extended.
302 * The direct IO mapping operations will then mask off those bits
303 * before doing the actual access, though that only happen when
304 * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
307 * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
308 * all PIO functions call through a hook.
311 #ifdef CONFIG_PPC_INDIRECT_MMIO
312 #define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul
313 #define PCI_IO_IND_TOKEN_SHIFT 48
314 #define PCI_FIX_ADDR(addr) \
315 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
316 #define PCI_GET_ADDR_TOKEN(addr) \
317 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
318 PCI_IO_IND_TOKEN_SHIFT)
319 #define PCI_SET_ADDR_TOKEN(addr, token) \
321 unsigned long __a = (unsigned long)(addr); \
322 __a &= ~PCI_IO_IND_TOKEN_MASK; \
323 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
324 (addr) = (void __iomem *)__a; \
327 #define PCI_FIX_ADDR(addr) (addr)
332 * Non ordered and non-swapping "raw" accessors
335 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
337 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
339 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
341 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
343 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
345 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
347 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
349 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
351 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
353 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
355 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
357 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
361 static inline unsigned long __raw_readq(const volatile void __iomem *addr)
363 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
365 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
367 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
371 * Real mode versions of the above. Those instructions are only supposed
372 * to be used in hypervisor real mode as per the architecture spec.
374 static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr)
376 __asm__ __volatile__("stbcix %0,0,%1"
377 : : "r" (val), "r" (paddr) : "memory");
380 static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr)
382 __asm__ __volatile__("sthcix %0,0,%1"
383 : : "r" (val), "r" (paddr) : "memory");
386 static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr)
388 __asm__ __volatile__("stwcix %0,0,%1"
389 : : "r" (val), "r" (paddr) : "memory");
392 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
394 __asm__ __volatile__("stdcix %0,0,%1"
395 : : "r" (val), "r" (paddr) : "memory");
398 static inline u8 __raw_rm_readb(volatile void __iomem *paddr)
401 __asm__ __volatile__("lbzcix %0,0, %1"
402 : "=r" (ret) : "r" (paddr) : "memory");
406 static inline u16 __raw_rm_readw(volatile void __iomem *paddr)
409 __asm__ __volatile__("lhzcix %0,0, %1"
410 : "=r" (ret) : "r" (paddr) : "memory");
414 static inline u32 __raw_rm_readl(volatile void __iomem *paddr)
417 __asm__ __volatile__("lwzcix %0,0, %1"
418 : "=r" (ret) : "r" (paddr) : "memory");
422 static inline u64 __raw_rm_readq(volatile void __iomem *paddr)
425 __asm__ __volatile__("ldcix %0,0, %1"
426 : "=r" (ret) : "r" (paddr) : "memory");
429 #endif /* __powerpc64__ */
433 * PCI PIO and MMIO accessors.
436 * On 32 bits, PIO operations have a recovery mechanism in case they trigger
437 * machine checks (which they occasionally do when probing non existing
438 * IO ports on some platforms, like PowerMac and 8xx).
439 * I always found it to be of dubious reliability and I am tempted to get
440 * rid of it one of these days. So if you think it's important to keep it,
441 * please voice up asap. We never had it for 64 bits and I do not intend
447 #define __do_in_asm(name, op) \
448 static inline unsigned int name(unsigned int port) \
451 __asm__ __volatile__( \
453 "0:" op " %0,0,%1\n" \
458 ".section .fixup,\"ax\"\n" \
467 : "r" (port + _IO_BASE) \
472 #define __do_out_asm(name, op) \
473 static inline void name(unsigned int val, unsigned int port) \
475 __asm__ __volatile__( \
477 "0:" op " %0,0,%1\n" \
482 : : "r" (val), "r" (port + _IO_BASE) \
486 __do_in_asm(_rec_inb, "lbzx")
487 __do_in_asm(_rec_inw, "lhbrx")
488 __do_in_asm(_rec_inl, "lwbrx")
489 __do_out_asm(_rec_outb, "stbx")
490 __do_out_asm(_rec_outw, "sthbrx")
491 __do_out_asm(_rec_outl, "stwbrx")
493 #endif /* CONFIG_PPC32 */
495 /* The "__do_*" operations below provide the actual "base" implementation
496 * for each of the defined accessors. Some of them use the out_* functions
497 * directly, some of them still use EEH, though we might change that in the
498 * future. Those macros below provide the necessary argument swapping and
499 * handling of the IO base for PIO.
501 * They are themselves used by the macros that define the actual accessors
502 * and can be used by the hooks if any.
504 * Note that PIO operations are always defined in terms of their corresonding
505 * MMIO operations. That allows platforms like iSeries who want to modify the
506 * behaviour of both to only hook on the MMIO version and get both. It's also
507 * possible to hook directly at the toplevel PIO operation if they have to
508 * be handled differently
510 #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
511 #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
512 #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
513 #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
514 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
515 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
516 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
519 #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
520 #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
521 #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
522 #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
523 #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
524 #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
525 #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
526 #else /* CONFIG_EEH */
527 #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
528 #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
529 #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
530 #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
531 #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
532 #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
533 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
534 #endif /* !defined(CONFIG_EEH) */
537 #define __do_outb(val, port) _rec_outb(val, port)
538 #define __do_outw(val, port) _rec_outw(val, port)
539 #define __do_outl(val, port) _rec_outl(val, port)
540 #define __do_inb(port) _rec_inb(port)
541 #define __do_inw(port) _rec_inw(port)
542 #define __do_inl(port) _rec_inl(port)
543 #else /* CONFIG_PPC32 */
544 #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
545 #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
546 #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
547 #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
548 #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
549 #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
550 #endif /* !CONFIG_PPC32 */
553 #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
554 #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
555 #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
556 #else /* CONFIG_EEH */
557 #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
558 #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
559 #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
560 #endif /* !CONFIG_EEH */
561 #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
562 #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
563 #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
565 #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
566 #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
567 #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
568 #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
569 #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
570 #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
572 #define __do_memset_io(addr, c, n) \
573 _memset_io(PCI_FIX_ADDR(addr), c, n)
574 #define __do_memcpy_toio(dst, src, n) \
575 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
578 #define __do_memcpy_fromio(dst, src, n) \
579 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
580 #else /* CONFIG_EEH */
581 #define __do_memcpy_fromio(dst, src, n) \
582 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
583 #endif /* !CONFIG_EEH */
585 #ifdef CONFIG_PPC_INDIRECT_PIO
586 #define DEF_PCI_HOOK_pio(x) x
588 #define DEF_PCI_HOOK_pio(x) NULL
591 #ifdef CONFIG_PPC_INDIRECT_MMIO
592 #define DEF_PCI_HOOK_mem(x) x
594 #define DEF_PCI_HOOK_mem(x) NULL
597 /* Structure containing all the hooks */
598 extern struct ppc_pci_io {
600 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at;
601 #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at;
603 #include <asm/io-defs.h>
605 #undef DEF_PCI_AC_RET
606 #undef DEF_PCI_AC_NORET
610 /* The inline wrappers */
611 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
612 static inline ret name at \
614 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
615 return ppc_pci_io.name al; \
616 return __do_##name al; \
619 #define DEF_PCI_AC_NORET(name, at, al, space, aa) \
620 static inline void name at \
622 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
623 ppc_pci_io.name al; \
628 #include <asm/io-defs.h>
630 #undef DEF_PCI_AC_RET
631 #undef DEF_PCI_AC_NORET
633 /* Some drivers check for the presence of readq & writeq with
634 * a #ifdef, so we make them happy here.
638 #define writeq writeq
642 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
645 #define xlate_dev_mem_ptr(p) __va(p)
648 * Convert a virtual cached pointer to an uncached pointer
650 #define xlate_dev_kmem_ptr(p) p
653 * We don't do relaxed operations yet, at least not with this semantic
655 #define readb_relaxed(addr) readb(addr)
656 #define readw_relaxed(addr) readw(addr)
657 #define readl_relaxed(addr) readl(addr)
658 #define readq_relaxed(addr) readq(addr)
659 #define writeb_relaxed(v, addr) writeb(v, addr)
660 #define writew_relaxed(v, addr) writew(v, addr)
661 #define writel_relaxed(v, addr) writel(v, addr)
662 #define writeq_relaxed(v, addr) writeq(v, addr)
664 #include <asm-generic/iomap.h>
670 * Enforce synchronisation of stores vs. spin_unlock
671 * (this does it explicitly, though our implementation of spin_unlock
672 * does it implicitely too)
674 static inline void mmiowb(void)
678 __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)"
679 : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync))
682 #endif /* !CONFIG_PPC32 */
684 static inline void iosync(void)
686 __asm__ __volatile__ ("sync" : : : "memory");
689 /* Enforce in-order execution of data I/O.
690 * No distinction between read/write on PPC; use eieio for all three.
691 * Those are fairly week though. They don't provide a barrier between
692 * MMIO and cacheable storage nor do they provide a barrier vs. locks,
693 * they only provide barriers between 2 __raw MMIO operations and
694 * possibly break write combining.
696 #define iobarrier_rw() eieio()
697 #define iobarrier_r() eieio()
698 #define iobarrier_w() eieio()
702 * output pause versions need a delay at least for the
703 * w83c105 ide controller in a p610.
705 #define inb_p(port) inb(port)
706 #define outb_p(val, port) (udelay(1), outb((val), (port)))
707 #define inw_p(port) inw(port)
708 #define outw_p(val, port) (udelay(1), outw((val), (port)))
709 #define inl_p(port) inl(port)
710 #define outl_p(val, port) (udelay(1), outl((val), (port)))
713 #define IO_SPACE_LIMIT ~(0UL)
717 * ioremap - map bus memory into CPU space
718 * @address: bus address of the memory
719 * @size: size of the resource to map
721 * ioremap performs a platform specific sequence of operations to
722 * make bus memory CPU accessible via the readb/readw/readl/writeb/
723 * writew/writel functions and the other mmio helpers. The returned
724 * address is not guaranteed to be usable directly as a virtual
727 * We provide a few variations of it:
729 * * ioremap is the standard one and provides non-cacheable guarded mappings
730 * and can be hooked by the platform via ppc_md
732 * * ioremap_prot allows to specify the page flags as an argument and can
733 * also be hooked by the platform via ppc_md.
735 * * ioremap_nocache is identical to ioremap
737 * * ioremap_wc enables write combining
739 * * iounmap undoes such a mapping and can be hooked
741 * * __ioremap_at (and the pending __iounmap_at) are low level functions to
742 * create hand-made mappings for use only by the PCI code and cannot
743 * currently be hooked. Must be page aligned.
745 * * __ioremap is the low level implementation used by ioremap and
746 * ioremap_prot and cannot be hooked (but can be used by a hook on one
747 * of the previous ones)
749 * * __ioremap_caller is the same as above but takes an explicit caller
750 * reference rather than using __builtin_return_address(0)
752 * * __iounmap, is the low level implementation used by iounmap and cannot
753 * be hooked (but can be used by a hook on iounmap)
756 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
757 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
758 unsigned long flags);
759 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
760 #define ioremap_nocache(addr, size) ioremap((addr), (size))
761 #define ioremap_uc(addr, size) ioremap((addr), (size))
762 #define ioremap_cache(addr, size) \
763 ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL))
765 extern void iounmap(volatile void __iomem *addr);
767 extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
768 unsigned long flags);
769 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
770 unsigned long flags, void *caller);
772 extern void __iounmap(volatile void __iomem *addr);
774 extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
775 unsigned long size, unsigned long flags);
776 extern void __iounmap_at(void *ea, unsigned long size);
779 * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
780 * which needs some additional definitions here. They basically allow PIO
781 * space overall to be 1GB. This will work as long as we never try to use
782 * iomap to map MMIO below 1GB which should be fine on ppc64
784 #define HAVE_ARCH_PIO_SIZE 1
785 #define PIO_OFFSET 0x00000000UL
786 #define PIO_MASK (FULL_IO_SIZE - 1)
787 #define PIO_RESERVED (FULL_IO_SIZE)
789 #define mmio_read16be(addr) readw_be(addr)
790 #define mmio_read32be(addr) readl_be(addr)
791 #define mmio_write16be(val, addr) writew_be(val, addr)
792 #define mmio_write32be(val, addr) writel_be(val, addr)
793 #define mmio_insb(addr, dst, count) readsb(addr, dst, count)
794 #define mmio_insw(addr, dst, count) readsw(addr, dst, count)
795 #define mmio_insl(addr, dst, count) readsl(addr, dst, count)
796 #define mmio_outsb(addr, src, count) writesb(addr, src, count)
797 #define mmio_outsw(addr, src, count) writesw(addr, src, count)
798 #define mmio_outsl(addr, src, count) writesl(addr, src, count)
801 * virt_to_phys - map virtual addresses to physical
802 * @address: address to remap
804 * The returned physical address is the physical (CPU) mapping for
805 * the memory address given. It is only valid to use this function on
806 * addresses directly mapped or allocated via kmalloc.
808 * This function does not give bus mappings for DMA transfers. In
809 * almost all conceivable cases a device driver should not be using
812 static inline unsigned long virt_to_phys(volatile void * address)
814 return __pa((unsigned long)address);
818 * phys_to_virt - map physical address to virtual
819 * @address: address to remap
821 * The returned virtual address is a current CPU mapping for
822 * the memory address given. It is only valid to use this function on
823 * addresses that have a kernel mapping
825 * This function does not handle bus mappings for DMA transfers. In
826 * almost all conceivable cases a device driver should not be using
829 static inline void * phys_to_virt(unsigned long address)
831 return (void *)__va(address);
835 * Change "struct page" to physical address.
837 #define page_to_phys(page) ((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT)
840 * 32 bits still uses virt_to_bus() for it's implementation of DMA
841 * mappings se we have to keep it defined here. We also have some old
842 * drivers (shame shame shame) that use bus_to_virt() and haven't been
843 * fixed yet so I need to define it here.
847 static inline unsigned long virt_to_bus(volatile void * address)
851 return __pa(address) + PCI_DRAM_OFFSET;
854 static inline void * bus_to_virt(unsigned long address)
858 return __va(address - PCI_DRAM_OFFSET);
861 #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
863 #endif /* CONFIG_PPC32 */
866 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
867 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
869 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
870 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
872 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v))
873 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
875 /* Clear and set bits in one shot. These macros can be used to clear and
876 * set multiple bits in a register using a single read-modify-write. These
877 * macros can also be used to set a multiple-bit bit pattern using a mask,
878 * by specifying the mask in the 'clear' parameter and the new bit pattern
879 * in the 'set' parameter.
882 #define clrsetbits(type, addr, clear, set) \
883 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
886 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
887 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
890 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
891 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
893 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
894 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
896 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
898 #endif /* __KERNEL__ */
900 #endif /* _ASM_POWERPC_IO_H */