1 #ifndef _ASM_POWERPC_MMU_H_
2 #define _ASM_POWERPC_MMU_H_
5 #include <linux/types.h>
7 #include <asm/asm-compat.h>
8 #include <asm/feature-fixups.h>
11 * MMU features bit definitions
17 #define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001)
18 #define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002)
19 #define MMU_FTR_TYPE_40x ASM_CONST(0x00000004)
20 #define MMU_FTR_TYPE_44x ASM_CONST(0x00000008)
21 #define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
22 #define MMU_FTR_TYPE_47x ASM_CONST(0x00000020)
24 /* Radix page table supported and enabled */
25 #define MMU_FTR_TYPE_RADIX ASM_CONST(0x00000040)
28 * Individual features below.
32 * Kernel read only support.
33 * We added the ppp value 0b110 in ISA 2.04.
35 #define MMU_FTR_KERNEL_RO ASM_CONST(0x00004000)
38 * We need to clear top 16bits of va (from the remaining 64 bits )in
41 #define MMU_FTR_TLBIE_CROP_VA ASM_CONST(0x00008000)
43 /* Enable use of high BAT registers */
44 #define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000)
46 /* Enable >32-bit physical addresses on 32-bit processor, only used
47 * by CONFIG_6xx currently as BookE supports that from day 1
49 #define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000)
51 /* Enable use of broadcast TLB invalidations. We don't always set it
52 * on processors that support it due to other constraints with the
53 * use of such invalidations
55 #define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000)
57 /* Enable use of tlbilx invalidate instructions.
59 #define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000)
61 /* This indicates that the processor cannot handle multiple outstanding
62 * broadcast tlbivax or tlbsync. This makes the code use a spinlock
63 * around such invalidate forms.
65 #define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000)
67 /* This indicates that the processor doesn't handle way selection
68 * properly and needs SW to track and update the LRU state. This
69 * is specific to an errata on e300c2/c3/c4 class parts
71 #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
73 /* Enable use of TLB reservation. Processor should support tlbsrx.
74 * instruction and MAS0[WQ].
76 #define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000)
78 /* Use paired MAS registers (MAS7||MAS3, etc.)
80 #define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
82 /* Doesn't support the B bit (1T segment) in SLBIE
84 #define MMU_FTR_NO_SLBIE_B ASM_CONST(0x02000000)
86 /* Support 16M large pages
88 #define MMU_FTR_16M_PAGE ASM_CONST(0x04000000)
90 /* Supports TLBIEL variant
92 #define MMU_FTR_TLBIEL ASM_CONST(0x08000000)
94 /* Supports tlbies w/o locking
96 #define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000)
98 /* Large pages can be marked CI
100 #define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000)
102 /* 1T segments available
104 #define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
106 /* MMU feature bit sets for various CPUs */
107 #define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
108 MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
109 #define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2
110 #define MMU_FTRS_PPC970 MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA
111 #define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
112 #define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_KERNEL_RO
113 #define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_KERNEL_RO
114 #define MMU_FTRS_POWER8 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_KERNEL_RO
115 #define MMU_FTRS_POWER9 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_KERNEL_RO
116 #define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
117 MMU_FTR_CI_LARGE_PAGE
118 #define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
119 MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
121 #include <linux/bug.h>
122 #include <asm/cputable.h>
124 #ifdef CONFIG_PPC_FSL_BOOK3E
125 #include <asm/percpu.h>
126 DECLARE_PER_CPU(int, next_tlbcam_idx);
130 MMU_FTRS_POSSIBLE = MMU_FTR_HPTE_TABLE | MMU_FTR_TYPE_8xx |
131 MMU_FTR_TYPE_40x | MMU_FTR_TYPE_44x | MMU_FTR_TYPE_FSL_E |
132 MMU_FTR_TYPE_47x | MMU_FTR_USE_HIGH_BATS | MMU_FTR_BIG_PHYS |
133 MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_USE_TLBILX |
134 MMU_FTR_LOCK_BCAST_INVAL | MMU_FTR_NEED_DTLB_SW_LRU |
135 MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS |
136 MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL |
137 MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |
138 MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA |
139 #ifdef CONFIG_PPC_RADIX_MMU
145 static inline bool early_mmu_has_feature(unsigned long feature)
147 return !!(MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature);
150 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
151 #include <linux/jump_label.h>
153 #define NUM_MMU_FTR_KEYS 32
155 extern struct static_key_true mmu_feature_keys[NUM_MMU_FTR_KEYS];
157 extern void mmu_feature_keys_init(void);
159 static __always_inline bool mmu_has_feature(unsigned long feature)
163 #ifndef __clang__ /* clang can't cope with this */
164 BUILD_BUG_ON(!__builtin_constant_p(feature));
167 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG
168 if (!static_key_initialized) {
169 printk("Warning! mmu_has_feature() used prior to jump label init!\n");
171 return early_mmu_has_feature(feature);
175 if (!(MMU_FTRS_POSSIBLE & feature))
178 i = __builtin_ctzl(feature);
179 return static_branch_likely(&mmu_feature_keys[i]);
182 static inline void mmu_clear_feature(unsigned long feature)
186 i = __builtin_ctzl(feature);
187 cur_cpu_spec->mmu_features &= ~feature;
188 static_branch_disable(&mmu_feature_keys[i]);
192 static inline void mmu_feature_keys_init(void)
197 static inline bool mmu_has_feature(unsigned long feature)
199 return early_mmu_has_feature(feature);
202 static inline void mmu_clear_feature(unsigned long feature)
204 cur_cpu_spec->mmu_features &= ~feature;
206 #endif /* CONFIG_JUMP_LABEL */
208 extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
211 /* This is our real memory area size on ppc64 server, on embedded, we
212 * make it match the size our of bolted TLB area
214 extern u64 ppc64_rma_size;
216 /* Cleanup function used by kexec */
217 extern void mmu_cleanup_all(void);
218 extern void radix__mmu_cleanup_all(void);
220 /* Functions for creating and updating partition table on POWER9 */
221 extern void mmu_partition_table_init(void);
222 extern void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
224 #endif /* CONFIG_PPC64 */
227 #ifdef CONFIG_DEBUG_VM
228 extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
229 #else /* CONFIG_DEBUG_VM */
230 static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
233 #endif /* !CONFIG_DEBUG_VM */
235 #ifdef CONFIG_PPC_RADIX_MMU
236 static inline bool radix_enabled(void)
238 return mmu_has_feature(MMU_FTR_TYPE_RADIX);
241 static inline bool early_radix_enabled(void)
243 return early_mmu_has_feature(MMU_FTR_TYPE_RADIX);
246 static inline bool radix_enabled(void)
251 static inline bool early_radix_enabled(void)
257 #endif /* !__ASSEMBLY__ */
259 /* The kernel use the constants below to index in the page sizes array.
260 * The use of fixed constants for this purpose is better for performances
261 * of the low level hash refill handlers.
263 * A non supported page size has a "shift" field set to 0
265 * Any new page size being implemented can get a new entry in here. Whether
266 * the kernel will use it or not is a different matter though. The actual page
267 * size used by hugetlbfs is not defined here and may be made variable
269 * Note: This array ended up being a false good idea as it's growing to the
270 * point where I wonder if we should replace it with something different,
271 * to think about, feedback welcome. --BenH.
274 /* These are #defines as they have to be used in assembly */
275 #define MMU_PAGE_4K 0
276 #define MMU_PAGE_16K 1
277 #define MMU_PAGE_64K 2
278 #define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */
279 #define MMU_PAGE_256K 4
280 #define MMU_PAGE_512K 5
281 #define MMU_PAGE_1M 6
282 #define MMU_PAGE_2M 7
283 #define MMU_PAGE_4M 8
284 #define MMU_PAGE_8M 9
285 #define MMU_PAGE_16M 10
286 #define MMU_PAGE_64M 11
287 #define MMU_PAGE_256M 12
288 #define MMU_PAGE_1G 13
289 #define MMU_PAGE_16G 14
290 #define MMU_PAGE_64G 15
292 /* N.B. we need to change the type of hpte_page_sizes if this gets to be > 16 */
293 #define MMU_PAGE_COUNT 16
295 #ifdef CONFIG_PPC_BOOK3S_64
296 #include <asm/book3s/64/mmu.h>
297 #else /* CONFIG_PPC_BOOK3S_64 */
300 /* MMU initialization */
301 extern void early_init_mmu(void);
302 extern void early_init_mmu_secondary(void);
303 extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
304 phys_addr_t first_memblock_size);
305 static inline void mmu_early_init_devtree(void) { }
306 #endif /* __ASSEMBLY__ */
309 #if defined(CONFIG_PPC_STD_MMU_32)
310 /* 32-bit classic hash table MMU */
311 #include <asm/book3s/32/mmu-hash.h>
312 #elif defined(CONFIG_40x)
313 /* 40x-style software loaded TLB */
314 # include <asm/mmu-40x.h>
315 #elif defined(CONFIG_44x)
316 /* 44x-style software loaded TLB */
317 # include <asm/mmu-44x.h>
318 #elif defined(CONFIG_PPC_BOOK3E_MMU)
319 /* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
320 # include <asm/mmu-book3e.h>
321 #elif defined (CONFIG_PPC_8xx)
322 /* Motorola/Freescale 8xx software loaded TLB */
323 # include <asm/mmu-8xx.h>
326 #endif /* __KERNEL__ */
327 #endif /* _ASM_POWERPC_MMU_H_ */