1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
2 #define _ASM_POWERPC_PCI_BRIDGE_H
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 #include <linux/pci.h>
11 #include <linux/list.h>
12 #include <linux/ioport.h>
17 * PCI controller operations
19 struct pci_controller_ops {
20 void (*dma_dev_setup)(struct pci_dev *pdev);
21 void (*dma_bus_setup)(struct pci_bus *bus);
22 bool (*iommu_bypass_supported)(struct pci_dev *pdev,
25 int (*probe_mode)(struct pci_bus *bus);
27 /* Called when pci_enable_device() is called. Returns true to
28 * allow assignment/enabling of the device. */
29 bool (*enable_device_hook)(struct pci_dev *pdev);
31 void (*disable_device)(struct pci_dev *pdev);
33 void (*release_device)(struct pci_dev *pdev);
35 /* Called during PCI resource reassignment */
36 resource_size_t (*window_alignment)(struct pci_bus *bus,
38 void (*setup_bridge)(struct pci_bus *bus,
40 void (*reset_secondary_bus)(struct pci_dev *pdev);
43 int (*setup_msi_irqs)(struct pci_dev *pdev,
45 void (*teardown_msi_irqs)(struct pci_dev *pdev);
48 int (*dma_set_mask)(struct pci_dev *pdev, u64 dma_mask);
49 u64 (*dma_get_required_mask)(struct pci_dev *pdev);
51 void (*shutdown)(struct pci_controller *hose);
55 * Structure of a PCI controller (host bridge)
57 struct pci_controller {
63 struct device_node *dn;
64 struct list_head list_node;
65 struct device *parent;
72 void __iomem *io_base_virt;
76 resource_size_t io_base_phys;
77 resource_size_t pci_io_size;
79 /* Some machines have a special region to forward the ISA
80 * "memory" cycles such as VGA memory regions. Left to 0
83 resource_size_t isa_mem_phys;
84 resource_size_t isa_mem_size;
86 struct pci_controller_ops controller_ops;
88 unsigned int __iomem *cfg_addr;
89 void __iomem *cfg_data;
92 * Used for variants of PCI indirect handling and possible quirks:
93 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
94 * EXT_REG - provides access to PCI-e extended registers
95 * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
96 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
97 * to determine which bus number to match on when generating type0
99 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
100 * hanging if we don't have link and try to do config cycles to
101 * anything but the PHB. Only allow talking to the PHB if this is
103 * BIG_ENDIAN - cfg_addr is a big endian register
104 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
105 * the PLB4. Effectively disable MRM commands by setting this.
106 * FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
107 * link status is in a RC PCIe cfg register (vs being a SoC register)
109 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
110 #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
111 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
112 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
113 #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
114 #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
115 #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
117 /* Currently, we limit ourselves to 1 IO range and 3 mem
118 * ranges since the common pci_bus structure can't handle more
120 struct resource io_resource;
121 struct resource mem_resources[3];
122 resource_size_t mem_offset[3];
123 int global_number; /* PCI domain number */
125 resource_size_t dma_window_base_cur;
126 resource_size_t dma_window_size;
130 struct pci_dn *pci_data;
131 #endif /* CONFIG_PPC64 */
137 /* These are used for config access before all the PCI probing
139 extern int early_read_config_byte(struct pci_controller *hose, int bus,
140 int dev_fn, int where, u8 *val);
141 extern int early_read_config_word(struct pci_controller *hose, int bus,
142 int dev_fn, int where, u16 *val);
143 extern int early_read_config_dword(struct pci_controller *hose, int bus,
144 int dev_fn, int where, u32 *val);
145 extern int early_write_config_byte(struct pci_controller *hose, int bus,
146 int dev_fn, int where, u8 val);
147 extern int early_write_config_word(struct pci_controller *hose, int bus,
148 int dev_fn, int where, u16 val);
149 extern int early_write_config_dword(struct pci_controller *hose, int bus,
150 int dev_fn, int where, u32 val);
152 extern int early_find_capability(struct pci_controller *hose, int bus,
153 int dev_fn, int cap);
155 extern void setup_indirect_pci(struct pci_controller* hose,
156 resource_size_t cfg_addr,
157 resource_size_t cfg_data, u32 flags);
159 extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
160 int offset, int len, u32 *val);
162 extern int __indirect_read_config(struct pci_controller *hose,
163 unsigned char bus_number, unsigned int devfn,
164 int offset, int len, u32 *val);
166 extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
167 int offset, int len, u32 val);
169 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
176 extern int pci_device_from_OF_node(struct device_node *node,
178 extern void pci_create_OF_bus_map(void);
180 #else /* CONFIG_PPC64 */
183 * PCI stuff, for nodes representing PCI devices, pointed to
184 * by device_node->data.
190 #define PCI_DN_FLAG_IOV_VF 0x01
192 int busno; /* pci bus number */
193 int devfn; /* pci device and function number */
194 int vendor_id; /* Vendor ID */
195 int device_id; /* Device ID */
196 int class_code; /* Device class code */
198 struct pci_dn *parent;
199 struct pci_controller *phb; /* for pci devices */
200 struct iommu_table_group *table_group; /* for phb's or bridges */
202 int pci_ext_config_space; /* for pci devices */
204 struct eeh_dev *edev; /* eeh device */
206 #define IODA_INVALID_PE 0xFFFFFFFF
207 unsigned int pe_number;
208 #ifdef CONFIG_PCI_IOV
209 int vf_index; /* VF index in the PF */
210 u16 vfs_expanded; /* number of VFs IOV BAR expanded */
211 u16 num_vfs; /* number of VFs enabled*/
212 unsigned int *pe_num_map; /* PE# for the first VF PE or array */
213 bool m64_single_mode; /* Use M64 BAR in Single Mode */
214 #define IODA_INVALID_M64 (-1)
215 int (*m64_map)[PCI_SRIOV_NUM_BARS]; /* Only used on powernv */
216 int last_allow_rc; /* Only used on pseries */
217 #endif /* CONFIG_PCI_IOV */
218 int mps; /* Maximum Payload Size */
219 struct list_head child_list;
220 struct list_head list;
221 struct resource holes[PCI_SRIOV_NUM_BARS];
224 /* Get the pointer to a device_node's pci_dn */
225 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
227 extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
229 extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
230 extern struct pci_dn *add_dev_pci_data(struct pci_dev *pdev);
231 extern void remove_dev_pci_data(struct pci_dev *pdev);
232 extern struct pci_dn *pci_add_device_node_info(struct pci_controller *hose,
233 struct device_node *dn);
234 extern void pci_remove_device_node_info(struct device_node *dn);
236 static inline int pci_device_from_OF_node(struct device_node *np,
241 *bus = PCI_DN(np)->busno;
242 *devfn = PCI_DN(np)->devfn;
246 #if defined(CONFIG_EEH)
247 static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
249 return pdn ? pdn->edev : NULL;
252 #define pdn_to_eeh_dev(x) (NULL)
255 /** Find the bus corresponding to the indicated device node */
256 extern struct pci_bus *pci_find_bus_by_node(struct device_node *dn);
258 /** Remove all of the PCI devices under this bus */
259 extern void pci_hp_remove_devices(struct pci_bus *bus);
261 /** Discover new pci devices under this bus, and add them */
262 extern void pci_hp_add_devices(struct pci_bus *bus);
264 extern int pcibios_unmap_io_space(struct pci_bus *bus);
265 extern int pcibios_map_io_space(struct pci_bus *bus);
268 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
270 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
273 #endif /* CONFIG_PPC64 */
275 /* Get the PCI host controller for an OF device */
276 extern struct pci_controller *pci_find_hose_for_OF_device(
277 struct device_node* node);
279 /* Fill up host controller resources from the OF node */
280 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
281 struct device_node *dev, int primary);
283 /* Allocate & free a PCI host bridge structure */
284 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
285 extern void pcibios_free_controller(struct pci_controller *phb);
286 extern void pcibios_free_controller_deferred(struct pci_host_bridge *bridge);
289 extern int pcibios_vaddr_is_ioport(void __iomem *address);
291 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
295 #endif /* CONFIG_PCI */
297 #endif /* __KERNEL__ */
298 #endif /* _ASM_POWERPC_PCI_BRIDGE_H */