2 * This file contains the 64-bit "server" PowerPC variant
3 * of the low level exception handling including exception
4 * vectors, exception return, part of the slb and stab
5 * handling and other fixed offset specific things.
7 * This file is meant to be #included from head_64.S due to
8 * position dependent assembly.
10 * Most of this originates from head_64.S and thus has the same
15 #include <asm/hw_irq.h>
16 #include <asm/exception-64s.h>
17 #include <asm/ptrace.h>
18 #include <asm/cpuidle.h>
19 #include <asm/head-64.h>
22 * There are a few constraints to be concerned with.
23 * - Real mode exceptions code/data must be located at their physical location.
24 * - Virtual mode exceptions must be mapped at their 0xc000... location.
25 * - Fixed location code must not call directly beyond the __end_interrupts
26 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
28 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
30 * - Conditional branch targets must be within +/-32K of caller.
32 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
33 * therefore don't have to run in physically located code or rfid to
34 * virtual mode kernel code. However on relocatable kernels they do have
35 * to branch to KERNELBASE offset because the rest of the kernel (outside
36 * the exception vectors) may be located elsewhere.
38 * Virtual exceptions correspond with physical, except their entry points
39 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
40 * offset applied. Virtual exceptions are enabled with the Alternate
41 * Interrupt Location (AIL) bit set in the LPCR. However this does not
42 * guarantee they will be delivered virtually. Some conditions (see the ISA)
43 * cause exceptions to be delivered in real mode.
45 * It's impossible to receive interrupts below 0x300 via AIL.
47 * KVM: None of the virtual exceptions are from the guest. Anything that
48 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
51 * We layout physical memory as follows:
52 * 0x0000 - 0x00ff : Secondary processor spin code
53 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
54 * 0x1900 - 0x3fff : Real mode trampolines
55 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
56 * 0x5900 - 0x6fff : Relon mode trampolines
57 * 0x7000 - 0x7fff : FWNMI data area
58 * 0x8000 - .... : Common interrupt handlers, remaining early
59 * setup code, rest of kernel.
61 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
62 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
65 OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
66 OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000)
67 OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900)
68 OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
69 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
71 * Data area reserved for FWNMI option.
72 * This address (0x7000) is fixed by the RPA.
73 * pseries and powernv need to keep the whole page from
74 * 0x7000 to 0x8000 free for use by the firmware
76 ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
77 OPEN_TEXT_SECTION(0x8000)
79 OPEN_TEXT_SECTION(0x7000)
82 USE_FIXED_SECTION(real_vectors)
85 * This is the start of the interrupt handlers for pSeries
86 * This code runs with relocation off.
87 * Code from here to __end_interrupts gets copied down to real
88 * address 0x100 when we are running a relocatable kernel.
89 * Therefore any relative branches in this section must only
90 * branch to labels in this section.
92 .globl __start_interrupts
95 /* No virt vectors corresponding with 0x0..0x100 */
96 EXC_VIRT_NONE(0x4000, 0x100)
99 #ifdef CONFIG_PPC_P7_NAP
101 * If running native on arch 2.06 or later, check if we are waking up
102 * from nap/sleep/winkle, and branch to idle handler. This tests SRR1
103 * bits 46:47. A non-0 value indicates that we are coming from a power
104 * saving state. The idle wakeup handler initially runs in real mode,
105 * but we branch to the 0xc000... address so we can turn on relocation
108 #define IDLETEST(n) \
109 BEGIN_FTR_SECTION ; \
110 mfspr r10,SPRN_SRR1 ; \
111 rlwinm. r10,r10,47-31,30,31 ; \
114 BRANCH_TO_C000(r10, system_reset_idle_common) ; \
116 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
118 #define IDLETEST NOTEST
121 EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
124 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is
125 * being used, so a nested NMI exception would corrupt it.
127 EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common, EXC_STD,
130 EXC_REAL_END(system_reset, 0x100, 0x100)
131 EXC_VIRT_NONE(0x4100, 0x100)
133 #ifdef CONFIG_PPC_P7_NAP
134 EXC_COMMON_BEGIN(system_reset_idle_common)
136 b pnv_powersave_wakeup
139 EXC_COMMON_BEGIN(system_reset_common)
141 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able
142 * to recover, but nested NMI will notice in_nmi and not recover
143 * because of the use of the NMI stack. in_nmi reentrancy is tested in
144 * system_reset_exception.
146 lhz r10,PACA_IN_NMI(r13)
148 sth r10,PACA_IN_NMI(r13)
153 ld r1,PACA_NMI_EMERG_SP(r13)
154 subi r1,r1,INT_FRAME_SIZE
155 EXCEPTION_COMMON_NORET_STACK(PACA_EXNMI, 0x100,
156 system_reset, system_reset_exception,
157 ADD_NVGPRS;ADD_RECONCILE)
160 * The stack is no longer in use, decrement in_nmi.
162 lhz r10,PACA_IN_NMI(r13)
164 sth r10,PACA_IN_NMI(r13)
168 #ifdef CONFIG_PPC_PSERIES
170 * Vectors for the FWNMI option. Share common code.
172 TRAMP_REAL_BEGIN(system_reset_fwnmi)
173 SET_SCRATCH0(r13) /* save r13 */
174 /* See comment at system_reset exception */
175 EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common,
176 EXC_STD, NOTEST, 0x100)
177 #endif /* CONFIG_PPC_PSERIES */
180 EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
181 /* This is moved out of line as it can be patched by FW, but
182 * some code path might still want to branch into the original
185 SET_SCRATCH0(r13) /* save r13 */
186 EXCEPTION_PROLOG_0(PACA_EXMC)
188 b machine_check_powernv_early
190 b machine_check_pSeries_0
191 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
192 EXC_REAL_END(machine_check, 0x200, 0x100)
193 EXC_VIRT_NONE(0x4200, 0x100)
194 TRAMP_REAL_BEGIN(machine_check_powernv_early)
196 EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200)
201 * Original R9 to R13 is saved on PACA_EXMC
203 * Switch to mc_emergency stack and handle re-entrancy (we limit
204 * the nested MCE upto level 4 to avoid stack overflow).
205 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
207 * We use paca->in_mce to check whether this is the first entry or
208 * nested machine check. We increment paca->in_mce to track nested
211 * If this is the first entry then set stack pointer to
212 * paca->mc_emergency_sp, otherwise r1 is already pointing to
213 * stack frame on mc_emergency stack.
215 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
216 * checkstop if we get another machine check exception before we do
217 * rfid with MSR_ME=1.
219 * This interrupt can wake directly from idle. If that is the case,
220 * the machine check is handled then the idle wakeup code is called
221 * to restore state. In that case, the POWER9 DD1 idle PACA workaround
222 * is not applied in the early machine check code, which will cause
225 mr r11,r1 /* Save r1 */
226 lhz r10,PACA_IN_MCE(r13)
227 cmpwi r10,0 /* Are we in nested machine check */
228 bne 0f /* Yes, we are. */
229 /* First machine check entry */
230 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
231 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
232 addi r10,r10,1 /* increment paca->in_mce */
233 sth r10,PACA_IN_MCE(r13)
234 /* Limit nested MCE to level 4 to avoid stack overflow */
236 bgt 2f /* Check if we hit limit of 4 */
237 std r11,GPR1(r1) /* Save r1 on the stack. */
238 std r11,0(r1) /* make stack chain pointer */
239 mfspr r11,SPRN_SRR0 /* Save SRR0 */
241 mfspr r11,SPRN_SRR1 /* Save SRR1 */
243 mfspr r11,SPRN_DAR /* Save DAR */
245 mfspr r11,SPRN_DSISR /* Save DSISR */
247 std r9,_CCR(r1) /* Save CR in stackframe */
248 /* Save r9 through r13 from EXMC save area to stack frame. */
249 EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
250 mfmsr r11 /* get MSR value */
251 ori r11,r11,MSR_ME /* turn on ME bit */
252 ori r11,r11,MSR_RI /* turn on RI bit */
253 LOAD_HANDLER(r12, machine_check_handle_early)
254 1: mtspr SPRN_SRR0,r12
257 b . /* prevent speculative execution */
259 /* Stack overflow. Stay on emergency stack and panic.
260 * Keep the ME bit off while panic-ing, so that if we hit
261 * another machine check we checkstop.
263 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */
265 LOAD_HANDLER(r12, unrecover_mce)
267 andc r11,r11,r10 /* Turn off MSR_ME */
269 b . /* prevent speculative execution */
270 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
272 TRAMP_REAL_BEGIN(machine_check_pSeries)
273 .globl machine_check_fwnmi
275 SET_SCRATCH0(r13) /* save r13 */
276 EXCEPTION_PROLOG_0(PACA_EXMC)
277 machine_check_pSeries_0:
278 EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200)
280 * MSR_RI is not enabled, because PACA_EXMC is being used, so a
281 * nested machine check corrupts it. machine_check_common enables
284 EXCEPTION_PROLOG_PSERIES_1_NORI(machine_check_common, EXC_STD)
286 TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
288 EXC_COMMON_BEGIN(machine_check_common)
290 * Machine check is different because we use a different
291 * save area: PACA_EXMC instead of PACA_EXGEN.
294 std r10,PACA_EXMC+EX_DAR(r13)
296 stw r10,PACA_EXMC+EX_DSISR(r13)
297 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
299 RECONCILE_IRQ_STATE(r10, r11)
300 ld r3,PACA_EXMC+EX_DAR(r13)
301 lwz r4,PACA_EXMC+EX_DSISR(r13)
302 /* Enable MSR_RI when finished with PACA_EXMC */
308 addi r3,r1,STACK_FRAME_OVERHEAD
309 bl machine_check_exception
312 #define MACHINE_CHECK_HANDLER_WINDUP \
313 /* Clear MSR_RI before setting SRR0 and SRR1. */\
315 mfmsr r9; /* get MSR value */ \
317 mtmsrd r9,1; /* Clear MSR_RI */ \
318 /* Move original SRR0 and SRR1 into the respective regs */ \
320 mtspr SPRN_SRR1,r9; \
322 mtspr SPRN_SRR0,r3; \
334 /* Decrement paca->in_mce. */ \
335 lhz r12,PACA_IN_MCE(r13); \
337 sth r12,PACA_IN_MCE(r13); \
339 REST_2GPRS(12, r1); \
340 /* restore original r1. */ \
343 #ifdef CONFIG_PPC_P7_NAP
345 * This is an idle wakeup. Low level machine check has already been
346 * done. Queue the event then call the idle code to do the wake up.
348 EXC_COMMON_BEGIN(machine_check_idle_common)
349 bl machine_check_queue_event
352 * We have not used any non-volatile GPRs here, and as a rule
353 * most exception code including machine check does not.
354 * Therefore PACA_NAPSTATELOST does not need to be set. Idle
355 * wakeup will restore volatile registers.
357 * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce.
359 * Then decrement MCE nesting after finishing with the stack.
363 lhz r11,PACA_IN_MCE(r13)
365 sth r11,PACA_IN_MCE(r13)
367 /* Turn off the RI bit because SRR1 is used by idle wakeup code. */
368 /* Recoverability could be improved by reducing the use of SRR1. */
372 b pnv_powersave_wakeup_mce
375 * Handle machine check early in real mode. We come here with
376 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
378 EXC_COMMON_BEGIN(machine_check_handle_early)
379 std r0,GPR0(r1) /* Save r0 */
380 EXCEPTION_PROLOG_COMMON_3(0x200)
382 addi r3,r1,STACK_FRAME_OVERHEAD
383 bl machine_check_early
384 std r3,RESULT(r1) /* Save result */
387 #ifdef CONFIG_PPC_P7_NAP
389 * Check if thread was in power saving mode. We come here when any
390 * of the following is true:
391 * a. thread wasn't in power saving mode
392 * b. thread was in power saving mode with no state loss,
393 * supervisor state loss or hypervisor state loss.
395 * Go back to nap/sleep/winkle mode again if (b) is true.
398 rlwinm. r11,r12,47-31,30,31
399 bne machine_check_idle_common
400 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
404 * Check if we are coming from hypervisor userspace. If yes then we
405 * continue in host kernel in V mode to deliver the MC event.
407 rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */
409 andi. r11,r12,MSR_PR /* See if coming from user. */
410 bne 9f /* continue in V mode if we are. */
413 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
415 * We are coming from kernel context. Check if we are coming from
416 * guest. if yes, then we can continue. We will fall through
417 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest.
419 lbz r11,HSTATE_IN_GUEST(r13)
420 cmpwi r11,0 /* Check if coming from guest */
421 bne 9f /* continue if we are. */
424 * At this point we are not sure about what context we come from.
425 * Queue up the MCE event and return from the interrupt.
426 * But before that, check if this is an un-recoverable exception.
427 * If yes, then stay on emergency stack and panic.
431 1: mfspr r11,SPRN_SRR0
432 LOAD_HANDLER(r10,unrecover_mce)
436 * We are going down. But there are chances that we might get hit by
437 * another MCE during panic path and we may run into unstable state
438 * with no way out. Hence, turn ME bit off while going down, so that
439 * when another MCE is hit during panic path, system will checkstop
440 * and hypervisor will get restarted cleanly by SP.
443 andc r10,r10,r3 /* Turn off MSR_ME */
449 * Check if we have successfully handled/recovered from error, if not
450 * then stay on emergency stack and panic.
452 ld r3,RESULT(r1) /* Load result */
453 cmpdi r3,0 /* see if we handled MCE successfully */
455 beq 1b /* if !handled then panic */
457 * Return from MC interrupt.
458 * Queue up the MCE event so that we can log it later, while
459 * returning from kernel or opal call.
461 bl machine_check_queue_event
462 MACHINE_CHECK_HANDLER_WINDUP
465 /* Deliver the machine check to host kernel in V mode. */
466 MACHINE_CHECK_HANDLER_WINDUP
467 b machine_check_pSeries
469 EXC_COMMON_BEGIN(unrecover_mce)
470 /* Invoke machine_check_exception to print MCE event and panic. */
471 addi r3,r1,STACK_FRAME_OVERHEAD
472 bl machine_check_exception
474 * We will not reach here. Even if we did, there is no way out. Call
475 * unrecoverable_exception and die.
477 1: addi r3,r1,STACK_FRAME_OVERHEAD
478 bl unrecoverable_exception
482 EXC_REAL(data_access, 0x300, 0x80)
483 EXC_VIRT(data_access, 0x4300, 0x80, 0x300)
484 TRAMP_KVM_SKIP(PACA_EXGEN, 0x300)
486 EXC_COMMON_BEGIN(data_access_common)
488 * Here r13 points to the paca, r9 contains the saved CR,
489 * SRR0 and SRR1 are saved in r11 and r12,
490 * r9 - r13 are saved in paca->exgen.
493 std r10,PACA_EXGEN+EX_DAR(r13)
495 stw r10,PACA_EXGEN+EX_DSISR(r13)
496 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
497 RECONCILE_IRQ_STATE(r10, r11)
499 ld r3,PACA_EXGEN+EX_DAR(r13)
500 lwz r4,PACA_EXGEN+EX_DSISR(r13)
504 BEGIN_MMU_FTR_SECTION
505 b do_hash_page /* Try to handle as hpte fault */
508 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
511 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
513 EXCEPTION_PROLOG_0(PACA_EXSLB)
514 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380)
515 mr r12,r3 /* save r3 */
519 BRANCH_TO_COMMON(r10, slb_miss_common)
520 EXC_REAL_END(data_access_slb, 0x380, 0x80)
522 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
524 EXCEPTION_PROLOG_0(PACA_EXSLB)
525 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380)
526 mr r12,r3 /* save r3 */
530 BRANCH_TO_COMMON(r10, slb_miss_common)
531 EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
532 TRAMP_KVM_SKIP(PACA_EXSLB, 0x380)
535 EXC_REAL(instruction_access, 0x400, 0x80)
536 EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400)
537 TRAMP_KVM(PACA_EXGEN, 0x400)
539 EXC_COMMON_BEGIN(instruction_access_common)
540 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
541 RECONCILE_IRQ_STATE(r10, r11)
548 BEGIN_MMU_FTR_SECTION
549 b do_hash_page /* Try to handle as hpte fault */
552 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
555 EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
557 EXCEPTION_PROLOG_0(PACA_EXSLB)
558 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480)
559 mr r12,r3 /* save r3 */
560 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
563 BRANCH_TO_COMMON(r10, slb_miss_common)
564 EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
566 EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
568 EXCEPTION_PROLOG_0(PACA_EXSLB)
569 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480)
570 mr r12,r3 /* save r3 */
571 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
574 BRANCH_TO_COMMON(r10, slb_miss_common)
575 EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
576 TRAMP_KVM(PACA_EXSLB, 0x480)
580 * This handler is used by the 0x380 and 0x480 SLB miss interrupts, as well as
581 * the virtual mode 0x4380 and 0x4480 interrupts if AIL is enabled.
583 EXC_COMMON_BEGIN(slb_miss_common)
585 * r13 points to the PACA, r9 contains the saved CR,
586 * r12 contains the saved r3,
587 * r11 contain the saved SRR1, SRR0 is still ready for return
588 * r3 has the faulting address
589 * r9 - r13 are saved in paca->exslb.
590 * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss
591 * We assume we aren't going to take any exceptions during this
595 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
596 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
599 * Test MSR_RI before calling slb_allocate_realmode, because the
600 * MSR in r11 gets clobbered. However we still want to allocate
601 * SLB in case MSR_RI=0, to minimise the risk of getting stuck in
602 * recursive SLB faults. So use cr5 for this, which is preserved.
604 andi. r11,r11,MSR_RI /* check for unrecoverable exception */
608 #ifdef CONFIG_PPC_STD_MMU_64
609 BEGIN_MMU_FTR_SECTION
611 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
614 ld r10,PACA_EXSLB+EX_LR(r13)
615 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
618 beq- 8f /* if bad address, make full stack frame */
620 bne- cr5,2f /* if unrecoverable exception, oops */
622 /* All done -- return from exception. */
627 mtcrf 0x04,r9 /* MSR[RI] indication is in cr5 */
628 mtcrf 0x02,r9 /* I/D indication is in cr6 */
629 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
632 RESTORE_CTR(r9, PACA_EXSLB)
633 RESTORE_PPR_PACA(PACA_EXSLB, r9)
635 ld r9,PACA_EXSLB+EX_R9(r13)
636 ld r10,PACA_EXSLB+EX_R10(r13)
637 ld r11,PACA_EXSLB+EX_R11(r13)
638 ld r12,PACA_EXSLB+EX_R12(r13)
639 ld r13,PACA_EXSLB+EX_R13(r13)
641 b . /* prevent speculative execution */
643 2: std r3,PACA_EXSLB+EX_DAR(r13)
647 LOAD_HANDLER(r10,unrecov_slb)
654 8: std r3,PACA_EXSLB+EX_DAR(r13)
658 LOAD_HANDLER(r10,bad_addr_slb)
665 EXC_COMMON_BEGIN(unrecov_slb)
666 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
667 RECONCILE_IRQ_STATE(r10, r11)
669 1: addi r3,r1,STACK_FRAME_OVERHEAD
670 bl unrecoverable_exception
673 EXC_COMMON_BEGIN(bad_addr_slb)
674 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB)
675 RECONCILE_IRQ_STATE(r10, r11)
676 ld r3, PACA_EXSLB+EX_DAR(r13)
679 li r10, 0x480 /* fix trap number for I-SLB miss */
682 addi r3, r1, STACK_FRAME_OVERHEAD
686 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
687 .globl hardware_interrupt_hv;
688 hardware_interrupt_hv:
690 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
691 EXC_HV, SOFTEN_TEST_HV)
693 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
694 EXC_STD, SOFTEN_TEST_PR)
695 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
696 EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
698 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
699 .globl hardware_interrupt_relon_hv;
700 hardware_interrupt_relon_hv:
702 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV)
704 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR)
705 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
706 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
708 TRAMP_KVM(PACA_EXGEN, 0x500)
709 TRAMP_KVM_HV(PACA_EXGEN, 0x500)
710 EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
713 EXC_REAL(alignment, 0x600, 0x100)
714 EXC_VIRT(alignment, 0x4600, 0x100, 0x600)
715 TRAMP_KVM(PACA_EXGEN, 0x600)
716 EXC_COMMON_BEGIN(alignment_common)
718 std r10,PACA_EXGEN+EX_DAR(r13)
720 stw r10,PACA_EXGEN+EX_DSISR(r13)
721 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
722 ld r3,PACA_EXGEN+EX_DAR(r13)
723 lwz r4,PACA_EXGEN+EX_DSISR(r13)
727 RECONCILE_IRQ_STATE(r10, r11)
728 addi r3,r1,STACK_FRAME_OVERHEAD
729 bl alignment_exception
733 EXC_REAL(program_check, 0x700, 0x100)
734 EXC_VIRT(program_check, 0x4700, 0x100, 0x700)
735 TRAMP_KVM(PACA_EXGEN, 0x700)
736 EXC_COMMON_BEGIN(program_check_common)
737 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
739 RECONCILE_IRQ_STATE(r10, r11)
740 addi r3,r1,STACK_FRAME_OVERHEAD
741 bl program_check_exception
745 EXC_REAL(fp_unavailable, 0x800, 0x100)
746 EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800)
747 TRAMP_KVM(PACA_EXGEN, 0x800)
748 EXC_COMMON_BEGIN(fp_unavailable_common)
749 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
750 bne 1f /* if from user, just load it up */
752 RECONCILE_IRQ_STATE(r10, r11)
753 addi r3,r1,STACK_FRAME_OVERHEAD
754 bl kernel_fp_unavailable_exception
757 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
759 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
760 * transaction), go do TM stuff
762 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
764 END_FTR_SECTION_IFSET(CPU_FTR_TM)
767 b fast_exception_return
768 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
769 2: /* User process was in a transaction */
771 RECONCILE_IRQ_STATE(r10, r11)
772 addi r3,r1,STACK_FRAME_OVERHEAD
778 EXC_REAL_MASKABLE(decrementer, 0x900, 0x80)
779 EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900)
780 TRAMP_KVM(PACA_EXGEN, 0x900)
781 EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt)
784 EXC_REAL_HV(hdecrementer, 0x980, 0x80)
785 EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980)
786 TRAMP_KVM_HV(PACA_EXGEN, 0x980)
787 EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt)
790 EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100)
791 EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00)
792 TRAMP_KVM(PACA_EXGEN, 0xa00)
793 #ifdef CONFIG_PPC_DOORBELL
794 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception)
796 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception)
800 EXC_REAL(trap_0b, 0xb00, 0x100)
801 EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00)
802 TRAMP_KVM(PACA_EXGEN, 0xb00)
803 EXC_COMMON(trap_0b_common, 0xb00, unknown_exception)
806 * system call / hypercall (0xc00, 0x4c00)
808 * The system call exception is invoked with "sc 0" and does not alter HV bit.
809 * There is support for kernel code to invoke system calls but there are no
812 * The hypercall is invoked with "sc 1" and sets HV=1.
814 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to
815 * 0x4c00 virtual mode.
819 * syscall register convention is in Documentation/powerpc/syscall64-abi.txt
821 * For hypercalls, the register convention is as follows:
824 * r3 volatile parameter and return value for status
825 * r4-r10 volatile input and output value
826 * r11 volatile hypercall number and output value
828 * r13-r31 nonvolatile
832 * CR0-1 CR5-7 volatile
834 * Other registers nonvolatile
836 * The intersection of volatile registers that don't contain possible
837 * inputs is: r12, cr0, xer, ctr. We may use these as scratch regs
838 * upon entry without saving.
840 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
842 * There is a little bit of juggling to get syscall and hcall
843 * working well. Save r10 in ctr to be restored in case it is a
846 * Userspace syscalls have already saved the PPR, hcalls must save
847 * it before setting HMT_MEDIUM.
849 #define SYSCALL_KVMTEST \
853 KVMTEST_PR(0xc00); /* uses r10, branch to do_kvm_0xc00_system_call */ \
858 #define SYSCALL_KVMTEST \
864 #define LOAD_SYSCALL_HANDLER(reg) \
865 __LOAD_HANDLER(reg, system_call_common)
867 #define SYSCALL_FASTENDIAN_TEST \
871 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \
874 * After SYSCALL_KVMTEST, we reach here with PACA in r13, r13 in r9,
877 #define SYSCALL_REAL \
878 mfspr r11,SPRN_SRR0 ; \
879 mfspr r12,SPRN_SRR1 ; \
880 LOAD_SYSCALL_HANDLER(r10) ; \
881 mtspr SPRN_SRR0,r10 ; \
882 ld r10,PACAKMSR(r13) ; \
883 mtspr SPRN_SRR1,r10 ; \
885 b . ; /* prevent speculative execution */
887 #define SYSCALL_FASTENDIAN \
888 /* Fast LE/BE switch system call */ \
889 1: mfspr r12,SPRN_SRR1 ; \
890 xori r12,r12,MSR_LE ; \
891 mtspr SPRN_SRR1,r12 ; \
893 rfid ; /* return to userspace */ \
894 b . ; /* prevent speculative execution */
896 #if defined(CONFIG_RELOCATABLE)
898 * We can't branch directly so we do it via the CTR which
899 * is volatile across system calls.
901 #define SYSCALL_VIRT \
902 LOAD_SYSCALL_HANDLER(r10) ; \
904 mfspr r11,SPRN_SRR0 ; \
905 mfspr r12,SPRN_SRR1 ; \
910 /* We can branch directly */
911 #define SYSCALL_VIRT \
912 mfspr r11,SPRN_SRR0 ; \
913 mfspr r12,SPRN_SRR1 ; \
915 mtmsrd r10,1 ; /* Set RI (EE=0) */ \
916 b system_call_common ;
919 EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
920 SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */
921 SYSCALL_FASTENDIAN_TEST
924 EXC_REAL_END(system_call, 0xc00, 0x100)
926 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
927 SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */
928 SYSCALL_FASTENDIAN_TEST
931 EXC_VIRT_END(system_call, 0x4c00, 0x100)
933 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
935 * This is a hcall, so register convention is as above, with these
941 TRAMP_KVM_BEGIN(do_kvm_0xc00)
943 * Save the PPR (on systems that support it) before changing to
944 * HMT_MEDIUM. That allows the KVM code to save that value into the
945 * guest state (it is the guest's PPR value).
947 OPT_GET_SPR(r0, SPRN_PPR, CPU_FTR_HAS_PPR)
949 OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r0, CPU_FTR_HAS_PPR)
952 std r9,PACA_EXGEN+EX_R9(r13)
954 std r10,PACA_EXGEN+EX_R10(r13)
955 KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00)
959 EXC_REAL(single_step, 0xd00, 0x100)
960 EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00)
961 TRAMP_KVM(PACA_EXGEN, 0xd00)
962 EXC_COMMON(single_step_common, 0xd00, single_step_exception)
964 EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20)
965 EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00)
966 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00)
967 EXC_COMMON_BEGIN(h_data_storage_common)
969 std r10,PACA_EXGEN+EX_DAR(r13)
970 mfspr r10,SPRN_HDSISR
971 stw r10,PACA_EXGEN+EX_DSISR(r13)
972 EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
974 RECONCILE_IRQ_STATE(r10, r11)
975 addi r3,r1,STACK_FRAME_OVERHEAD
980 EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20)
981 EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20)
982 TRAMP_KVM_HV(PACA_EXGEN, 0xe20)
983 EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception)
986 EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20)
987 EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40)
988 TRAMP_KVM_HV(PACA_EXGEN, 0xe40)
989 EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt)
993 * hmi_exception trampoline is a special case. It jumps to hmi_exception_early
994 * first, and then eventaully from there to the trampoline to get into virtual
997 __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early)
998 __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60)
999 EXC_VIRT_NONE(0x4e60, 0x20)
1000 TRAMP_KVM_HV(PACA_EXGEN, 0xe60)
1001 TRAMP_REAL_BEGIN(hmi_exception_early)
1002 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60)
1003 mr r10,r1 /* Save r1 */
1004 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */
1005 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1006 mfspr r11,SPRN_HSRR0 /* Save HSRR0 */
1007 mfspr r12,SPRN_HSRR1 /* Save HSRR1 */
1008 EXCEPTION_PROLOG_COMMON_1()
1009 EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN)
1010 EXCEPTION_PROLOG_COMMON_3(0xe60)
1011 addi r3,r1,STACK_FRAME_OVERHEAD
1012 BRANCH_LINK_TO_FAR(hmi_exception_realmode) /* Function call ABI */
1013 /* Windup the stack. */
1014 /* Move original HSRR0 and HSRR1 into the respective regs */
1032 /* restore original r1. */
1036 * Go to virtual mode and pull the HMI event information from
1039 .globl hmi_exception_after_realmode
1040 hmi_exception_after_realmode:
1042 EXCEPTION_PROLOG_0(PACA_EXGEN)
1043 b tramp_real_hmi_exception
1045 EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception)
1048 EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20)
1049 EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80)
1050 TRAMP_KVM_HV(PACA_EXGEN, 0xe80)
1051 #ifdef CONFIG_PPC_DOORBELL
1052 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception)
1054 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception)
1058 EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20)
1059 EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0)
1060 TRAMP_KVM_HV(PACA_EXGEN, 0xea0)
1061 EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ)
1064 EXC_REAL_NONE(0xec0, 0x20)
1065 EXC_VIRT_NONE(0x4ec0, 0x20)
1066 EXC_REAL_NONE(0xee0, 0x20)
1067 EXC_VIRT_NONE(0x4ee0, 0x20)
1070 EXC_REAL_OOL(performance_monitor, 0xf00, 0x20)
1071 EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x20, 0xf00)
1072 TRAMP_KVM(PACA_EXGEN, 0xf00)
1073 EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception)
1076 EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20)
1077 EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20)
1078 TRAMP_KVM(PACA_EXGEN, 0xf20)
1079 EXC_COMMON_BEGIN(altivec_unavailable_common)
1080 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1081 #ifdef CONFIG_ALTIVEC
1084 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1085 BEGIN_FTR_SECTION_NESTED(69)
1086 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1087 * transaction), go do TM stuff
1089 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1091 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1094 b fast_exception_return
1095 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1096 2: /* User process was in a transaction */
1098 RECONCILE_IRQ_STATE(r10, r11)
1099 addi r3,r1,STACK_FRAME_OVERHEAD
1100 bl altivec_unavailable_tm
1104 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1107 RECONCILE_IRQ_STATE(r10, r11)
1108 addi r3,r1,STACK_FRAME_OVERHEAD
1109 bl altivec_unavailable_exception
1113 EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20)
1114 EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40)
1115 TRAMP_KVM(PACA_EXGEN, 0xf40)
1116 EXC_COMMON_BEGIN(vsx_unavailable_common)
1117 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
1121 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1122 BEGIN_FTR_SECTION_NESTED(69)
1123 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1124 * transaction), go do TM stuff
1126 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1128 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1131 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1132 2: /* User process was in a transaction */
1134 RECONCILE_IRQ_STATE(r10, r11)
1135 addi r3,r1,STACK_FRAME_OVERHEAD
1136 bl vsx_unavailable_tm
1140 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1143 RECONCILE_IRQ_STATE(r10, r11)
1144 addi r3,r1,STACK_FRAME_OVERHEAD
1145 bl vsx_unavailable_exception
1149 EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20)
1150 EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60)
1151 TRAMP_KVM(PACA_EXGEN, 0xf60)
1152 EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception)
1155 EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20)
1156 EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80)
1157 TRAMP_KVM_HV(PACA_EXGEN, 0xf80)
1158 EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception)
1161 EXC_REAL_NONE(0xfa0, 0x20)
1162 EXC_VIRT_NONE(0x4fa0, 0x20)
1163 EXC_REAL_NONE(0xfc0, 0x20)
1164 EXC_VIRT_NONE(0x4fc0, 0x20)
1165 EXC_REAL_NONE(0xfe0, 0x20)
1166 EXC_VIRT_NONE(0x4fe0, 0x20)
1168 EXC_REAL_NONE(0x1000, 0x100)
1169 EXC_VIRT_NONE(0x5000, 0x100)
1170 EXC_REAL_NONE(0x1100, 0x100)
1171 EXC_VIRT_NONE(0x5100, 0x100)
1173 #ifdef CONFIG_CBE_RAS
1174 EXC_REAL_HV(cbe_system_error, 0x1200, 0x100)
1175 EXC_VIRT_NONE(0x5200, 0x100)
1176 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200)
1177 EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception)
1178 #else /* CONFIG_CBE_RAS */
1179 EXC_REAL_NONE(0x1200, 0x100)
1180 EXC_VIRT_NONE(0x5200, 0x100)
1184 EXC_REAL(instruction_breakpoint, 0x1300, 0x100)
1185 EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300)
1186 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300)
1187 EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception)
1189 EXC_REAL_NONE(0x1400, 0x100)
1190 EXC_VIRT_NONE(0x5400, 0x100)
1192 EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
1193 mtspr SPRN_SPRG_HSCRATCH0,r13
1194 EXCEPTION_PROLOG_0(PACA_EXGEN)
1195 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500)
1197 #ifdef CONFIG_PPC_DENORMALISATION
1198 mfspr r10,SPRN_HSRR1
1199 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
1200 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */
1201 addi r11,r11,-4 /* HSRR0 is next instruction */
1206 EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV)
1207 EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100)
1209 #ifdef CONFIG_PPC_DENORMALISATION
1210 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
1211 b exc_real_0x1500_denorm_exception_hv
1212 EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
1214 EXC_VIRT_NONE(0x5500, 0x100)
1217 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500)
1219 #ifdef CONFIG_PPC_DENORMALISATION
1220 TRAMP_REAL_BEGIN(denorm_assist)
1223 * To denormalise we need to move a copy of the register to itself.
1224 * For POWER6 do that here for all FP regs.
1227 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
1228 xori r10,r10,(MSR_FE0|MSR_FE1)
1232 #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1
1233 #define FMR4(n) FMR2(n) ; FMR2(n+2)
1234 #define FMR8(n) FMR4(n) ; FMR4(n+4)
1235 #define FMR16(n) FMR8(n) ; FMR8(n+8)
1236 #define FMR32(n) FMR16(n) ; FMR16(n+16)
1241 * To denormalise we need to move a copy of the register to itself.
1242 * For POWER7 do that here for the first 32 VSX registers only.
1245 oris r10,r10,MSR_VSX@h
1249 #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)
1250 #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)
1251 #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)
1252 #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)
1253 #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)
1256 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
1260 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1262 * To denormalise we need to move a copy of the register to itself.
1263 * For POWER8 we need to do that for all 64 VSX registers
1267 mtspr SPRN_HSRR0,r11
1269 ld r9,PACA_EXGEN+EX_R9(r13)
1270 RESTORE_PPR_PACA(PACA_EXGEN, r10)
1272 ld r10,PACA_EXGEN+EX_CFAR(r13)
1274 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1275 ld r10,PACA_EXGEN+EX_R10(r13)
1276 ld r11,PACA_EXGEN+EX_R11(r13)
1277 ld r12,PACA_EXGEN+EX_R12(r13)
1278 ld r13,PACA_EXGEN+EX_R13(r13)
1283 EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception)
1286 #ifdef CONFIG_CBE_RAS
1287 EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100)
1288 EXC_VIRT_NONE(0x5600, 0x100)
1289 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600)
1290 EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception)
1291 #else /* CONFIG_CBE_RAS */
1292 EXC_REAL_NONE(0x1600, 0x100)
1293 EXC_VIRT_NONE(0x5600, 0x100)
1297 EXC_REAL(altivec_assist, 0x1700, 0x100)
1298 EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700)
1299 TRAMP_KVM(PACA_EXGEN, 0x1700)
1300 #ifdef CONFIG_ALTIVEC
1301 EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception)
1303 EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception)
1307 #ifdef CONFIG_CBE_RAS
1308 EXC_REAL_HV(cbe_thermal, 0x1800, 0x100)
1309 EXC_VIRT_NONE(0x5800, 0x100)
1310 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800)
1311 EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception)
1312 #else /* CONFIG_CBE_RAS */
1313 EXC_REAL_NONE(0x1800, 0x100)
1314 EXC_VIRT_NONE(0x5800, 0x100)
1317 #if defined(CONFIG_HARDLOCKUP_DETECTOR) && defined(CONFIG_HAVE_HARDLOCKUP_DETECTOR_ARCH)
1319 #define MASKED_DEC_HANDLER_LABEL 3f
1321 #define MASKED_DEC_HANDLER(_H) \
1323 std r12,PACA_EXGEN+EX_R12(r13); \
1324 GET_SCRATCH0(r10); \
1325 std r10,PACA_EXGEN+EX_R13(r13); \
1326 EXCEPTION_PROLOG_PSERIES_1(soft_nmi_common, _H)
1328 EXC_COMMON_BEGIN(soft_nmi_common)
1330 ld r1,PACAEMERGSP(r13)
1331 ld r1,PACA_NMI_EMERG_SP(r13)
1332 subi r1,r1,INT_FRAME_SIZE
1333 EXCEPTION_COMMON_NORET_STACK(PACA_EXGEN, 0x900,
1334 system_reset, soft_nmi_interrupt,
1335 ADD_NVGPRS;ADD_RECONCILE)
1339 #define MASKED_DEC_HANDLER_LABEL 2f /* normal return */
1340 #define MASKED_DEC_HANDLER(_H)
1344 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
1345 * - If it was a decrementer interrupt, we bump the dec to max and and return.
1346 * - If it was a doorbell we return immediately since doorbells are edge
1347 * triggered and won't automatically refire.
1348 * - If it was a HMI we return immediately since we handled it in realmode
1349 * and it won't refire.
1350 * - else we hard disable and return.
1351 * This is called with r10 containing the value to OR to the paca field.
1353 #define MASKED_INTERRUPT(_H) \
1354 masked_##_H##interrupt: \
1355 std r11,PACA_EXGEN+EX_R11(r13); \
1356 lbz r11,PACAIRQHAPPENED(r13); \
1358 stb r11,PACAIRQHAPPENED(r13); \
1359 cmpwi r10,PACA_IRQ_DEC; \
1362 ori r10,r10,0xffff; \
1363 mtspr SPRN_DEC,r10; \
1364 b MASKED_DEC_HANDLER_LABEL; \
1365 1: cmpwi r10,PACA_IRQ_DBELL; \
1367 cmpwi r10,PACA_IRQ_HMI; \
1369 mfspr r10,SPRN_##_H##SRR1; \
1370 rldicl r10,r10,48,1; /* clear MSR_EE */ \
1371 rotldi r10,r10,16; \
1372 mtspr SPRN_##_H##SRR1,r10; \
1374 ld r9,PACA_EXGEN+EX_R9(r13); \
1375 ld r10,PACA_EXGEN+EX_R10(r13); \
1376 ld r11,PACA_EXGEN+EX_R11(r13); \
1377 GET_SCRATCH0(r13); \
1380 MASKED_DEC_HANDLER(_H)
1383 * Real mode exceptions actually use this too, but alternate
1384 * instruction code patches (which end up in the common .text area)
1385 * cannot reach these if they are put there.
1387 USE_FIXED_SECTION(virt_trampolines)
1391 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1392 TRAMP_REAL_BEGIN(kvmppc_skip_interrupt)
1394 * Here all GPRs are unchanged from when the interrupt happened
1395 * except for r13, which is saved in SPRG_SCRATCH0.
1397 mfspr r13, SPRN_SRR0
1399 mtspr SPRN_SRR0, r13
1404 TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt)
1406 * Here all GPRs are unchanged from when the interrupt happened
1407 * except for r13, which is saved in SPRG_SCRATCH0.
1409 mfspr r13, SPRN_HSRR0
1411 mtspr SPRN_HSRR0, r13
1418 * Ensure that any handlers that get invoked from the exception prologs
1419 * above are below the first 64KB (0x10000) of the kernel image because
1420 * the prologs assemble the addresses of these handlers using the
1421 * LOAD_HANDLER macro, which uses an ori instruction.
1424 /*** Common interrupt handlers ***/
1428 * Relocation-on interrupts: A subset of the interrupts can be delivered
1429 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
1430 * it. Addresses are the same as the original interrupt addresses, but
1431 * offset by 0xc000000000004000.
1432 * It's impossible to receive interrupts below 0x300 via this mechanism.
1433 * KVM: None of these traps are from the guest ; anything that escalated
1434 * to HV=1 from HV=0 is delivered via real mode handlers.
1438 * This uses the standard macro, since the original 0x300 vector
1439 * only has extra guff for STAB-based processors -- which never
1443 EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline)
1444 b __ppc64_runlatch_on
1446 USE_FIXED_SECTION(virt_trampolines)
1448 * The __end_interrupts marker must be past the out-of-line (OOL)
1449 * handlers, so that they are copied to real address 0x100 when running
1450 * a relocatable kernel. This ensures they can be reached from the short
1451 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
1452 * directly, without using LOAD_HANDLER().
1455 .globl __end_interrupts
1457 DEFINE_FIXED_SYMBOL(__end_interrupts)
1459 #ifdef CONFIG_PPC_970_NAP
1460 EXC_COMMON_BEGIN(power4_fixup_nap)
1462 std r9,TI_LOCAL_FLAGS(r11)
1463 ld r10,_LINK(r1) /* make idle task do the */
1464 std r10,_NIP(r1) /* equivalent of a blr */
1468 CLOSE_FIXED_SECTION(real_vectors);
1469 CLOSE_FIXED_SECTION(real_trampolines);
1470 CLOSE_FIXED_SECTION(virt_vectors);
1471 CLOSE_FIXED_SECTION(virt_trampolines);
1478 .balign IFETCH_ALIGN_BYTES
1480 #ifdef CONFIG_PPC_STD_MMU_64
1481 andis. r0,r4,0xa450 /* weird error? */
1482 bne- handle_page_fault /* if not, try to insert a HPTE */
1483 CURRENT_THREAD_INFO(r11, r1)
1484 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */
1485 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */
1486 bne 77f /* then don't call hash_page now */
1489 * r3 contains the faulting address
1491 * r5 contains the trap number
1494 * at return r3 = 0 for success, 1 for page fault, negative for error
1498 bl __hash_page /* build HPTE if possible */
1499 cmpdi r3,0 /* see if __hash_page succeeded */
1502 beq fast_exc_return_irq /* Return from exception on success */
1507 /* Reload DSISR into r4 for the DABR check below */
1509 #endif /* CONFIG_PPC_STD_MMU_64 */
1511 /* Here we have a page fault that hash_page can't handle. */
1513 11: andis. r0,r4,DSISR_DABRMATCH@h
1514 bne- handle_dabr_fault
1517 addi r3,r1,STACK_FRAME_OVERHEAD
1523 addi r3,r1,STACK_FRAME_OVERHEAD
1528 /* We have a data breakpoint exception - handle it */
1533 addi r3,r1,STACK_FRAME_OVERHEAD
1535 12: b ret_from_except_lite
1538 #ifdef CONFIG_PPC_STD_MMU_64
1539 /* We have a page fault that hash_page could handle but HV refused
1544 addi r3,r1,STACK_FRAME_OVERHEAD
1551 * We come here as a result of a DSI at a point where we don't want
1552 * to call hash_page, such as when we are accessing memory (possibly
1553 * user memory) inside a PMU interrupt that occurred while interrupts
1554 * were soft-disabled. We want to invoke the exception handler for
1555 * the access, or panic if there isn't a handler.
1559 addi r3,r1,STACK_FRAME_OVERHEAD
1565 * Here we have detected that the kernel stack pointer is bad.
1566 * R9 contains the saved CR, r13 points to the paca,
1567 * r10 contains the (bad) kernel stack pointer,
1568 * r11 and r12 contain the saved SRR0 and SRR1.
1569 * We switch to using an emergency stack, save the registers there,
1570 * and call kernel_bad_stack(), which panics.
1573 ld r1,PACAEMERGSP(r13)
1574 subi r1,r1,64+INT_FRAME_SIZE
1580 mfspr r12,SPRN_DSISR
1606 std r10,ORIG_GPR3(r1)
1607 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1610 lhz r12,PACA_TRAP_SAVE(r13)
1612 addi r11,r1,INT_FRAME_SIZE
1617 ld r11,exception_marker@toc(r2)
1619 std r11,STACK_FRAME_OVERHEAD-16(r1)
1620 1: addi r3,r1,STACK_FRAME_OVERHEAD
1623 _ASM_NOKPROBE_SYMBOL(bad_stack);
1626 * When doorbell is triggered from system reset wakeup, the message is
1627 * not cleared, so it would fire again when EE is enabled.
1629 * When coming from local_irq_enable, there may be the same problem if
1630 * we were hard disabled.
1632 * Execute msgclr to clear pending exceptions before handling it.
1634 h_doorbell_common_msgclr:
1635 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
1639 doorbell_super_common_msgclr:
1640 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
1642 b doorbell_super_common
1645 * Called from arch_local_irq_enable when an interrupt needs
1646 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate
1647 * which kind of interrupt. MSR:EE is already off. We generate a
1648 * stackframe like if a real interrupt had happened.
1650 * Note: While MSR:EE is off, we need to make sure that _MSR
1651 * in the generated frame has EE set to 1 or the exception
1652 * handler will not properly re-enable them.
1654 * Note that we don't specify LR as the NIP (return address) for
1655 * the interrupt because that would unbalance the return branch
1658 _GLOBAL(__replay_interrupt)
1659 /* We are going to jump to the exception common code which
1660 * will retrieve various register values from the PACA which
1661 * we don't give a damn about, so we don't bother storing them.
1664 LOAD_REG_ADDR(r11, 1f)
1668 beq decrementer_common
1670 beq hardware_interrupt_common
1673 beq h_doorbell_common_msgclr
1675 beq h_virt_irq_common
1677 beq hmi_exception_common
1680 beq doorbell_super_common_msgclr
1681 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
1685 _ASM_NOKPROBE_SYMBOL(__replay_interrupt)