3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
15 * This file contains the entry point for the 64-bit kernel along
16 * with some early initialization code common to all 64-bit powerpc
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
25 #include <linux/threads.h>
26 #include <linux/init.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/head-64.h>
32 #include <asm/asm-offsets.h>
34 #include <asm/cputable.h>
35 #include <asm/setup.h>
36 #include <asm/hvcall.h>
37 #include <asm/thread_info.h>
38 #include <asm/firmware.h>
39 #include <asm/page_64.h>
40 #include <asm/irqflags.h>
41 #include <asm/kvm_book3s_asm.h>
42 #include <asm/ptrace.h>
43 #include <asm/hw_irq.h>
44 #include <asm/cputhreads.h>
45 #include <asm/ppc-opcode.h>
46 #include <asm/export.h>
48 /* The physical memory is laid out such that the secondary processor
49 * spin code sits at 0x0000...0x00ff. On server, the vectors follow
50 * using the layout described in exceptions-64s.S
54 * Entering into this code we make the following assumptions:
56 * For pSeries or server processors:
57 * 1. The MMU is off & open firmware is running in real mode.
58 * 2. The primary CPU enters at __start.
59 * 3. If the RTAS supports "query-cpu-stopped-state", then secondary
60 * CPUs will enter as directed by "start-cpu" RTAS call, which is
61 * generic_secondary_smp_init, with PIR in r3.
62 * 4. Else the secondary CPUs will enter at secondary_hold (0x60) as
63 * directed by the "start-cpu" RTS call, with PIR in r3.
64 * -or- For OPAL entry:
65 * 1. The MMU is off, processor in HV mode.
66 * 2. The primary CPU enters at 0 with device-tree in r3, OPAL base
67 * in r8, and entry in r9 for debugging purposes.
68 * 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which
69 * is at generic_secondary_smp_init, with PIR in r3.
71 * For Book3E processors:
72 * 1. The MMU is on running in AS0 in a state defined in ePAPR
73 * 2. The kernel is entered at __start
76 OPEN_FIXED_SECTION(first_256B, 0x0, 0x100)
77 USE_FIXED_SECTION(first_256B)
79 * Offsets are relative from the start of fixed section, and
80 * first_256B starts at 0. Offsets are a bit easier to use here
81 * than the fixed section entry macros.
85 /* NOP this out unconditionally */
88 b __start_initialization_multiplatform
91 /* Catch branch to 0 in real mode */
94 /* Secondary processors spin on this value until it becomes non-zero.
95 * When non-zero, it contains the real address of the function the cpu
99 .globl __secondary_hold_spinloop
100 __secondary_hold_spinloop:
103 /* Secondary processors write this value with their cpu # */
104 /* after they enter the spin loop immediately below. */
105 .globl __secondary_hold_acknowledge
106 __secondary_hold_acknowledge:
109 #ifdef CONFIG_RELOCATABLE
110 /* This flag is set to 1 by a loader if the kernel should run
111 * at the loaded address instead of the linked address. This
112 * is used by kexec-tools to keep the the kdump kernel in the
113 * crash_kernel region. The loader is responsible for
114 * observing the alignment requirement.
117 #ifdef CONFIG_RELOCATABLE_TEST
118 #define RUN_AT_LOAD_DEFAULT 1 /* Test relocation, do not copy to 0 */
120 #define RUN_AT_LOAD_DEFAULT 0x72756e30 /* "run0" -- relocate to 0 by default */
123 /* Do not move this variable as kexec-tools knows about it. */
127 DEFINE_FIXED_SYMBOL(__run_at_load)
128 .long RUN_AT_LOAD_DEFAULT
133 * The following code is used to hold secondary processors
134 * in a spin loop after they have entered the kernel, but
135 * before the bulk of the kernel has been relocated. This code
136 * is relocated to physical address 0x60 before prom_init is run.
137 * All of it must fit below the first exception vector at 0x100.
138 * Use .globl here not _GLOBAL because we want __secondary_hold
139 * to be the actual text address, not a descriptor.
141 .globl __secondary_hold
144 #ifndef CONFIG_PPC_BOOK3E
147 mtmsrd r24 /* RI on */
149 /* Grab our physical cpu number */
151 /* stash r4 for book3e */
154 /* Tell the master cpu we're here */
155 /* Relocation is off & we are located at an address less */
156 /* than 0x100, so only need to grab low order offset. */
157 std r24,(ABS_ADDR(__secondary_hold_acknowledge))(0)
161 #ifdef CONFIG_PPC_BOOK3E
164 /* All secondary cpus wait here until told to start. */
165 100: ld r12,(ABS_ADDR(__secondary_hold_spinloop))(r26)
169 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
170 #ifdef CONFIG_PPC_BOOK3E
176 * it may be the case that other platforms have r4 right to
177 * begin with, this gives us some safety in case it is not
179 #ifdef CONFIG_PPC_BOOK3E
184 /* Make sure that patched code is visible */
190 CLOSE_FIXED_SECTION(first_256B)
192 /* This value is used to mark exception frames on the stack. */
195 .tc ID_72656773_68657265[TC],0x7265677368657265
199 * On server, we include the exception vectors code here as it
200 * relies on absolute addressing which is only possible within
201 * this compilation unit
203 #ifdef CONFIG_PPC_BOOK3S
204 #include "exceptions-64s.S"
206 OPEN_TEXT_SECTION(0x100)
211 #ifdef CONFIG_PPC_BOOK3E
213 * The booting_thread_hwid holds the thread id we want to boot in cpu
214 * hotplug case. It is set by cpu hotplug code, and is invalid by default.
215 * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID]
218 .globl booting_thread_hwid
220 .long INVALID_THREAD_HWID
223 * start a thread in the same core
225 * r3 = the thread physical id
226 * r4 = the entry point where thread starts
228 _GLOBAL(book3e_start_thread)
229 LOAD_REG_IMMEDIATE(r5, MSR_KERNEL)
234 /* If the thread id is invalid, just exit. */
252 * stop a thread in the same core
254 * r3 = the thread physical id
256 _GLOBAL(book3e_stop_thread)
261 /* If the thread id is invalid, just exit. */
270 _GLOBAL(fsl_secondary_thread_init)
273 /* Enable branch prediction */
275 ori r3,r3,BUCSR_INIT@l
280 * Fix PIR to match the linear numbering in the device tree.
282 * On e6500, the reset value of PIR uses the low three bits for
283 * the thread within a core, and the upper bits for the core
284 * number. There are two threads per core, so shift everything
285 * but the low bit right by two bits so that the cpu numbering is
288 * If the old value of BUCSR is non-zero, this thread has run
289 * before. Thus, we assume we are coming from kexec or a similar
290 * scenario, and PIR is already set to the correct value. This
291 * is a bit of a hack, but there are limited opportunities for
292 * getting information into the thread and the alternatives
293 * seemed like they'd be overkill. We can't tell just by looking
294 * at the old PIR value which state it's in, since the same value
295 * could be valid for one thread out of reset and for a different
302 rlwimi r3, r3, 30, 2, 30
307 _GLOBAL(generic_secondary_thread_init)
310 /* turn on 64-bit mode */
313 /* get a valid TOC pointer, wherever we're mapped at */
317 #ifdef CONFIG_PPC_BOOK3E
318 /* Book3E initialization */
320 bl book3e_secondary_thread_init
322 b generic_secondary_common_init
325 * On pSeries and most other platforms, secondary processors spin
326 * in the following code.
327 * At entry, r3 = this processor's number (physical cpu id)
329 * On Book3E, r4 = 1 to indicate that the initial TLB entry for
330 * this core already exists (setup via some other mechanism such
331 * as SCOM before entry).
333 _GLOBAL(generic_secondary_smp_init)
338 /* turn on 64-bit mode */
341 /* get a valid TOC pointer, wherever we're mapped at */
345 #ifdef CONFIG_PPC_BOOK3E
346 /* Book3E initialization */
349 bl book3e_secondary_core_init
352 * After common core init has finished, check if the current thread is the
353 * one we wanted to boot. If not, start the specified thread and stop the
356 LOAD_REG_ADDR(r4, booting_thread_hwid)
358 li r5, INVALID_THREAD_HWID
363 * The value of booting_thread_hwid has been stored in r3,
364 * so make it invalid.
369 * Get the current thread id and check if it is the one we wanted.
370 * If not, start the one specified in booting_thread_hwid and stop
371 * the current thread.
377 /* start the specified thread */
378 LOAD_REG_ADDR(r5, fsl_secondary_thread_init)
380 bl book3e_start_thread
382 /* stop the current thread */
384 bl book3e_stop_thread
390 generic_secondary_common_init:
391 /* Set up a paca value for this processor. Since we have the
392 * physical cpu id in r24, we need to search the pacas to find
393 * which logical id maps to our physical one.
396 b kexec_wait /* wait for next kernel if !SMP */
398 LOAD_REG_ADDR(r8, paca_ptrs) /* Load paca_ptrs pointe */
399 ld r8,0(r8) /* Get base vaddr of array */
400 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */
401 lwz r7,0(r7) /* also the max paca allocated */
402 li r5,0 /* logical cpu id */
404 sldi r9,r5,3 /* get paca_ptrs[] index from cpu id */
405 ldx r13,r9,r8 /* r13 = paca_ptrs[cpu id] */
406 lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
407 cmpw r6,r24 /* Compare to our id */
410 cmpw r5,r7 /* Check if more pacas exist */
413 mr r3,r24 /* not found, copy phys to r3 */
414 b kexec_wait /* next kernel might do better */
417 #ifdef CONFIG_PPC_BOOK3E
418 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */
419 mtspr SPRN_SPRG_TLB_EXFRAME,r12
422 /* From now on, r24 is expected to be logical cpuid */
425 /* See if we need to call a cpu state restore handler */
426 LOAD_REG_ADDR(r23, cur_cpu_spec)
428 ld r12,CPU_SPEC_RESTORE(r23)
431 #ifdef PPC64_ELF_ABI_v1
437 3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */
445 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
448 beq 4b /* Loop until told to go */
450 sync /* order paca.run and cur_cpu_spec */
451 isync /* In case code patching happened */
453 /* Create a temp kernel stack for use before relocation is on. */
454 ld r1,PACAEMERGSP(r13)
455 subi r1,r1,STACK_FRAME_OVERHEAD
462 * Assumes we're mapped EA == RA if the MMU is on.
464 #ifdef CONFIG_PPC_BOOK3S
467 andi. r0,r3,MSR_IR|MSR_DR
475 b . /* prevent speculative execution */
480 * Here is our main kernel entry point. We support currently 2 kind of entries
481 * depending on the value of r5.
483 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
486 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
487 * DT block, r4 is a physical pointer to the kernel itself
490 __start_initialization_multiplatform:
491 /* Make sure we are running in 64 bits mode */
494 /* Get TOC pointer (current runtime address) */
497 /* find out where we are now */
499 0: mflr r26 /* r26 = runtime addr here */
500 addis r26,r26,(_stext - 0b)@ha
501 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
504 * Are we booted from a PROM Of-type client-interface ?
508 b __boot_from_prom /* yes -> prom */
510 /* Save parameters */
513 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
514 /* Save OPAL entry */
519 #ifdef CONFIG_PPC_BOOK3E
520 bl start_initialization_book3e
523 /* Setup some critical 970 SPRs before switching MMU off */
526 cmpwi r0,0x39 /* 970 */
528 cmpwi r0,0x3c /* 970FX */
530 cmpwi r0,0x44 /* 970MP */
532 cmpwi r0,0x45 /* 970GX */
534 1: bl __cpu_preinit_ppc970
537 /* Switch off MMU if not already off */
540 #endif /* CONFIG_PPC_BOOK3E */
543 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
544 /* Save parameters */
552 * Align the stack to 16-byte boundary
553 * Depending on the size and layout of the ELF sections in the initial
554 * boot binary, the stack pointer may be unaligned on PowerMac
558 #ifdef CONFIG_RELOCATABLE
559 /* Relocate code for where we are now */
564 /* Restore parameters */
571 /* Do all of the interaction with OF client interface */
574 #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */
576 /* We never return. We also hit that trap if trying to boot
577 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
581 #ifdef CONFIG_RELOCATABLE
582 /* process relocations for the final address of the kernel */
583 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */
585 #if defined(CONFIG_PPC_BOOK3E)
586 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
588 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
589 #if defined(CONFIG_PPC_BOOK3E)
592 cmplwi cr0,r7,1 /* flagged to stay where we are ? */
597 #if defined(CONFIG_PPC_BOOK3E)
598 /* IVPR needs to be set after relocation. */
604 * We need to run with _stext at physical address PHYSICAL_START.
605 * This will leave some code in the first 256B of
606 * real memory, which are reserved for software use.
608 * Note: This process overwrites the OF exception vectors.
610 li r3,0 /* target addr */
611 #ifdef CONFIG_PPC_BOOK3E
612 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */
614 mr. r4,r26 /* In some cases the loader may */
615 #if defined(CONFIG_PPC_BOOK3E)
618 beq 9f /* have already put us at zero */
619 li r6,0x100 /* Start offset, the first 0x100 */
620 /* bytes were copied earlier. */
622 #ifdef CONFIG_RELOCATABLE
624 * Check if the kernel has to be running as relocatable kernel based on the
625 * variable __run_at_load, if it is set the kernel is treated as relocatable
626 * kernel, otherwise it will be moved to PHYSICAL_START
628 #if defined(CONFIG_PPC_BOOK3E)
629 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
631 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
635 #ifdef CONFIG_PPC_BOOK3E
636 LOAD_REG_ADDR(r5, __end_interrupts)
637 LOAD_REG_ADDR(r11, _stext)
640 /* just copy interrupts */
641 LOAD_REG_IMMEDIATE(r5, FIXED_SYMBOL_ABS_ADDR(__end_interrupts))
646 /* # bytes of memory to copy */
647 lis r5,(ABS_ADDR(copy_to_here))@ha
648 addi r5,r5,(ABS_ADDR(copy_to_here))@l
650 bl copy_and_flush /* copy the first n bytes */
651 /* this includes the code being */
653 /* Jump to the copy of this code that we just made */
654 addis r8,r3,(ABS_ADDR(4f))@ha
655 addi r12,r8,(ABS_ADDR(4f))@l
660 p_end: .8byte _end - copy_to_here
664 * Now copy the rest of the kernel up to _end, add
665 * _end - copy_to_here to the copy limit and run again.
667 addis r8,r26,(ABS_ADDR(p_end))@ha
668 ld r8,(ABS_ADDR(p_end))@l(r8)
670 5: bl copy_and_flush /* copy the rest */
672 9: b start_here_multiplatform
675 * Copy routine used to copy the kernel to start at physical address 0
676 * and flush and invalidate the caches as needed.
677 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
678 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
680 * Note: this routine *only* clobbers r0, r6 and lr
682 _GLOBAL(copy_and_flush)
685 4: li r0,8 /* Use the smallest common */
686 /* denominator cache line */
687 /* size. This results in */
688 /* extra cache line flushes */
689 /* but operation is correct. */
690 /* Can't get cache line size */
691 /* from NACA as it is being */
694 mtctr r0 /* put # words/line in ctr */
695 3: addi r6,r6,8 /* copy a cache line */
699 dcbst r6,r3 /* write it to memory */
701 icbi r6,r3 /* flush the icache line */
714 #ifdef CONFIG_PPC_PMAC
716 * On PowerMac, secondary processors starts from the reset vector, which
717 * is temporarily turned into a call to one of the functions below.
722 .globl __secondary_start_pmac_0
723 __secondary_start_pmac_0:
724 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
734 _GLOBAL(pmac_secondary_start)
735 /* turn on 64-bit mode */
740 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
747 /* get TOC pointer (real address) */
751 /* Copy some CPU settings from CPU 0 */
752 bl __restore_cpu_ppc970
754 /* pSeries do that early though I don't think we really need it */
757 mtmsrd r3 /* RI on */
759 /* Set up a paca value for this processor. */
760 LOAD_REG_ADDR(r4,paca_ptrs) /* Load paca pointer */
761 ld r4,0(r4) /* Get base vaddr of paca_ptrs array */
762 sldi r5,r24,3 /* get paca_ptrs[] index from cpu id */
763 ldx r13,r5,r4 /* r13 = paca_ptrs[cpu id] */
764 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/
766 /* Mark interrupts soft and hard disabled (they might be enabled
767 * in the PACA when doing hotplug)
770 stb r0,PACAIRQSOFTMASK(r13)
771 li r0,PACA_IRQ_HARD_DIS
772 stb r0,PACAIRQHAPPENED(r13)
774 /* Create a temp kernel stack for use before relocation is on. */
775 ld r1,PACAEMERGSP(r13)
776 subi r1,r1,STACK_FRAME_OVERHEAD
780 #endif /* CONFIG_PPC_PMAC */
783 * This function is called after the master CPU has released the
784 * secondary processors. The execution environment is relocation off.
785 * The paca for this processor has the following fields initialized at
787 * 1. Processor number
788 * 2. Segment table pointer (virtual address)
789 * On entry the following are set:
790 * r1 = stack pointer (real addr of temp stack)
791 * r24 = cpu# (in Linux terms)
792 * r13 = paca virtual address
793 * SPRG_PACA = paca virtual address
798 .globl __secondary_start
800 /* Set thread priority to MEDIUM */
803 /* Initialize the kernel stack */
804 LOAD_REG_ADDR(r3, current_set)
805 sldi r28,r24,3 /* get current_set[cpu#] */
807 addi r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD
808 std r14,PACAKSAVE(r13)
810 /* Do early setup for that CPU (SLB and hash table pointer) */
811 bl early_setup_secondary
814 * setup the new stack pointer, but *don't* use this until
819 /* Clear backchain so we get nice backtraces */
823 /* Mark interrupts soft and hard disabled (they might be enabled
824 * in the PACA when doing hotplug)
827 stb r7,PACAIRQSOFTMASK(r13)
828 li r0,PACA_IRQ_HARD_DIS
829 stb r0,PACAIRQHAPPENED(r13)
831 /* enable MMU and jump to start_secondary */
832 LOAD_REG_ADDR(r3, start_secondary_prolog)
833 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
838 b . /* prevent speculative execution */
841 * Running with relocation on at this point. All we want to do is
842 * zero the stack back-chain pointer and get the TOC virtual address
843 * before going into C code.
845 start_secondary_prolog:
848 std r3,0(r1) /* Zero the stack frame pointer */
852 * Reset stack pointer and call start_secondary
853 * to continue with online operation when woken up
854 * from cede in cpu offline.
856 _GLOBAL(start_secondary_resume)
857 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */
859 std r3,0(r1) /* Zero the stack frame pointer */
865 * This subroutine clobbers r11 and r12
868 mfmsr r11 /* grab the current MSR */
869 #ifdef CONFIG_PPC_BOOK3E
870 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */
872 #else /* CONFIG_PPC_BOOK3E */
873 li r12,(MSR_64BIT | MSR_ISF)@highest
882 * This puts the TOC pointer into r2, offset by 0x8000 (as expected
883 * by the toolchain). It computes the correct value for wherever we
884 * are running at the moment, using position-independent code.
886 * Note: The compiler constructs pointers using offsets from the
887 * TOC in -mcmodel=medium mode. After we relocate to 0 but before
888 * the MMU is on we need our TOC to be a virtual address otherwise
889 * these pointers will be real addresses which may get stored and
890 * accessed later with the MMU on. We use tovirt() at the call
891 * sites to handle this.
893 _GLOBAL(relative_toc)
897 ld r2,(p_toc - 0b)(r11)
903 p_toc: .8byte __toc_start + 0x8000 - 0b
906 * This is where the main kernel code starts.
908 start_here_multiplatform:
913 /* Clear out the BSS. It may have been done in prom_init,
914 * already but that's irrelevant since prom_init will soon
915 * be detached from the kernel completely. Besides, we need
916 * to clear it now for kexec-style entry.
918 LOAD_REG_ADDR(r11,__bss_stop)
919 LOAD_REG_ADDR(r8,__bss_start)
920 sub r11,r11,r8 /* bss size */
921 addi r11,r11,7 /* round up to an even double word */
922 srdi. r11,r11,3 /* shift right by 3 */
926 mtctr r11 /* zero this many doublewords */
931 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
932 /* Setup OPAL entry */
933 LOAD_REG_ADDR(r11, opal)
938 #ifndef CONFIG_PPC_BOOK3E
941 mtmsrd r6 /* RI on */
944 #ifdef CONFIG_RELOCATABLE
945 /* Save the physical address we're running at in kernstart_addr */
946 LOAD_REG_ADDR(r4, kernstart_addr)
951 /* The following gets the stack set up with the regs */
952 /* pointing to the real addr of the kernel stack. This is */
953 /* all done to support the C function call below which sets */
954 /* up the htab. This is done because we have relocated the */
955 /* kernel but are still running in real mode. */
957 LOAD_REG_ADDR(r3,init_thread_union)
959 /* set up a stack pointer */
960 LOAD_REG_IMMEDIATE(r1,THREAD_SIZE)
963 stdu r0,-STACK_FRAME_OVERHEAD(r1)
966 * Do very early kernel initializations, including initial hash table
967 * and SLB setup before we turn on relocation.
970 /* Restore parameters passed from prom_init/kexec */
972 bl early_setup /* also sets r13 and SPRG_PACA */
974 LOAD_REG_ADDR(r3, start_here_common)
979 b . /* prevent speculative execution */
981 /* This is where all platforms converge execution */
984 /* relocation is on at this point */
985 std r1,PACAKSAVE(r13)
987 /* Load the TOC (virtual address) */
990 /* Mark interrupts soft and hard disabled (they might be enabled
991 * in the PACA when doing hotplug)
994 stb r0,PACAIRQSOFTMASK(r13)
995 li r0,PACA_IRQ_HARD_DIS
996 stb r0,PACAIRQHAPPENED(r13)
998 /* Generic kernel entry */
1005 * We put a few things here that have to be page-aligned.
1006 * This stuff goes at the beginning of the bss, which is page-aligned.
1010 * pgd dir should be aligned to PGD_TABLE_SIZE which is 64K.
1011 * We will need to find a better way to fix this
1015 .globl swapper_pg_dir
1017 .space PGD_TABLE_SIZE
1019 .globl empty_zero_page
1022 EXPORT_SYMBOL(empty_zero_page)