2 * This file contains idle entry/exit functions for POWER7,
3 * POWER8 and POWER9 CPUs.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
11 #include <linux/threads.h>
12 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/thread_info.h>
16 #include <asm/ppc_asm.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/ppc-opcode.h>
19 #include <asm/hw_irq.h>
20 #include <asm/kvm_book3s_asm.h>
22 #include <asm/cpuidle.h>
23 #include <asm/exception-64s.h>
24 #include <asm/book3s/64/mmu-hash.h>
30 * Use unused space in the interrupt stack to save and restore
31 * registers for winkle support.
44 #define PSSCR_EC_ESL_MASK_SHIFTED (PSSCR_EC | PSSCR_ESL) >> 16
49 * Used by threads before entering deep idle states. Saves SPRs
50 * in interrupt stack frame
54 * Note all register i.e per-core, per-subcore or per-thread is saved
55 * here since any thread in the core might wake up first
61 * Note - SDR1 is dropped in Power ISA v3. Hence not restoring
67 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
88 * Used by threads when the lock bit of core_idle_state is set.
89 * Threads will spin in HMT_LOW until the lock bit is cleared.
90 * r14 - pointer to core_idle_state
91 * r15 - used to load contents of core_idle_state
92 * r9 - used as a temporary variable
98 andis. r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
102 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
103 bne- core_idle_lock_held
107 * Pass requested state in r3:
108 * r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8
109 * - Requested STOP state in POWER9
111 * To check IRQ_HAPPENED in r4
115 * Address to 'rfid' to in r5
117 pnv_powersave_common:
118 /* Use r3 to pass state nap/sleep/winkle */
119 /* NAP is a state loss, we create a regs frame on the
120 * stack, fill it up with the state we care about and
121 * stick a pointer to it in PACAR1. We really only
122 * need to save PC, some CR bits and the NV GPRs,
123 * but for now an interrupt frame will do.
127 stdu r1,-INT_FRAME_SIZE(r1)
131 /* Hard disable interrupts */
135 mtmsrd r9,1 /* hard-disable interrupts */
137 /* Check if something happened while soft-disabled */
138 lbz r0,PACAIRQHAPPENED(r13)
139 andi. r0,r0,~PACA_IRQ_HARD_DIS@l
143 addi r1,r1,INT_FRAME_SIZE
145 li r3,0 /* Return 0 (no nap) */
149 1: /* We mark irqs hard disabled as this is the state we'll
150 * be in when returning and we need to tell arch_local_irq_restore()
153 li r0,PACA_IRQ_HARD_DIS
154 stb r0,PACAIRQHAPPENED(r13)
156 /* We haven't lost state ... yet */
158 stb r0,PACA_NAPSTATELOST(r13)
160 /* Continue saving state */
169 * Go to real mode to do the nap, as required by the architecture.
170 * Also, we need to be in real mode before setting hwthread_state,
171 * because as soon as we do that, another thread can switch
172 * the MMU context to the guest.
174 LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
177 mtmsrd r6, 1 /* clear RI before setting SRR0/1 */
182 .globl pnv_enter_arch207_idle_mode
183 pnv_enter_arch207_idle_mode:
184 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
185 /* Tell KVM we're entering idle */
186 li r4,KVM_HWTHREAD_IN_IDLE
187 /******************************************************/
188 /* N O T E W E L L ! ! ! N O T E W E L L */
189 /* The following store to HSTATE_HWTHREAD_STATE(r13) */
190 /* MUST occur in real mode, i.e. with the MMU off, */
191 /* and the MMU must stay off until we clear this flag */
192 /* and test HSTATE_HWTHREAD_REQ(r13) in */
193 /* pnv_powersave_wakeup in this file. */
194 /* The reason is that another thread can switch the */
195 /* MMU to a guest context whenever this flag is set */
196 /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */
197 /* that would potentially cause this thread to start */
198 /* executing instructions from guest memory in */
199 /* hypervisor mode, leading to a host crash or data */
200 /* corruption, or worse. */
201 /******************************************************/
202 stb r4,HSTATE_HWTHREAD_STATE(r13)
204 stb r3,PACA_THREAD_IDLE_STATE(r13)
205 cmpwi cr3,r3,PNV_THREAD_SLEEP
207 IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP)
210 /* Sleep or winkle */
211 lbz r7,PACA_THREAD_MASK(r13)
212 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
215 lis r5,PNV_CORE_IDLE_WINKLE_COUNT@h
220 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
221 bnel- core_idle_lock_held
223 add r15,r15,r5 /* Add if winkle */
224 andc r15,r15,r7 /* Clear thread bit */
226 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS
229 * If cr0 = 0, then current thread is the last thread of the core entering
230 * sleep. Last thread needs to execute the hardware bug workaround code if
231 * required by the platform.
232 * Make the workaround call unconditionally here. The below branch call is
233 * patched out when the idle states are discovered if the platform does not
236 .global pnv_fastsleep_workaround_at_entry
237 pnv_fastsleep_workaround_at_entry:
238 beq fastsleep_workaround_at_entry
244 common_enter: /* common code for all the threads entering sleep or winkle */
246 IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP)
248 fastsleep_workaround_at_entry:
249 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
254 /* Fast sleep workaround */
257 bl opal_config_cpu_idle_state
260 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
266 bl save_sprs_to_stack
268 IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
271 * r3 - PSSCR value corresponding to the requested stop state.
274 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
275 /* Tell KVM we're entering idle */
276 li r4,KVM_HWTHREAD_IN_IDLE
277 /* DO THIS IN REAL MODE! See comment above. */
278 stb r4,HSTATE_HWTHREAD_STATE(r13)
281 * Check if we are executing the lite variant with ESL=EC=0
283 andis. r4,r3,PSSCR_EC_ESL_MASK_SHIFTED
284 clrldi r3,r3,60 /* r3 = Bits[60:63] = Requested Level (RL) */
285 bne .Lhandle_esl_ec_set
286 IDLE_STATE_ENTER_SEQ(PPC_STOP)
287 li r3,0 /* Since we didn't lose state, return 0 */
292 * Check if the requested state is a deep idle state.
294 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
295 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
297 bge .Lhandle_deep_stop
298 IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP)
301 * Entering deep idle state.
302 * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to
303 * stack and enter stop
305 lbz r7,PACA_THREAD_MASK(r13)
306 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
310 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
311 bnel- core_idle_lock_held
312 andc r15,r15,r7 /* Clear thread bit */
318 bl save_sprs_to_stack
320 IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP)
323 /* Now check if user or arch enabled NAP mode */
324 LOAD_REG_ADDRBASE(r3,powersave_nap)
325 lwz r4,ADDROFF(powersave_nap)(r3)
334 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
335 b pnv_powersave_common
338 _GLOBAL(power7_sleep)
339 li r3,PNV_THREAD_SLEEP
341 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
342 b pnv_powersave_common
345 _GLOBAL(power7_winkle)
346 li r3,PNV_THREAD_WINKLE
348 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
349 b pnv_powersave_common
352 #define CHECK_HMI_INTERRUPT \
353 mfspr r0,SPRN_SRR1; \
354 BEGIN_FTR_SECTION_NESTED(66); \
355 rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \
356 FTR_SECTION_ELSE_NESTED(66); \
357 rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \
358 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
359 cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
361 /* Invoke opal call to handle hmi */ \
362 ld r2,PACATOC(r13); \
364 std r3,ORIG_GPR3(r1); /* Save original r3 */ \
365 li r3,0; /* NULL argument */ \
366 bl hmi_exception_realmode; \
368 ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
372 * r3 - The PSSCR value corresponding to the stop state.
373 * r4 - The PSSCR mask corrresonding to the stop state.
375 _GLOBAL(power9_idle_stop)
380 LOAD_REG_ADDR(r5,power_enter_stop)
382 b pnv_powersave_common
386 * On waking up from stop 0,1,2 with ESL=1 on POWER9 DD1,
387 * HSPRG0 will be set to the HSPRG0 value of one of the
388 * threads in this core. Thus the value we have in r13
389 * may not be this thread's paca pointer.
391 * Fortunately, the TIR remains invariant. Since this thread's
392 * paca pointer is recorded in all its sibling's paca, we can
393 * correctly recover this thread's paca pointer if we
394 * know the index of this thread in the core.
396 * This index can be obtained from the TIR.
398 * i.e, thread's position in the core = TIR.
399 * If this value is i, then this thread's paca is
400 * paca->thread_sibling_pacas[i].
402 power9_dd1_recover_paca:
405 * Since each entry in thread_sibling_pacas is 8 bytes
406 * we need to left-shift by 3 bits. Thus r4 = i * 8
409 /* Get &paca->thread_sibling_pacas[0] in r5 */
410 ld r5, PACA_SIBLING_PACA_PTRS(r13)
411 /* Load paca->thread_sibling_pacas[i] into r13 */
415 * Indicate that we have lost NVGPR state
416 * which needs to be restored from the stack.
419 stb r0,PACA_NAPSTATELOST(r13)
423 * Called from machine check handler for powersave wakeups.
424 * Low level machine check processing has already been done. Now just
425 * go through the wake up path to get everything in order.
427 * r3 - The original SRR1 value.
428 * Original SRR[01] have been clobbered.
431 .global pnv_powersave_wakeup_mce
432 pnv_powersave_wakeup_mce:
433 /* Set cr3 for pnv_powersave_wakeup */
434 rlwinm r11,r3,47-31,30,31
438 * Now put the original SRR1 with SRR1_WAKEMCE_RESVD as the wake
439 * reason into SRR1, which allows reuse of the system reset wakeup
440 * code without being mistaken for another type of wakeup.
442 oris r3,r3,SRR1_WAKEMCE_RESVD@h
445 b pnv_powersave_wakeup
448 * Called from reset vector for powersave wakeups.
449 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
451 .global pnv_powersave_wakeup
452 pnv_powersave_wakeup:
456 BEGIN_FTR_SECTION_NESTED(70)
457 bl power9_dd1_recover_paca
458 END_FTR_SECTION_NESTED_IFSET(CPU_FTR_POWER9_DD1, 70)
459 bl pnv_restore_hyp_resource_arch300
461 bl pnv_restore_hyp_resource_arch207
462 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
464 li r0,PNV_THREAD_RUNNING
465 stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */
467 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
468 li r0,KVM_HWTHREAD_IN_KERNEL
469 stb r0,HSTATE_HWTHREAD_STATE(r13)
470 /* Order setting hwthread_state vs. testing hwthread_req */
472 lbz r0,HSTATE_HWTHREAD_REQ(r13)
479 /* Return SRR1 from power7_nap() */
481 blt cr3,pnv_wakeup_noloss
485 * Check whether we have woken up with hypervisor state loss.
486 * If yes, restore hypervisor state and return back to link.
488 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
490 pnv_restore_hyp_resource_arch300:
492 * POWER ISA 3. Use PSSCR to determine if we
493 * are waking up from deep idle state
495 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
496 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
500 * 0-3 bits correspond to Power-Saving Level Status
501 * which indicates the idle state we are waking up from
505 bge cr4,pnv_wakeup_tb_loss /* returns to caller */
507 blr /* Waking up without hypervisor state loss. */
509 /* Same calling convention as arch300 */
510 pnv_restore_hyp_resource_arch207:
512 * POWER ISA 2.07 or less.
513 * Check if we slept with sleep or winkle.
515 lbz r4,PACA_THREAD_IDLE_STATE(r13)
516 cmpwi cr2,r4,PNV_THREAD_NAP
517 bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */
520 * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
521 * up from nap. At this stage CR3 shouldn't contains 'gt' since that
522 * indicates we are waking with hypervisor state loss from nap.
526 blr /* Waking up without hypervisor state loss */
529 * Called if waking up from idle state which can cause either partial or
530 * complete hyp state loss.
531 * In POWER8, called if waking up from fastsleep or winkle
532 * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state
535 * cr3 - gt if waking up with partial/complete hypervisor state loss
538 * cr4 - gt or eq if waking up from complete hypervisor state loss.
541 * r4 - PACA_THREAD_IDLE_STATE
546 * Before entering any idle state, the NVGPRs are saved in the stack.
547 * If there was a state loss, or PACA_NAPSTATELOST was set, then the
548 * NVGPRs are restored. If we are here, it is likely that state is lost,
549 * but not guaranteed -- neither ISA207 nor ISA300 tests to reach
550 * here are the same as the test to restore NVGPRS:
551 * PACA_THREAD_IDLE_STATE test for ISA207, PSSCR test for ISA300,
552 * and SRR1 test for restoring NVGPRs.
554 * We are about to clobber NVGPRs now, so set NAPSTATELOST to
555 * guarantee they will always be restored. This might be tightened
556 * with careful reading of specs (particularly for ISA300) but this
557 * is already a slow wakeup path and it's simpler to be safe.
560 stb r0,PACA_NAPSTATELOST(r13)
564 * Save SRR1 and LR in NVGPRs as they might be clobbered in
565 * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required
566 * to determine the wakeup reason if we branch to kvm_start_guest. LR
567 * is required to return back to reset vector after hypervisor state
568 * restore is complete.
575 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
577 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
578 lbz r7,PACA_THREAD_MASK(r13)
581 * Take the core lock to synchronize against other threads.
583 * Lock bit is set in one of the 2 cases-
584 * a. In the sleep/winkle enter path, the last thread is executing
585 * fastsleep workaround code.
586 * b. In the wake up path, another thread is executing fastsleep
587 * workaround undo code or resyncing timebase or restoring context
588 * In either case loop until the lock bit is cleared.
592 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
593 bnel- core_idle_lock_held
594 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
599 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS
604 * cr2 - eq if first thread to wakeup in core
605 * cr3- gt if waking up with partial/complete hypervisor state loss
607 * cr4 - gt or eq if waking up from complete hypervisor state loss.
613 * If yes, check if all threads were in winkle, decrement our
614 * winkle count, set all thread winkle bits if all were in winkle.
615 * Check if our thread has a winkle bit set, and set cr4 accordingly
616 * (to match ISA300, above). Pseudo-code for core idle state
617 * transitions for ISA207 is as follows (everything happens atomically
618 * due to store conditional and/or lock bit):
625 * core_idle_state &= ~thread_in_core
630 * bool first_in_core, first_in_subcore;
632 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
633 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
635 * core_idle_state |= thread_in_core;
640 * core_idle_state &= ~thread_in_core;
641 * core_idle_state += 1 << WINKLE_COUNT_SHIFT;
646 * bool first_in_core, first_in_subcore, winkle_state_lost;
648 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
649 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
651 * core_idle_state |= thread_in_core;
653 * if ((core_idle_state & WINKLE_MASK) == (8 << WINKLE_COUNT_SIHFT))
654 * core_idle_state |= THREAD_WINKLE_BITS;
655 * core_idle_state -= 1 << WINKLE_COUNT_SHIFT;
657 * winkle_state_lost = core_idle_state &
658 * (thread_in_core << WINKLE_THREAD_SHIFT);
659 * core_idle_state &= ~(thread_in_core << WINKLE_THREAD_SHIFT);
663 cmpwi r18,PNV_THREAD_WINKLE
665 andis. r9,r15,PNV_CORE_IDLE_WINKLE_COUNT_ALL_BIT@h
666 subis r15,r15,PNV_CORE_IDLE_WINKLE_COUNT@h
668 ori r15,r15,PNV_CORE_IDLE_THREAD_WINKLE_BITS /* all were winkle */
670 /* Shift thread bit to winkle mask, then test if this thread is set,
671 * and remove it from the winkle bits */
675 cmpwi cr4,r8,1 /* cr4 will be gt if our bit is set, lt if not */
677 lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
679 cmpwi r4,0 /* Check if first in subcore */
681 or r15,r15,r7 /* Set thread bit */
682 beq first_thread_in_subcore
683 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
685 or r15,r15,r7 /* Set thread bit */
686 beq cr2,first_thread_in_core
688 /* Not first thread in core or subcore to wake up */
691 first_thread_in_subcore:
693 * If waking up from sleep, subcore state is not lost. Hence
694 * skip subcore state restore
696 blt cr4,subcore_state_restored
698 /* Restore per-subcore state */
707 subcore_state_restored:
709 * Check if the thread is also the first thread in the core. If not,
710 * skip to clear_lock.
714 first_thread_in_core:
717 * First thread in the core waking up from any state which can cause
718 * partial or complete hypervisor state loss. It needs to
719 * call the fastsleep workaround code if the platform requires it.
720 * Call it unconditionally here. The below branch instruction will
721 * be patched out if the platform does not have fastsleep or does not
722 * require the workaround. Patching will be performed during the
723 * discovery of idle-states.
725 .global pnv_fastsleep_workaround_at_exit
726 pnv_fastsleep_workaround_at_exit:
727 b fastsleep_workaround_at_exit
731 * Use cr3 which indicates that we are waking up with atleast partial
732 * hypervisor state loss to determine if TIMEBASE RESYNC is needed.
735 /* Time base re-sync */
736 bl opal_resync_timebase;
738 * If waking up from sleep, per core state is not lost, skip to
744 * First thread in the core to wake up and its waking up with
745 * complete hypervisor state loss. Restore per core hypervisor
753 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
761 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
767 * Common to all threads.
769 * If waking up from sleep, hypervisor state is not lost. Hence
770 * skip hypervisor state restore.
772 blt cr4,hypervisor_state_restored
774 /* Waking up from winkle */
776 BEGIN_MMU_FTR_SECTION
778 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
779 /* Restore SLB from PACA */
780 ld r8,PACA_SLBSHADOWPTR(r13)
783 li r3, SLBSHADOW_SAVEAREA
787 andis. r7,r5,SLB_ESID_V@h
794 /* Restore per thread state */
805 /* Call cur_cpu_spec->cpu_restore() */
806 LOAD_REG_ADDR(r4, cur_cpu_spec)
808 ld r12,CPU_SPEC_RESTORE(r4)
809 #ifdef PPC64_ELF_ABI_v1
815 hypervisor_state_restored:
819 blr /* return to pnv_powersave_wakeup */
821 fastsleep_workaround_at_exit:
824 bl opal_config_cpu_idle_state
828 * R3 here contains the value that will be returned to the caller
831 .global pnv_wakeup_loss
836 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
842 addi r1,r1,INT_FRAME_SIZE
849 * R3 here contains the value that will be returned to the caller
853 lbz r0,PACA_NAPSTATELOST(r13)
858 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
863 addi r1,r1,INT_FRAME_SIZE