arch/powerpc/kernel/process.c

   1 /*
   2  *  Derived from "arch/i386/kernel/process.c"
   3  *    Copyright (C) 1995  Linus Torvalds
   4  *
   5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
   6  *  Paul Mackerras (paulus@cs.anu.edu.au)
   7  *
   8  *  PowerPC version
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/kernel.h>
  20 #include <linux/mm.h>
  21 #include <linux/smp.h>
  22 #include <linux/stddef.h>
  23 #include <linux/unistd.h>
  24 #include <linux/ptrace.h>
  25 #include <linux/slab.h>
  26 #include <linux/user.h>
  27 #include <linux/elf.h>
  28 #include <linux/prctl.h>
  29 #include <linux/init_task.h>
  30 #include <linux/export.h>
  31 #include <linux/kallsyms.h>
  32 #include <linux/mqueue.h>
  33 #include <linux/hardirq.h>
  34 #include <linux/utsname.h>
  35 #include <linux/ftrace.h>
  36 #include <linux/kernel_stat.h>
  37 #include <linux/personality.h>
  38 #include <linux/random.h>
  39 #include <linux/hw_breakpoint.h>
  40 #include <linux/uaccess.h>
  41 #include <linux/elf-randomize.h>
  42
  43 #include <asm/pgtable.h>
  44 #include <asm/io.h>
  45 #include <asm/processor.h>
  46 #include <asm/mmu.h>
  47 #include <asm/prom.h>
  48 #include <asm/machdep.h>
  49 #include <asm/time.h>
  50 #include <asm/runlatch.h>
  51 #include <asm/syscalls.h>
  52 #include <asm/switch_to.h>
  53 #include <asm/tm.h>
  54 #include <asm/debug.h>
  55 #ifdef CONFIG_PPC64
  56 #include <asm/firmware.h>
  57 #endif
  58 #include <asm/code-patching.h>
  59 #include <asm/exec.h>
  60 #include <asm/livepatch.h>
  61 #include <asm/cpu_has_feature.h>
  62 #include <asm/asm-prototypes.h>
  63
  64 #include <linux/kprobes.h>
  65 #include <linux/kdebug.h>
  66
  67 #ifdef CONFIG_CC_STACKPROTECTOR
  68 #include <linux/stackprotector.h>
  69 unsigned long __stack_chk_guard __read_mostly;
  70 EXPORT_SYMBOL(__stack_chk_guard);
  71 #endif
  72
  73 /* Transactional Memory debug */
  74 #ifdef TM_DEBUG_SW
  75 #define TM_DEBUG(x...) printk(KERN_INFO x)
  76 #else
  77 #define TM_DEBUG(x...) do { } while(0)
  78 #endif
  79
  80 extern unsigned long _get_SP(void);
  81
  82 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  83 static void check_if_tm_restore_required(struct task_struct *tsk)
  84 {
  85         /*
  86          * If we are saving the current thread's registers, and the
  87          * thread is in a transactional state, set the TIF_RESTORE_TM
  88          * bit so that we know to restore the registers before
  89          * returning to userspace.
  90          */
  91         if (tsk == current && tsk->thread.regs &&
  92             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
  93             !test_thread_flag(TIF_RESTORE_TM)) {
  94                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
  95                 set_thread_flag(TIF_RESTORE_TM);
  96         }
  97 }
  98
  99 static inline bool msr_tm_active(unsigned long msr)
 100 {
 101         return MSR_TM_ACTIVE(msr);
 102 }
 103 #else
 104 static inline bool msr_tm_active(unsigned long msr) { return false; }
 105 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
 106 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 107
 108 bool strict_msr_control;
 109 EXPORT_SYMBOL(strict_msr_control);
 110
 111 static int __init enable_strict_msr_control(char *str)
 112 {
 113         strict_msr_control = true;
 114         pr_info("Enabling strict facility control\n");
 115
 116         return 0;
 117 }
 118 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
 119
 120 unsigned long msr_check_and_set(unsigned long bits)
 121 {
 122         unsigned long oldmsr = mfmsr();
 123         unsigned long newmsr;
 124
 125         newmsr = oldmsr | bits;
 126
 127 #ifdef CONFIG_VSX
 128         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 129                 newmsr |= MSR_VSX;
 130 #endif
 131
 132         if (oldmsr != newmsr)
 133                 mtmsr_isync(newmsr);
 134
 135         return newmsr;
 136 }
 137
 138 void __msr_check_and_clear(unsigned long bits)
 139 {
 140         unsigned long oldmsr = mfmsr();
 141         unsigned long newmsr;
 142
 143         newmsr = oldmsr & ~bits;
 144
 145 #ifdef CONFIG_VSX
 146         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 147                 newmsr &= ~MSR_VSX;
 148 #endif
 149
 150         if (oldmsr != newmsr)
 151                 mtmsr_isync(newmsr);
 152 }
 153 EXPORT_SYMBOL(__msr_check_and_clear);
 154
 155 #ifdef CONFIG_PPC_FPU
 156 void __giveup_fpu(struct task_struct *tsk)
 157 {
 158         unsigned long msr;
 159
 160         save_fpu(tsk);
 161         msr = tsk->thread.regs->msr;
 162         msr &= ~MSR_FP;
 163 #ifdef CONFIG_VSX
 164         if (cpu_has_feature(CPU_FTR_VSX))
 165                 msr &= ~MSR_VSX;
 166 #endif
 167         tsk->thread.regs->msr = msr;
 168 }
 169
 170 void giveup_fpu(struct task_struct *tsk)
 171 {
 172         check_if_tm_restore_required(tsk);
 173
 174         msr_check_and_set(MSR_FP);
 175         __giveup_fpu(tsk);
 176         msr_check_and_clear(MSR_FP);
 177 }
 178 EXPORT_SYMBOL(giveup_fpu);
 179
 180 /*
 181  * Make sure the floating-point register state in the
 182  * the thread_struct is up to date for task tsk.
 183  */
 184 void flush_fp_to_thread(struct task_struct *tsk)
 185 {
 186         if (tsk->thread.regs) {
 187                 /*
 188                  * We need to disable preemption here because if we didn't,
 189                  * another process could get scheduled after the regs->msr
 190                  * test but before we have finished saving the FP registers
 191                  * to the thread_struct.  That process could take over the
 192                  * FPU, and then when we get scheduled again we would store
 193                  * bogus values for the remaining FP registers.
 194                  */
 195                 preempt_disable();
 196                 if (tsk->thread.regs->msr & MSR_FP) {
 197                         /*
 198                          * This should only ever be called for current or
 199                          * for a stopped child process.  Since we save away
 200                          * the FP register state on context switch,
 201                          * there is something wrong if a stopped child appears
 202                          * to still have its FP state in the CPU registers.
 203                          */
 204                         BUG_ON(tsk != current);
 205                         giveup_fpu(tsk);
 206                 }
 207                 preempt_enable();
 208         }
 209 }
 210 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
 211
 212 void enable_kernel_fp(void)
 213 {
 214         unsigned long cpumsr;
 215
 216         WARN_ON(preemptible());
 217
 218         cpumsr = msr_check_and_set(MSR_FP);
 219
 220         if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
 221                 check_if_tm_restore_required(current);
 222                 /*
 223                  * If a thread has already been reclaimed then the
 224                  * checkpointed registers are on the CPU but have definitely
 225                  * been saved by the reclaim code. Don't need to and *cannot*
 226                  * giveup as this would save  to the 'live' structure not the
 227                  * checkpointed structure.
 228                  */
 229                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 230                         return;
 231                 __giveup_fpu(current);
 232         }
 233 }
 234 EXPORT_SYMBOL(enable_kernel_fp);
 235
 236 static int restore_fp(struct task_struct *tsk) {
 237         if (tsk->thread.load_fp || msr_tm_active(tsk->thread.regs->msr)) {
 238                 load_fp_state(&current->thread.fp_state);
 239                 current->thread.load_fp++;
 240                 return 1;
 241         }
 242         return 0;
 243 }
 244 #else
 245 static int restore_fp(struct task_struct *tsk) { return 0; }
 246 #endif /* CONFIG_PPC_FPU */
 247
 248 #ifdef CONFIG_ALTIVEC
 249 #define loadvec(thr) ((thr).load_vec)
 250
 251 static void __giveup_altivec(struct task_struct *tsk)
 252 {
 253         unsigned long msr;
 254
 255         save_altivec(tsk);
 256         msr = tsk->thread.regs->msr;
 257         msr &= ~MSR_VEC;
 258 #ifdef CONFIG_VSX
 259         if (cpu_has_feature(CPU_FTR_VSX))
 260                 msr &= ~MSR_VSX;
 261 #endif
 262         tsk->thread.regs->msr = msr;
 263 }
 264
 265 void giveup_altivec(struct task_struct *tsk)
 266 {
 267         check_if_tm_restore_required(tsk);
 268
 269         msr_check_and_set(MSR_VEC);
 270         __giveup_altivec(tsk);
 271         msr_check_and_clear(MSR_VEC);
 272 }
 273 EXPORT_SYMBOL(giveup_altivec);
 274
 275 void enable_kernel_altivec(void)
 276 {
 277         unsigned long cpumsr;
 278
 279         WARN_ON(preemptible());
 280
 281         cpumsr = msr_check_and_set(MSR_VEC);
 282
 283         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
 284                 check_if_tm_restore_required(current);
 285                 /*
 286                  * If a thread has already been reclaimed then the
 287                  * checkpointed registers are on the CPU but have definitely
 288                  * been saved by the reclaim code. Don't need to and *cannot*
 289                  * giveup as this would save  to the 'live' structure not the
 290                  * checkpointed structure.
 291                  */
 292                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 293                         return;
 294                 __giveup_altivec(current);
 295         }
 296 }
 297 EXPORT_SYMBOL(enable_kernel_altivec);
 298
 299 /*
 300  * Make sure the VMX/Altivec register state in the
 301  * the thread_struct is up to date for task tsk.
 302  */
 303 void flush_altivec_to_thread(struct task_struct *tsk)
 304 {
 305         if (tsk->thread.regs) {
 306                 preempt_disable();
 307                 if (tsk->thread.regs->msr & MSR_VEC) {
 308                         BUG_ON(tsk != current);
 309                         giveup_altivec(tsk);
 310                 }
 311                 preempt_enable();
 312         }
 313 }
 314 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
 315
 316 static int restore_altivec(struct task_struct *tsk)
 317 {
 318         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
 319                 (tsk->thread.load_vec || msr_tm_active(tsk->thread.regs->msr))) {
 320                 load_vr_state(&tsk->thread.vr_state);
 321                 tsk->thread.used_vr = 1;
 322                 tsk->thread.load_vec++;
 323
 324                 return 1;
 325         }
 326         return 0;
 327 }
 328 #else
 329 #define loadvec(thr) 0
 330 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
 331 #endif /* CONFIG_ALTIVEC */
 332
 333 #ifdef CONFIG_VSX
 334 static void __giveup_vsx(struct task_struct *tsk)
 335 {
 336         if (tsk->thread.regs->msr & MSR_FP)
 337                 __giveup_fpu(tsk);
 338         if (tsk->thread.regs->msr & MSR_VEC)
 339                 __giveup_altivec(tsk);
 340         tsk->thread.regs->msr &= ~MSR_VSX;
 341 }
 342
 343 static void giveup_vsx(struct task_struct *tsk)
 344 {
 345         check_if_tm_restore_required(tsk);
 346
 347         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 348         __giveup_vsx(tsk);
 349         msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
 350 }
 351
 352 static void save_vsx(struct task_struct *tsk)
 353 {
 354         if (tsk->thread.regs->msr & MSR_FP)
 355                 save_fpu(tsk);
 356         if (tsk->thread.regs->msr & MSR_VEC)
 357                 save_altivec(tsk);
 358 }
 359
 360 void enable_kernel_vsx(void)
 361 {
 362         unsigned long cpumsr;
 363
 364         WARN_ON(preemptible());
 365
 366         cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 367
 368         if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) {
 369                 check_if_tm_restore_required(current);
 370                 /*
 371                  * If a thread has already been reclaimed then the
 372                  * checkpointed registers are on the CPU but have definitely
 373                  * been saved by the reclaim code. Don't need to and *cannot*
 374                  * giveup as this would save  to the 'live' structure not the
 375                  * checkpointed structure.
 376                  */
 377                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 378                         return;
 379                 if (current->thread.regs->msr & MSR_FP)
 380                         __giveup_fpu(current);
 381                 if (current->thread.regs->msr & MSR_VEC)
 382                         __giveup_altivec(current);
 383                 __giveup_vsx(current);
 384         }
 385 }
 386 EXPORT_SYMBOL(enable_kernel_vsx);
 387
 388 void flush_vsx_to_thread(struct task_struct *tsk)
 389 {
 390         if (tsk->thread.regs) {
 391                 preempt_disable();
 392                 if (tsk->thread.regs->msr & MSR_VSX) {
 393                         BUG_ON(tsk != current);
 394                         giveup_vsx(tsk);
 395                 }
 396                 preempt_enable();
 397         }
 398 }
 399 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
 400
 401 static int restore_vsx(struct task_struct *tsk)
 402 {
 403         if (cpu_has_feature(CPU_FTR_VSX)) {
 404                 tsk->thread.used_vsr = 1;
 405                 return 1;
 406         }
 407
 408         return 0;
 409 }
 410 #else
 411 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
 412 static inline void save_vsx(struct task_struct *tsk) { }
 413 #endif /* CONFIG_VSX */
 414
 415 #ifdef CONFIG_SPE
 416 void giveup_spe(struct task_struct *tsk)
 417 {
 418         check_if_tm_restore_required(tsk);
 419
 420         msr_check_and_set(MSR_SPE);
 421         __giveup_spe(tsk);
 422         msr_check_and_clear(MSR_SPE);
 423 }
 424 EXPORT_SYMBOL(giveup_spe);
 425
 426 void enable_kernel_spe(void)
 427 {
 428         WARN_ON(preemptible());
 429
 430         msr_check_and_set(MSR_SPE);
 431
 432         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
 433                 check_if_tm_restore_required(current);
 434                 __giveup_spe(current);
 435         }
 436 }
 437 EXPORT_SYMBOL(enable_kernel_spe);
 438
 439 void flush_spe_to_thread(struct task_struct *tsk)
 440 {
 441         if (tsk->thread.regs) {
 442                 preempt_disable();
 443                 if (tsk->thread.regs->msr & MSR_SPE) {
 444                         BUG_ON(tsk != current);
 445                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 446                         giveup_spe(tsk);
 447                 }
 448                 preempt_enable();
 449         }
 450 }
 451 #endif /* CONFIG_SPE */
 452
 453 static unsigned long msr_all_available;
 454
 455 static int __init init_msr_all_available(void)
 456 {
 457 #ifdef CONFIG_PPC_FPU
 458         msr_all_available |= MSR_FP;
 459 #endif
 460 #ifdef CONFIG_ALTIVEC
 461         if (cpu_has_feature(CPU_FTR_ALTIVEC))
 462                 msr_all_available |= MSR_VEC;
 463 #endif
 464 #ifdef CONFIG_VSX
 465         if (cpu_has_feature(CPU_FTR_VSX))
 466                 msr_all_available |= MSR_VSX;
 467 #endif
 468 #ifdef CONFIG_SPE
 469         if (cpu_has_feature(CPU_FTR_SPE))
 470                 msr_all_available |= MSR_SPE;
 471 #endif
 472
 473         return 0;
 474 }
 475 early_initcall(init_msr_all_available);
 476
 477 void giveup_all(struct task_struct *tsk)
 478 {
 479         unsigned long usermsr;
 480
 481         if (!tsk->thread.regs)
 482                 return;
 483
 484         usermsr = tsk->thread.regs->msr;
 485
 486         if ((usermsr & msr_all_available) == 0)
 487                 return;
 488
 489         msr_check_and_set(msr_all_available);
 490         check_if_tm_restore_required(tsk);
 491
 492 #ifdef CONFIG_PPC_FPU
 493         if (usermsr & MSR_FP)
 494                 __giveup_fpu(tsk);
 495 #endif
 496 #ifdef CONFIG_ALTIVEC
 497         if (usermsr & MSR_VEC)
 498                 __giveup_altivec(tsk);
 499 #endif
 500 #ifdef CONFIG_VSX
 501         if (usermsr & MSR_VSX)
 502                 __giveup_vsx(tsk);
 503 #endif
 504 #ifdef CONFIG_SPE
 505         if (usermsr & MSR_SPE)
 506                 __giveup_spe(tsk);
 507 #endif
 508
 509         msr_check_and_clear(msr_all_available);
 510 }
 511 EXPORT_SYMBOL(giveup_all);
 512
 513 void restore_math(struct pt_regs *regs)
 514 {
 515         unsigned long msr;
 516
 517         if (!msr_tm_active(regs->msr) &&
 518                 !current->thread.load_fp && !loadvec(current->thread))
 519                 return;
 520
 521         msr = regs->msr;
 522         msr_check_and_set(msr_all_available);
 523
 524         /*
 525          * Only reload if the bit is not set in the user MSR, the bit BEING set
 526          * indicates that the registers are hot
 527          */
 528         if ((!(msr & MSR_FP)) && restore_fp(current))
 529                 msr |= MSR_FP | current->thread.fpexc_mode;
 530
 531         if ((!(msr & MSR_VEC)) && restore_altivec(current))
 532                 msr |= MSR_VEC;
 533
 534         if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
 535                         restore_vsx(current)) {
 536                 msr |= MSR_VSX;
 537         }
 538
 539         msr_check_and_clear(msr_all_available);
 540
 541         regs->msr = msr;
 542 }
 543
 544 void save_all(struct task_struct *tsk)
 545 {
 546         unsigned long usermsr;
 547
 548         if (!tsk->thread.regs)
 549                 return;
 550
 551         usermsr = tsk->thread.regs->msr;
 552
 553         if ((usermsr & msr_all_available) == 0)
 554                 return;
 555
 556         msr_check_and_set(msr_all_available);
 557
 558         /*
 559          * Saving the way the register space is in hardware, save_vsx boils
 560          * down to a save_fpu() and save_altivec()
 561          */
 562         if (usermsr & MSR_VSX) {
 563                 save_vsx(tsk);
 564         } else {
 565                 if (usermsr & MSR_FP)
 566                         save_fpu(tsk);
 567
 568                 if (usermsr & MSR_VEC)
 569                         save_altivec(tsk);
 570         }
 571
 572         if (usermsr & MSR_SPE)
 573                 __giveup_spe(tsk);
 574
 575         msr_check_and_clear(msr_all_available);
 576 }
 577
 578 void flush_all_to_thread(struct task_struct *tsk)
 579 {
 580         if (tsk->thread.regs) {
 581                 preempt_disable();
 582                 BUG_ON(tsk != current);
 583                 save_all(tsk);
 584
 585 #ifdef CONFIG_SPE
 586                 if (tsk->thread.regs->msr & MSR_SPE)
 587                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 588 #endif
 589
 590                 preempt_enable();
 591         }
 592 }
 593 EXPORT_SYMBOL(flush_all_to_thread);
 594
 595 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 596 void do_send_trap(struct pt_regs *regs, unsigned long address,
 597                   unsigned long error_code, int signal_code, int breakpt)
 598 {
 599         siginfo_t info;
 600
 601         current->thread.trap_nr = signal_code;
 602         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 603                         11, SIGSEGV) == NOTIFY_STOP)
 604                 return;
 605
 606         /* Deliver the signal to userspace */
 607         info.si_signo = SIGTRAP;
 608         info.si_errno = breakpt;        /* breakpoint or watchpoint id */
 609         info.si_code = signal_code;
 610         info.si_addr = (void __user *)address;
 611         force_sig_info(SIGTRAP, &info, current);
 612 }
 613 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 614 void do_break (struct pt_regs *regs, unsigned long address,
 615                     unsigned long error_code)
 616 {
 617         siginfo_t info;
 618
 619         current->thread.trap_nr = TRAP_HWBKPT;
 620         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 621                         11, SIGSEGV) == NOTIFY_STOP)
 622                 return;
 623
 624         if (debugger_break_match(regs))
 625                 return;
 626
 627         /* Clear the breakpoint */
 628         hw_breakpoint_disable();
 629
 630         /* Deliver the signal to userspace */
 631         info.si_signo = SIGTRAP;
 632         info.si_errno = 0;
 633         info.si_code = TRAP_HWBKPT;
 634         info.si_addr = (void __user *)address;
 635         force_sig_info(SIGTRAP, &info, current);
 636 }
 637 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 638
 639 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
 640
 641 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 642 /*
 643  * Set the debug registers back to their default "safe" values.
 644  */
 645 static void set_debug_reg_defaults(struct thread_struct *thread)
 646 {
 647         thread->debug.iac1 = thread->debug.iac2 = 0;
 648 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 649         thread->debug.iac3 = thread->debug.iac4 = 0;
 650 #endif
 651         thread->debug.dac1 = thread->debug.dac2 = 0;
 652 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 653         thread->debug.dvc1 = thread->debug.dvc2 = 0;
 654 #endif
 655         thread->debug.dbcr0 = 0;
 656 #ifdef CONFIG_BOOKE
 657         /*
 658          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
 659          */
 660         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
 661                         DBCR1_IAC3US | DBCR1_IAC4US;
 662         /*
 663          * Force Data Address Compare User/Supervisor bits to be User-only
 664          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
 665          */
 666         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 667 #else
 668         thread->debug.dbcr1 = 0;
 669 #endif
 670 }
 671
 672 static void prime_debug_regs(struct debug_reg *debug)
 673 {
 674         /*
 675          * We could have inherited MSR_DE from userspace, since
 676          * it doesn't get cleared on exception entry.  Make sure
 677          * MSR_DE is clear before we enable any debug events.
 678          */
 679         mtmsr(mfmsr() & ~MSR_DE);
 680
 681         mtspr(SPRN_IAC1, debug->iac1);
 682         mtspr(SPRN_IAC2, debug->iac2);
 683 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 684         mtspr(SPRN_IAC3, debug->iac3);
 685         mtspr(SPRN_IAC4, debug->iac4);
 686 #endif
 687         mtspr(SPRN_DAC1, debug->dac1);
 688         mtspr(SPRN_DAC2, debug->dac2);
 689 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 690         mtspr(SPRN_DVC1, debug->dvc1);
 691         mtspr(SPRN_DVC2, debug->dvc2);
 692 #endif
 693         mtspr(SPRN_DBCR0, debug->dbcr0);
 694         mtspr(SPRN_DBCR1, debug->dbcr1);
 695 #ifdef CONFIG_BOOKE
 696         mtspr(SPRN_DBCR2, debug->dbcr2);
 697 #endif
 698 }
 699 /*
 700  * Unless neither the old or new thread are making use of the
 701  * debug registers, set the debug registers from the values
 702  * stored in the new thread.
 703  */
 704 void switch_booke_debug_regs(struct debug_reg *new_debug)
 705 {
 706         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
 707                 || (new_debug->dbcr0 & DBCR0_IDM))
 708                         prime_debug_regs(new_debug);
 709 }
 710 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
 711 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 712 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 713 static void set_debug_reg_defaults(struct thread_struct *thread)
 714 {
 715         thread->hw_brk.address = 0;
 716         thread->hw_brk.type = 0;
 717         set_breakpoint(&thread->hw_brk);
 718 }
 719 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 720 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 721
 722 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 723 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 724 {
 725         mtspr(SPRN_DAC1, dabr);
 726 #ifdef CONFIG_PPC_47x
 727         isync();
 728 #endif
 729         return 0;
 730 }
 731 #elif defined(CONFIG_PPC_BOOK3S)
 732 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 733 {
 734         mtspr(SPRN_DABR, dabr);
 735         if (cpu_has_feature(CPU_FTR_DABRX))
 736                 mtspr(SPRN_DABRX, dabrx);
 737         return 0;
 738 }
 739 #else
 740 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 741 {
 742         return -EINVAL;
 743 }
 744 #endif
 745
 746 static inline int set_dabr(struct arch_hw_breakpoint *brk)
 747 {
 748         unsigned long dabr, dabrx;
 749
 750         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
 751         dabrx = ((brk->type >> 3) & 0x7);
 752
 753         if (ppc_md.set_dabr)
 754                 return ppc_md.set_dabr(dabr, dabrx);
 755
 756         return __set_dabr(dabr, dabrx);
 757 }
 758
 759 static inline int set_dawr(struct arch_hw_breakpoint *brk)
 760 {
 761         unsigned long dawr, dawrx, mrd;
 762
 763         dawr = brk->address;
 764
 765         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
 766                                    << (63 - 58); //* read/write bits */
 767         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
 768                                    << (63 - 59); //* translate */
 769         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
 770                                    >> 3; //* PRIM bits */
 771         /* dawr length is stored in field MDR bits 48:53.  Matches range in
 772            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
 773            0b111111=64DW.
 774            brk->len is in bytes.
 775            This aligns up to double word size, shifts and does the bias.
 776         */
 777         mrd = ((brk->len + 7) >> 3) - 1;
 778         dawrx |= (mrd & 0x3f) << (63 - 53);
 779
 780         if (ppc_md.set_dawr)
 781                 return ppc_md.set_dawr(dawr, dawrx);
 782         mtspr(SPRN_DAWR, dawr);
 783         mtspr(SPRN_DAWRX, dawrx);
 784         return 0;
 785 }
 786
 787 void __set_breakpoint(struct arch_hw_breakpoint *brk)
 788 {
 789         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
 790
 791         if (cpu_has_feature(CPU_FTR_DAWR))
 792                 set_dawr(brk);
 793         else
 794                 set_dabr(brk);
 795 }
 796
 797 void set_breakpoint(struct arch_hw_breakpoint *brk)
 798 {
 799         preempt_disable();
 800         __set_breakpoint(brk);
 801         preempt_enable();
 802 }
 803
 804 #ifdef CONFIG_PPC64
 805 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
 806 #endif
 807
 808 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
 809                               struct arch_hw_breakpoint *b)
 810 {
 811         if (a->address != b->address)
 812                 return false;
 813         if (a->type != b->type)
 814                 return false;
 815         if (a->len != b->len)
 816                 return false;
 817         return true;
 818 }
 819
 820 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 821
 822 static inline bool tm_enabled(struct task_struct *tsk)
 823 {
 824         return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
 825 }
 826
 827 static void tm_reclaim_thread(struct thread_struct *thr,
 828                               struct thread_info *ti, uint8_t cause)
 829 {
 830         /*
 831          * Use the current MSR TM suspended bit to track if we have
 832          * checkpointed state outstanding.
 833          * On signal delivery, we'd normally reclaim the checkpointed
 834          * state to obtain stack pointer (see:get_tm_stackpointer()).
 835          * This will then directly return to userspace without going
 836          * through __switch_to(). However, if the stack frame is bad,
 837          * we need to exit this thread which calls __switch_to() which
 838          * will again attempt to reclaim the already saved tm state.
 839          * Hence we need to check that we've not already reclaimed
 840          * this state.
 841          * We do this using the current MSR, rather tracking it in
 842          * some specific thread_struct bit, as it has the additional
 843          * benefit of checking for a potential TM bad thing exception.
 844          */
 845         if (!MSR_TM_SUSPENDED(mfmsr()))
 846                 return;
 847
 848         giveup_all(container_of(thr, struct task_struct, thread));
 849
 850         tm_reclaim(thr, thr->ckpt_regs.msr, cause);
 851 }
 852
 853 void tm_reclaim_current(uint8_t cause)
 854 {
 855         tm_enable();
 856         tm_reclaim_thread(&current->thread, current_thread_info(), cause);
 857 }
 858
 859 static inline void tm_reclaim_task(struct task_struct *tsk)
 860 {
 861         /* We have to work out if we're switching from/to a task that's in the
 862          * middle of a transaction.
 863          *
 864          * In switching we need to maintain a 2nd register state as
 865          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
 866          * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
 867          * ckvr_state
 868          *
 869          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
 870          */
 871         struct thread_struct *thr = &tsk->thread;
 872
 873         if (!thr->regs)
 874                 return;
 875
 876         if (!MSR_TM_ACTIVE(thr->regs->msr))
 877                 goto out_and_saveregs;
 878
 879         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
 880                  "ccr=%lx, msr=%lx, trap=%lx)\n",
 881                  tsk->pid, thr->regs->nip,
 882                  thr->regs->ccr, thr->regs->msr,
 883                  thr->regs->trap);
 884
 885         tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
 886
 887         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
 888                  tsk->pid);
 889
 890 out_and_saveregs:
 891         /* Always save the regs here, even if a transaction's not active.
 892          * This context-switches a thread's TM info SPRs.  We do it here to
 893          * be consistent with the restore path (in recheckpoint) which
 894          * cannot happen later in _switch().
 895          */
 896         tm_save_sprs(thr);
 897 }
 898
 899 extern void __tm_recheckpoint(struct thread_struct *thread,
 900                               unsigned long orig_msr);
 901
 902 void tm_recheckpoint(struct thread_struct *thread,
 903                      unsigned long orig_msr)
 904 {
 905         unsigned long flags;
 906
 907         if (!(thread->regs->msr & MSR_TM))
 908                 return;
 909
 910         /* We really can't be interrupted here as the TEXASR registers can't
 911          * change and later in the trecheckpoint code, we have a userspace R1.
 912          * So let's hard disable over this region.
 913          */
 914         local_irq_save(flags);
 915         hard_irq_disable();
 916
 917         /* The TM SPRs are restored here, so that TEXASR.FS can be set
 918          * before the trecheckpoint and no explosion occurs.
 919          */
 920         tm_restore_sprs(thread);
 921
 922         __tm_recheckpoint(thread, orig_msr);
 923
 924         local_irq_restore(flags);
 925 }
 926
 927 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 928 {
 929         unsigned long msr;
 930
 931         if (!cpu_has_feature(CPU_FTR_TM))
 932                 return;
 933
 934         /* Recheckpoint the registers of the thread we're about to switch to.
 935          *
 936          * If the task was using FP, we non-lazily reload both the original and
 937          * the speculative FP register states.  This is because the kernel
 938          * doesn't see if/when a TM rollback occurs, so if we take an FP
 939          * unavailable later, we are unable to determine which set of FP regs
 940          * need to be restored.
 941          */
 942         if (!tm_enabled(new))
 943                 return;
 944
 945         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
 946                 tm_restore_sprs(&new->thread);
 947                 return;
 948         }
 949         msr = new->thread.ckpt_regs.msr;
 950         /* Recheckpoint to restore original checkpointed register state. */
 951         TM_DEBUG("*** tm_recheckpoint of pid %d "
 952                  "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
 953                  new->pid, new->thread.regs->msr, msr);
 954
 955         tm_recheckpoint(&new->thread, msr);
 956
 957         /*
 958          * The checkpointed state has been restored but the live state has
 959          * not, ensure all the math functionality is turned off to trigger
 960          * restore_math() to reload.
 961          */
 962         new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
 963
 964         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
 965                  "(kernel msr 0x%lx)\n",
 966                  new->pid, mfmsr());
 967 }
 968
 969 static inline void __switch_to_tm(struct task_struct *prev,
 970                 struct task_struct *new)
 971 {
 972         if (cpu_has_feature(CPU_FTR_TM)) {
 973                 if (tm_enabled(prev) || tm_enabled(new))
 974                         tm_enable();
 975
 976                 if (tm_enabled(prev)) {
 977                         prev->thread.load_tm++;
 978                         tm_reclaim_task(prev);
 979                         if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
 980                                 prev->thread.regs->msr &= ~MSR_TM;
 981                 }
 982
 983                 tm_recheckpoint_new_task(new);
 984         }
 985 }
 986
 987 /*
 988  * This is called if we are on the way out to userspace and the
 989  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
 990  * FP and/or vector state and does so if necessary.
 991  * If userspace is inside a transaction (whether active or
 992  * suspended) and FP/VMX/VSX instructions have ever been enabled
 993  * inside that transaction, then we have to keep them enabled
 994  * and keep the FP/VMX/VSX state loaded while ever the transaction
 995  * continues.  The reason is that if we didn't, and subsequently
 996  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
 997  * we don't know whether it's the same transaction, and thus we
 998  * don't know which of the checkpointed state and the transactional
 999  * state to use.
1000  */
1001 void restore_tm_state(struct pt_regs *regs)
1002 {
1003         unsigned long msr_diff;
1004
1005         /*
1006          * This is the only moment we should clear TIF_RESTORE_TM as
1007          * it is here that ckpt_regs.msr and pt_regs.msr become the same
1008          * again, anything else could lead to an incorrect ckpt_msr being
1009          * saved and therefore incorrect signal contexts.
1010          */
1011         clear_thread_flag(TIF_RESTORE_TM);
1012         if (!MSR_TM_ACTIVE(regs->msr))
1013                 return;
1014
1015         msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
1016         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
1017
1018         /* Ensure that restore_math() will restore */
1019         if (msr_diff & MSR_FP)
1020                 current->thread.load_fp = 1;
1021 #ifdef CONFIG_ALTIVEC
1022         if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1023                 current->thread.load_vec = 1;
1024 #endif
1025         restore_math(regs);
1026
1027         regs->msr |= msr_diff;
1028 }
1029
1030 #else
1031 #define tm_recheckpoint_new_task(new)
1032 #define __switch_to_tm(prev, new)
1033 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1034
1035 static inline void save_sprs(struct thread_struct *t)
1036 {
1037 #ifdef CONFIG_ALTIVEC
1038         if (cpu_has_feature(CPU_FTR_ALTIVEC))
1039                 t->vrsave = mfspr(SPRN_VRSAVE);
1040 #endif
1041 #ifdef CONFIG_PPC_BOOK3S_64
1042         if (cpu_has_feature(CPU_FTR_DSCR))
1043                 t->dscr = mfspr(SPRN_DSCR);
1044
1045         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1046                 t->bescr = mfspr(SPRN_BESCR);
1047                 t->ebbhr = mfspr(SPRN_EBBHR);
1048                 t->ebbrr = mfspr(SPRN_EBBRR);
1049
1050                 t->fscr = mfspr(SPRN_FSCR);
1051
1052                 /*
1053                  * Note that the TAR is not available for use in the kernel.
1054                  * (To provide this, the TAR should be backed up/restored on
1055                  * exception entry/exit instead, and be in pt_regs.  FIXME,
1056                  * this should be in pt_regs anyway (for debug).)
1057                  */
1058                 t->tar = mfspr(SPRN_TAR);
1059         }
1060 #endif
1061 }
1062
1063 static inline void restore_sprs(struct thread_struct *old_thread,
1064                                 struct thread_struct *new_thread)
1065 {
1066 #ifdef CONFIG_ALTIVEC
1067         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1068             old_thread->vrsave != new_thread->vrsave)
1069                 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1070 #endif
1071 #ifdef CONFIG_PPC_BOOK3S_64
1072         if (cpu_has_feature(CPU_FTR_DSCR)) {
1073                 u64 dscr = get_paca()->dscr_default;
1074                 if (new_thread->dscr_inherit)
1075                         dscr = new_thread->dscr;
1076
1077                 if (old_thread->dscr != dscr)
1078                         mtspr(SPRN_DSCR, dscr);
1079         }
1080
1081         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1082                 if (old_thread->bescr != new_thread->bescr)
1083                         mtspr(SPRN_BESCR, new_thread->bescr);
1084                 if (old_thread->ebbhr != new_thread->ebbhr)
1085                         mtspr(SPRN_EBBHR, new_thread->ebbhr);
1086                 if (old_thread->ebbrr != new_thread->ebbrr)
1087                         mtspr(SPRN_EBBRR, new_thread->ebbrr);
1088
1089                 if (old_thread->fscr != new_thread->fscr)
1090                         mtspr(SPRN_FSCR, new_thread->fscr);
1091
1092                 if (old_thread->tar != new_thread->tar)
1093                         mtspr(SPRN_TAR, new_thread->tar);
1094         }
1095 #endif
1096 }
1097
1098 struct task_struct *__switch_to(struct task_struct *prev,
1099         struct task_struct *new)
1100 {
1101         struct thread_struct *new_thread, *old_thread;
1102         struct task_struct *last;
1103 #ifdef CONFIG_PPC_BOOK3S_64
1104         struct ppc64_tlb_batch *batch;
1105 #endif
1106
1107         new_thread = &new->thread;
1108         old_thread = &current->thread;
1109
1110         WARN_ON(!irqs_disabled());
1111
1112 #ifdef CONFIG_PPC64
1113         /*
1114          * Collect processor utilization data per process
1115          */
1116         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
1117                 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
1118                 long unsigned start_tb, current_tb;
1119                 start_tb = old_thread->start_tb;
1120                 cu->current_tb = current_tb = mfspr(SPRN_PURR);
1121                 old_thread->accum_tb += (current_tb - start_tb);
1122                 new_thread->start_tb = current_tb;
1123         }
1124 #endif /* CONFIG_PPC64 */
1125
1126 #ifdef CONFIG_PPC_STD_MMU_64
1127         batch = this_cpu_ptr(&ppc64_tlb_batch);
1128         if (batch->active) {
1129                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1130                 if (batch->index)
1131                         __flush_tlb_pending(batch);
1132                 batch->active = 0;
1133         }
1134 #endif /* CONFIG_PPC_STD_MMU_64 */
1135
1136 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1137         switch_booke_debug_regs(&new->thread.debug);
1138 #else
1139 /*
1140  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1141  * schedule DABR
1142  */
1143 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1144         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
1145                 __set_breakpoint(&new->thread.hw_brk);
1146 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1147 #endif
1148
1149         /*
1150          * We need to save SPRs before treclaim/trecheckpoint as these will
1151          * change a number of them.
1152          */
1153         save_sprs(&prev->thread);
1154
1155         /* Save FPU, Altivec, VSX and SPE state */
1156         giveup_all(prev);
1157
1158         __switch_to_tm(prev, new);
1159
1160         /*
1161          * We can't take a PMU exception inside _switch() since there is a
1162          * window where the kernel stack SLB and the kernel stack are out
1163          * of sync. Hard disable here.
1164          */
1165         hard_irq_disable();
1166
1167         /*
1168          * Call restore_sprs() before calling _switch(). If we move it after
1169          * _switch() then we miss out on calling it for new tasks. The reason
1170          * for this is we manually create a stack frame for new tasks that
1171          * directly returns through ret_from_fork() or
1172          * ret_from_kernel_thread(). See copy_thread() for details.
1173          */
1174         restore_sprs(old_thread, new_thread);
1175
1176         last = _switch(old_thread, new_thread);
1177
1178 #ifdef CONFIG_PPC_STD_MMU_64
1179         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1180                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1181                 batch = this_cpu_ptr(&ppc64_tlb_batch);
1182                 batch->active = 1;
1183         }
1184
1185         if (current_thread_info()->task->thread.regs)
1186                 restore_math(current_thread_info()->task->thread.regs);
1187 #endif /* CONFIG_PPC_STD_MMU_64 */
1188
1189         return last;
1190 }
1191
1192 static int instructions_to_print = 16;
1193
1194 static void show_instructions(struct pt_regs *regs)
1195 {
1196         int i;
1197         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
1198                         sizeof(int));
1199
1200         printk("Instruction dump:");
1201
1202         for (i = 0; i < instructions_to_print; i++) {
1203                 int instr;
1204
1205                 if (!(i % 8))
1206                         pr_cont("\n");
1207
1208 #if !defined(CONFIG_BOOKE)
1209                 /* If executing with the IMMU off, adjust pc rather
1210                  * than print XXXXXXXX.
1211                  */
1212                 if (!(regs->msr & MSR_IR))
1213                         pc = (unsigned long)phys_to_virt(pc);
1214 #endif
1215
1216                 if (!__kernel_text_address(pc) ||
1217                      probe_kernel_address((unsigned int __user *)pc, instr)) {
1218                         pr_cont("XXXXXXXX ");
1219                 } else {
1220                         if (regs->nip == pc)
1221                                 pr_cont("<%08x> ", instr);
1222                         else
1223                                 pr_cont("%08x ", instr);
1224                 }
1225
1226                 pc += sizeof(int);
1227         }
1228
1229         pr_cont("\n");
1230 }
1231
1232 struct regbit {
1233         unsigned long bit;
1234         const char *name;
1235 };
1236
1237 static struct regbit msr_bits[] = {
1238 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1239         {MSR_SF,        "SF"},
1240         {MSR_HV,        "HV"},
1241 #endif
1242         {MSR_VEC,       "VEC"},
1243         {MSR_VSX,       "VSX"},
1244 #ifdef CONFIG_BOOKE
1245         {MSR_CE,        "CE"},
1246 #endif
1247         {MSR_EE,        "EE"},
1248         {MSR_PR,        "PR"},
1249         {MSR_FP,        "FP"},
1250         {MSR_ME,        "ME"},
1251 #ifdef CONFIG_BOOKE
1252         {MSR_DE,        "DE"},
1253 #else
1254         {MSR_SE,        "SE"},
1255         {MSR_BE,        "BE"},
1256 #endif
1257         {MSR_IR,        "IR"},
1258         {MSR_DR,        "DR"},
1259         {MSR_PMM,       "PMM"},
1260 #ifndef CONFIG_BOOKE
1261         {MSR_RI,        "RI"},
1262         {MSR_LE,        "LE"},
1263 #endif
1264         {0,             NULL}
1265 };
1266
1267 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1268 {
1269         const char *s = "";
1270
1271         for (; bits->bit; ++bits)
1272                 if (val & bits->bit) {
1273                         pr_cont("%s%s", s, bits->name);
1274                         s = sep;
1275                 }
1276 }
1277
1278 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1279 static struct regbit msr_tm_bits[] = {
1280         {MSR_TS_T,      "T"},
1281         {MSR_TS_S,      "S"},
1282         {MSR_TM,        "E"},
1283         {0,             NULL}
1284 };
1285
1286 static void print_tm_bits(unsigned long val)
1287 {
1288 /*
1289  * This only prints something if at least one of the TM bit is set.
1290  * Inside the TM[], the output means:
1291  *   E: Enabled         (bit 32)
1292  *   S: Suspended       (bit 33)
1293  *   T: Transactional   (bit 34)
1294  */
1295         if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1296                 pr_cont(",TM[");
1297                 print_bits(val, msr_tm_bits, "");
1298                 pr_cont("]");
1299         }
1300 }
1301 #else
1302 static void print_tm_bits(unsigned long val) {}
1303 #endif
1304
1305 static void print_msr_bits(unsigned long val)
1306 {
1307         pr_cont("<");
1308         print_bits(val, msr_bits, ",");
1309         print_tm_bits(val);
1310         pr_cont(">");
1311 }
1312
1313 #ifdef CONFIG_PPC64
1314 #define REG             "%016lx"
1315 #define REGS_PER_LINE   4
1316 #define LAST_VOLATILE   13
1317 #else
1318 #define REG             "%08lx"
1319 #define REGS_PER_LINE   8
1320 #define LAST_VOLATILE   12
1321 #endif
1322
1323 void show_regs(struct pt_regs * regs)
1324 {
1325         int i, trap;
1326
1327         show_regs_print_info(KERN_DEFAULT);
1328
1329         printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1330                regs->nip, regs->link, regs->ctr);
1331         printk("REGS: %p TRAP: %04lx   %s  (%s)\n",
1332                regs, regs->trap, print_tainted(), init_utsname()->release);
1333         printk("MSR: "REG" ", regs->msr);
1334         print_msr_bits(regs->msr);
1335         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1336         trap = TRAP(regs);
1337         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1338                 pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1339         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1340 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1341                 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1342 #else
1343                 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1344 #endif
1345 #ifdef CONFIG_PPC64
1346         pr_cont("SOFTE: %ld ", regs->softe);
1347 #endif
1348 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1349         if (MSR_TM_ACTIVE(regs->msr))
1350                 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1351 #endif
1352
1353         for (i = 0;  i < 32;  i++) {
1354                 if ((i % REGS_PER_LINE) == 0)
1355                         pr_cont("\nGPR%02d: ", i);
1356                 pr_cont(REG " ", regs->gpr[i]);
1357                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1358                         break;
1359         }
1360         pr_cont("\n");
1361 #ifdef CONFIG_KALLSYMS
1362         /*
1363          * Lookup NIP late so we have the best change of getting the
1364          * above info out without failing
1365          */
1366         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1367         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1368 #endif
1369         show_stack(current, (unsigned long *) regs->gpr[1]);
1370         if (!user_mode(regs))
1371                 show_instructions(regs);
1372 }
1373
1374 void flush_thread(void)
1375 {
1376 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1377         flush_ptrace_hw_breakpoint(current);
1378 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1379         set_debug_reg_defaults(&current->thread);
1380 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1381 }
1382
1383 void
1384 release_thread(struct task_struct *t)
1385 {
1386 }
1387
1388 /*
1389  * this gets called so that we can store coprocessor state into memory and
1390  * copy the current task into the new thread.
1391  */
1392 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1393 {
1394         flush_all_to_thread(src);
1395         /*
1396          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1397          * flush but it removes the checkpointed state from the current CPU and
1398          * transitions the CPU out of TM mode.  Hence we need to call
1399          * tm_recheckpoint_new_task() (on the same task) to restore the
1400          * checkpointed state back and the TM mode.
1401          *
1402          * Can't pass dst because it isn't ready. Doesn't matter, passing
1403          * dst is only important for __switch_to()
1404          */
1405         __switch_to_tm(src, src);
1406
1407         *dst = *src;
1408
1409         clear_task_ebb(dst);
1410
1411         return 0;
1412 }
1413
1414 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1415 {
1416 #ifdef CONFIG_PPC_STD_MMU_64
1417         unsigned long sp_vsid;
1418         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1419
1420         if (radix_enabled())
1421                 return;
1422
1423         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1424                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1425                         << SLB_VSID_SHIFT_1T;
1426         else
1427                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1428                         << SLB_VSID_SHIFT;
1429         sp_vsid |= SLB_VSID_KERNEL | llp;
1430         p->thread.ksp_vsid = sp_vsid;
1431 #endif
1432 }
1433
1434 /*
1435  * Copy a thread..
1436  */
1437
1438 /*
1439  * Copy architecture-specific thread state
1440  */
1441 int copy_thread(unsigned long clone_flags, unsigned long usp,
1442                 unsigned long kthread_arg, struct task_struct *p)
1443 {
1444         struct pt_regs *childregs, *kregs;
1445         extern void ret_from_fork(void);
1446         extern void ret_from_kernel_thread(void);
1447         void (*f)(void);
1448         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1449         struct thread_info *ti = task_thread_info(p);
1450
1451         klp_init_thread_info(ti);
1452
1453         /* Copy registers */
1454         sp -= sizeof(struct pt_regs);
1455         childregs = (struct pt_regs *) sp;
1456         if (unlikely(p->flags & PF_KTHREAD)) {
1457                 /* kernel thread */
1458                 memset(childregs, 0, sizeof(struct pt_regs));
1459                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1460                 /* function */
1461                 if (usp)
1462                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1463 #ifdef CONFIG_PPC64
1464                 clear_tsk_thread_flag(p, TIF_32BIT);
1465                 childregs->softe = 1;
1466 #endif
1467                 childregs->gpr[15] = kthread_arg;
1468                 p->thread.regs = NULL;  /* no user register state */
1469                 ti->flags |= _TIF_RESTOREALL;
1470                 f = ret_from_kernel_thread;
1471         } else {
1472                 /* user thread */
1473                 struct pt_regs *regs = current_pt_regs();
1474                 CHECK_FULL_REGS(regs);
1475                 *childregs = *regs;
1476                 if (usp)
1477                         childregs->gpr[1] = usp;
1478                 p->thread.regs = childregs;
1479                 childregs->gpr[3] = 0;  /* Result from fork() */
1480                 if (clone_flags & CLONE_SETTLS) {
1481 #ifdef CONFIG_PPC64
1482                         if (!is_32bit_task())
1483                                 childregs->gpr[13] = childregs->gpr[6];
1484                         else
1485 #endif
1486                                 childregs->gpr[2] = childregs->gpr[6];
1487                 }
1488
1489                 f = ret_from_fork;
1490         }
1491         childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1492         sp -= STACK_FRAME_OVERHEAD;
1493
1494         /*
1495          * The way this works is that at some point in the future
1496          * some task will call _switch to switch to the new task.
1497          * That will pop off the stack frame created below and start
1498          * the new task running at ret_from_fork.  The new task will
1499          * do some house keeping and then return from the fork or clone
1500          * system call, using the stack frame created above.
1501          */
1502         ((unsigned long *)sp)[0] = 0;
1503         sp -= sizeof(struct pt_regs);
1504         kregs = (struct pt_regs *) sp;
1505         sp -= STACK_FRAME_OVERHEAD;
1506         p->thread.ksp = sp;
1507 #ifdef CONFIG_PPC32
1508         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1509                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1510 #endif
1511 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1512         p->thread.ptrace_bps[0] = NULL;
1513 #endif
1514
1515         p->thread.fp_save_area = NULL;
1516 #ifdef CONFIG_ALTIVEC
1517         p->thread.vr_save_area = NULL;
1518 #endif
1519
1520         setup_ksp_vsid(p, sp);
1521
1522 #ifdef CONFIG_PPC64
1523         if (cpu_has_feature(CPU_FTR_DSCR)) {
1524                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1525                 p->thread.dscr = mfspr(SPRN_DSCR);
1526         }
1527         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1528                 p->thread.ppr = INIT_PPR;
1529 #endif
1530         kregs->nip = ppc_function_entry(f);
1531         return 0;
1532 }
1533
1534 /*
1535  * Set up a thread for executing a new program
1536  */
1537 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1538 {
1539 #ifdef CONFIG_PPC64
1540         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1541 #endif
1542
1543         /*
1544          * If we exec out of a kernel thread then thread.regs will not be
1545          * set.  Do it now.
1546          */
1547         if (!current->thread.regs) {
1548                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1549                 current->thread.regs = regs - 1;
1550         }
1551
1552 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1553         /*
1554          * Clear any transactional state, we're exec()ing. The cause is
1555          * not important as there will never be a recheckpoint so it's not
1556          * user visible.
1557          */
1558         if (MSR_TM_SUSPENDED(mfmsr()))
1559                 tm_reclaim_current(0);
1560 #endif
1561
1562         memset(regs->gpr, 0, sizeof(regs->gpr));
1563         regs->ctr = 0;
1564         regs->link = 0;
1565         regs->xer = 0;
1566         regs->ccr = 0;
1567         regs->gpr[1] = sp;
1568
1569         /*
1570          * We have just cleared all the nonvolatile GPRs, so make
1571          * FULL_REGS(regs) return true.  This is necessary to allow
1572          * ptrace to examine the thread immediately after exec.
1573          */
1574         regs->trap &= ~1UL;
1575
1576 #ifdef CONFIG_PPC32
1577         regs->mq = 0;
1578         regs->nip = start;
1579         regs->msr = MSR_USER;
1580 #else
1581         if (!is_32bit_task()) {
1582                 unsigned long entry;
1583
1584                 if (is_elf2_task()) {
1585                         /* Look ma, no function descriptors! */
1586                         entry = start;
1587
1588                         /*
1589                          * Ulrich says:
1590                          *   The latest iteration of the ABI requires that when
1591                          *   calling a function (at its global entry point),
1592                          *   the caller must ensure r12 holds the entry point
1593                          *   address (so that the function can quickly
1594                          *   establish addressability).
1595                          */
1596                         regs->gpr[12] = start;
1597                         /* Make sure that's restored on entry to userspace. */
1598                         set_thread_flag(TIF_RESTOREALL);
1599                 } else {
1600                         unsigned long toc;
1601
1602                         /* start is a relocated pointer to the function
1603                          * descriptor for the elf _start routine.  The first
1604                          * entry in the function descriptor is the entry
1605                          * address of _start and the second entry is the TOC
1606                          * value we need to use.
1607                          */
1608                         __get_user(entry, (unsigned long __user *)start);
1609                         __get_user(toc, (unsigned long __user *)start+1);
1610
1611                         /* Check whether the e_entry function descriptor entries
1612                          * need to be relocated before we can use them.
1613                          */
1614                         if (load_addr != 0) {
1615                                 entry += load_addr;
1616                                 toc   += load_addr;
1617                         }
1618                         regs->gpr[2] = toc;
1619                 }
1620                 regs->nip = entry;
1621                 regs->msr = MSR_USER64;
1622         } else {
1623                 regs->nip = start;
1624                 regs->gpr[2] = 0;
1625                 regs->msr = MSR_USER32;
1626         }
1627 #endif
1628 #ifdef CONFIG_VSX
1629         current->thread.used_vsr = 0;
1630 #endif
1631         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1632         current->thread.fp_save_area = NULL;
1633 #ifdef CONFIG_ALTIVEC
1634         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1635         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1636         current->thread.vr_save_area = NULL;
1637         current->thread.vrsave = 0;
1638         current->thread.used_vr = 0;
1639 #endif /* CONFIG_ALTIVEC */
1640 #ifdef CONFIG_SPE
1641         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1642         current->thread.acc = 0;
1643         current->thread.spefscr = 0;
1644         current->thread.used_spe = 0;
1645 #endif /* CONFIG_SPE */
1646 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1647         current->thread.tm_tfhar = 0;
1648         current->thread.tm_texasr = 0;
1649         current->thread.tm_tfiar = 0;
1650 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1651 }
1652 EXPORT_SYMBOL(start_thread);
1653
1654 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1655                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1656
1657 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1658 {
1659         struct pt_regs *regs = tsk->thread.regs;
1660
1661         /* This is a bit hairy.  If we are an SPE enabled  processor
1662          * (have embedded fp) we store the IEEE exception enable flags in
1663          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1664          * mode (asyn, precise, disabled) for 'Classic' FP. */
1665         if (val & PR_FP_EXC_SW_ENABLE) {
1666 #ifdef CONFIG_SPE
1667                 if (cpu_has_feature(CPU_FTR_SPE)) {
1668                         /*
1669                          * When the sticky exception bits are set
1670                          * directly by userspace, it must call prctl
1671                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1672                          * in the existing prctl settings) or
1673                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1674                          * the bits being set).  <fenv.h> functions
1675                          * saving and restoring the whole
1676                          * floating-point environment need to do so
1677                          * anyway to restore the prctl settings from
1678                          * the saved environment.
1679                          */
1680                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1681                         tsk->thread.fpexc_mode = val &
1682                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1683                         return 0;
1684                 } else {
1685                         return -EINVAL;
1686                 }
1687 #else
1688                 return -EINVAL;
1689 #endif
1690         }
1691
1692         /* on a CONFIG_SPE this does not hurt us.  The bits that
1693          * __pack_fe01 use do not overlap with bits used for
1694          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1695          * on CONFIG_SPE implementations are reserved so writing to
1696          * them does not change anything */
1697         if (val > PR_FP_EXC_PRECISE)
1698                 return -EINVAL;
1699         tsk->thread.fpexc_mode = __pack_fe01(val);
1700         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1701                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1702                         | tsk->thread.fpexc_mode;
1703         return 0;
1704 }
1705
1706 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1707 {
1708         unsigned int val;
1709
1710         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1711 #ifdef CONFIG_SPE
1712                 if (cpu_has_feature(CPU_FTR_SPE)) {
1713                         /*
1714                          * When the sticky exception bits are set
1715                          * directly by userspace, it must call prctl
1716                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1717                          * in the existing prctl settings) or
1718                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1719                          * the bits being set).  <fenv.h> functions
1720                          * saving and restoring the whole
1721                          * floating-point environment need to do so
1722                          * anyway to restore the prctl settings from
1723                          * the saved environment.
1724                          */
1725                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1726                         val = tsk->thread.fpexc_mode;
1727                 } else
1728                         return -EINVAL;
1729 #else
1730                 return -EINVAL;
1731 #endif
1732         else
1733                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1734         return put_user(val, (unsigned int __user *) adr);
1735 }
1736
1737 int set_endian(struct task_struct *tsk, unsigned int val)
1738 {
1739         struct pt_regs *regs = tsk->thread.regs;
1740
1741         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1742             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1743                 return -EINVAL;
1744
1745         if (regs == NULL)
1746                 return -EINVAL;
1747
1748         if (val == PR_ENDIAN_BIG)
1749                 regs->msr &= ~MSR_LE;
1750         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1751                 regs->msr |= MSR_LE;
1752         else
1753                 return -EINVAL;
1754
1755         return 0;
1756 }
1757
1758 int get_endian(struct task_struct *tsk, unsigned long adr)
1759 {
1760         struct pt_regs *regs = tsk->thread.regs;
1761         unsigned int val;
1762
1763         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1764             !cpu_has_feature(CPU_FTR_REAL_LE))
1765                 return -EINVAL;
1766
1767         if (regs == NULL)
1768                 return -EINVAL;
1769
1770         if (regs->msr & MSR_LE) {
1771                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1772                         val = PR_ENDIAN_LITTLE;
1773                 else
1774                         val = PR_ENDIAN_PPC_LITTLE;
1775         } else
1776                 val = PR_ENDIAN_BIG;
1777
1778         return put_user(val, (unsigned int __user *)adr);
1779 }
1780
1781 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1782 {
1783         tsk->thread.align_ctl = val;
1784         return 0;
1785 }
1786
1787 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1788 {
1789         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1790 }
1791
1792 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1793                                   unsigned long nbytes)
1794 {
1795         unsigned long stack_page;
1796         unsigned long cpu = task_cpu(p);
1797
1798         /*
1799          * Avoid crashing if the stack has overflowed and corrupted
1800          * task_cpu(p), which is in the thread_info struct.
1801          */
1802         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1803                 stack_page = (unsigned long) hardirq_ctx[cpu];
1804                 if (sp >= stack_page + sizeof(struct thread_struct)
1805                     && sp <= stack_page + THREAD_SIZE - nbytes)
1806                         return 1;
1807
1808                 stack_page = (unsigned long) softirq_ctx[cpu];
1809                 if (sp >= stack_page + sizeof(struct thread_struct)
1810                     && sp <= stack_page + THREAD_SIZE - nbytes)
1811                         return 1;
1812         }
1813         return 0;
1814 }
1815
1816 int validate_sp(unsigned long sp, struct task_struct *p,
1817                        unsigned long nbytes)
1818 {
1819         unsigned long stack_page = (unsigned long)task_stack_page(p);
1820
1821         if (sp >= stack_page + sizeof(struct thread_struct)
1822             && sp <= stack_page + THREAD_SIZE - nbytes)
1823                 return 1;
1824
1825         return valid_irq_stack(sp, p, nbytes);
1826 }
1827
1828 EXPORT_SYMBOL(validate_sp);
1829
1830 unsigned long get_wchan(struct task_struct *p)
1831 {
1832         unsigned long ip, sp;
1833         int count = 0;
1834
1835         if (!p || p == current || p->state == TASK_RUNNING)
1836                 return 0;
1837
1838         sp = p->thread.ksp;
1839         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1840                 return 0;
1841
1842         do {
1843                 sp = *(unsigned long *)sp;
1844                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1845                         return 0;
1846                 if (count > 0) {
1847                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1848                         if (!in_sched_functions(ip))
1849                                 return ip;
1850                 }
1851         } while (count++ < 16);
1852         return 0;
1853 }
1854
1855 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1856
1857 void show_stack(struct task_struct *tsk, unsigned long *stack)
1858 {
1859         unsigned long sp, ip, lr, newsp;
1860         int count = 0;
1861         int firstframe = 1;
1862 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1863         int curr_frame = current->curr_ret_stack;
1864         extern void return_to_handler(void);
1865         unsigned long rth = (unsigned long)return_to_handler;
1866 #endif
1867
1868         sp = (unsigned long) stack;
1869         if (tsk == NULL)
1870                 tsk = current;
1871         if (sp == 0) {
1872                 if (tsk == current)
1873                         sp = current_stack_pointer();
1874                 else
1875                         sp = tsk->thread.ksp;
1876         }
1877
1878         lr = 0;
1879         printk("Call Trace:\n");
1880         do {
1881                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1882                         return;
1883
1884                 stack = (unsigned long *) sp;
1885                 newsp = stack[0];
1886                 ip = stack[STACK_FRAME_LR_SAVE];
1887                 if (!firstframe || ip != lr) {
1888                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1889 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1890                         if ((ip == rth) && curr_frame >= 0) {
1891                                 pr_cont(" (%pS)",
1892                                        (void *)current->ret_stack[curr_frame].ret);
1893                                 curr_frame--;
1894                         }
1895 #endif
1896                         if (firstframe)
1897                                 pr_cont(" (unreliable)");
1898                         pr_cont("\n");
1899                 }
1900                 firstframe = 0;
1901
1902                 /*
1903                  * See if this is an exception frame.
1904                  * We look for the "regshere" marker in the current frame.
1905                  */
1906                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1907                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1908                         struct pt_regs *regs = (struct pt_regs *)
1909                                 (sp + STACK_FRAME_OVERHEAD);
1910                         lr = regs->link;
1911                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
1912                                regs->trap, (void *)regs->nip, (void *)lr);
1913                         firstframe = 1;
1914                 }
1915
1916                 sp = newsp;
1917         } while (count++ < kstack_depth_to_print);
1918 }
1919
1920 #ifdef CONFIG_PPC64
1921 /* Called with hard IRQs off */
1922 void notrace __ppc64_runlatch_on(void)
1923 {
1924         struct thread_info *ti = current_thread_info();
1925         unsigned long ctrl;
1926
1927         ctrl = mfspr(SPRN_CTRLF);
1928         ctrl |= CTRL_RUNLATCH;
1929         mtspr(SPRN_CTRLT, ctrl);
1930
1931         ti->local_flags |= _TLF_RUNLATCH;
1932 }
1933
1934 /* Called with hard IRQs off */
1935 void notrace __ppc64_runlatch_off(void)
1936 {
1937         struct thread_info *ti = current_thread_info();
1938         unsigned long ctrl;
1939
1940         ti->local_flags &= ~_TLF_RUNLATCH;
1941
1942         ctrl = mfspr(SPRN_CTRLF);
1943         ctrl &= ~CTRL_RUNLATCH;
1944         mtspr(SPRN_CTRLT, ctrl);
1945 }
1946 #endif /* CONFIG_PPC64 */
1947
1948 unsigned long arch_align_stack(unsigned long sp)
1949 {
1950         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1951                 sp -= get_random_int() & ~PAGE_MASK;
1952         return sp & ~0xf;
1953 }
1954
1955 static inline unsigned long brk_rnd(void)
1956 {
1957         unsigned long rnd = 0;
1958
1959         /* 8MB for 32bit, 1GB for 64bit */
1960         if (is_32bit_task())
1961                 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
1962         else
1963                 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
1964
1965         return rnd << PAGE_SHIFT;
1966 }
1967
1968 unsigned long arch_randomize_brk(struct mm_struct *mm)
1969 {
1970         unsigned long base = mm->brk;
1971         unsigned long ret;
1972
1973 #ifdef CONFIG_PPC_STD_MMU_64
1974         /*
1975          * If we are using 1TB segments and we are allowed to randomise
1976          * the heap, we can put it above 1TB so it is backed by a 1TB
1977          * segment. Otherwise the heap will be in the bottom 1TB
1978          * which always uses 256MB segments and this may result in a
1979          * performance penalty. We don't need to worry about radix. For
1980          * radix, mmu_highuser_ssize remains unchanged from 256MB.
1981          */
1982         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1983                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
1984 #endif
1985
1986         ret = PAGE_ALIGN(base + brk_rnd());
1987
1988         if (ret < mm->brk)
1989                 return mm->brk;
1990
1991         return ret;
1992 }
1993