arch/powerpc/kernel/process.c

   1 /*
   2  *  Derived from "arch/i386/kernel/process.c"
   3  *    Copyright (C) 1995  Linus Torvalds
   4  *
   5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
   6  *  Paul Mackerras (paulus@cs.anu.edu.au)
   7  *
   8  *  PowerPC version
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/sched/debug.h>
  20 #include <linux/sched/task.h>
  21 #include <linux/sched/task_stack.h>
  22 #include <linux/kernel.h>
  23 #include <linux/mm.h>
  24 #include <linux/smp.h>
  25 #include <linux/stddef.h>
  26 #include <linux/unistd.h>
  27 #include <linux/ptrace.h>
  28 #include <linux/slab.h>
  29 #include <linux/user.h>
  30 #include <linux/elf.h>
  31 #include <linux/prctl.h>
  32 #include <linux/init_task.h>
  33 #include <linux/export.h>
  34 #include <linux/kallsyms.h>
  35 #include <linux/mqueue.h>
  36 #include <linux/hardirq.h>
  37 #include <linux/utsname.h>
  38 #include <linux/ftrace.h>
  39 #include <linux/kernel_stat.h>
  40 #include <linux/personality.h>
  41 #include <linux/random.h>
  42 #include <linux/hw_breakpoint.h>
  43 #include <linux/uaccess.h>
  44 #include <linux/elf-randomize.h>
  45 #include <linux/pkeys.h>
  46
  47 #include <asm/pgtable.h>
  48 #include <asm/io.h>
  49 #include <asm/processor.h>
  50 #include <asm/mmu.h>
  51 #include <asm/prom.h>
  52 #include <asm/machdep.h>
  53 #include <asm/time.h>
  54 #include <asm/runlatch.h>
  55 #include <asm/syscalls.h>
  56 #include <asm/switch_to.h>
  57 #include <asm/tm.h>
  58 #include <asm/debug.h>
  59 #ifdef CONFIG_PPC64
  60 #include <asm/firmware.h>
  61 #include <asm/hw_irq.h>
  62 #endif
  63 #include <asm/code-patching.h>
  64 #include <asm/exec.h>
  65 #include <asm/livepatch.h>
  66 #include <asm/cpu_has_feature.h>
  67 #include <asm/asm-prototypes.h>
  68 #include <asm/stacktrace.h>
  69
  70 #include <linux/kprobes.h>
  71 #include <linux/kdebug.h>
  72
  73 /* Transactional Memory debug */
  74 #ifdef TM_DEBUG_SW
  75 #define TM_DEBUG(x...) printk(KERN_INFO x)
  76 #else
  77 #define TM_DEBUG(x...) do { } while(0)
  78 #endif
  79
  80 extern unsigned long _get_SP(void);
  81
  82 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  83 /*
  84  * Are we running in "Suspend disabled" mode? If so we have to block any
  85  * sigreturn that would get us into suspended state, and we also warn in some
  86  * other paths that we should never reach with suspend disabled.
  87  */
  88 bool tm_suspend_disabled __ro_after_init = false;
  89
  90 static void check_if_tm_restore_required(struct task_struct *tsk)
  91 {
  92         /*
  93          * If we are saving the current thread's registers, and the
  94          * thread is in a transactional state, set the TIF_RESTORE_TM
  95          * bit so that we know to restore the registers before
  96          * returning to userspace.
  97          */
  98         if (tsk == current && tsk->thread.regs &&
  99             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
 100             !test_thread_flag(TIF_RESTORE_TM)) {
 101                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
 102                 set_thread_flag(TIF_RESTORE_TM);
 103         }
 104 }
 105
 106 static bool tm_active_with_fp(struct task_struct *tsk)
 107 {
 108         return MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
 109                 (tsk->thread.ckpt_regs.msr & MSR_FP);
 110 }
 111
 112 static bool tm_active_with_altivec(struct task_struct *tsk)
 113 {
 114         return MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
 115                 (tsk->thread.ckpt_regs.msr & MSR_VEC);
 116 }
 117 #else
 118 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
 119 static inline bool tm_active_with_fp(struct task_struct *tsk) { return false; }
 120 static inline bool tm_active_with_altivec(struct task_struct *tsk) { return false; }
 121 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 122
 123 bool strict_msr_control;
 124 EXPORT_SYMBOL(strict_msr_control);
 125
 126 static int __init enable_strict_msr_control(char *str)
 127 {
 128         strict_msr_control = true;
 129         pr_info("Enabling strict facility control\n");
 130
 131         return 0;
 132 }
 133 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
 134
 135 unsigned long msr_check_and_set(unsigned long bits)
 136 {
 137         unsigned long oldmsr = mfmsr();
 138         unsigned long newmsr;
 139
 140         newmsr = oldmsr | bits;
 141
 142 #ifdef CONFIG_VSX
 143         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 144                 newmsr |= MSR_VSX;
 145 #endif
 146
 147         if (oldmsr != newmsr)
 148                 mtmsr_isync(newmsr);
 149
 150         return newmsr;
 151 }
 152 EXPORT_SYMBOL_GPL(msr_check_and_set);
 153
 154 void __msr_check_and_clear(unsigned long bits)
 155 {
 156         unsigned long oldmsr = mfmsr();
 157         unsigned long newmsr;
 158
 159         newmsr = oldmsr & ~bits;
 160
 161 #ifdef CONFIG_VSX
 162         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 163                 newmsr &= ~MSR_VSX;
 164 #endif
 165
 166         if (oldmsr != newmsr)
 167                 mtmsr_isync(newmsr);
 168 }
 169 EXPORT_SYMBOL(__msr_check_and_clear);
 170
 171 #ifdef CONFIG_PPC_FPU
 172 static void __giveup_fpu(struct task_struct *tsk)
 173 {
 174         unsigned long msr;
 175
 176         save_fpu(tsk);
 177         msr = tsk->thread.regs->msr;
 178         msr &= ~MSR_FP;
 179 #ifdef CONFIG_VSX
 180         if (cpu_has_feature(CPU_FTR_VSX))
 181                 msr &= ~MSR_VSX;
 182 #endif
 183         tsk->thread.regs->msr = msr;
 184 }
 185
 186 void giveup_fpu(struct task_struct *tsk)
 187 {
 188         check_if_tm_restore_required(tsk);
 189
 190         msr_check_and_set(MSR_FP);
 191         __giveup_fpu(tsk);
 192         msr_check_and_clear(MSR_FP);
 193 }
 194 EXPORT_SYMBOL(giveup_fpu);
 195
 196 /*
 197  * Make sure the floating-point register state in the
 198  * the thread_struct is up to date for task tsk.
 199  */
 200 void flush_fp_to_thread(struct task_struct *tsk)
 201 {
 202         if (tsk->thread.regs) {
 203                 /*
 204                  * We need to disable preemption here because if we didn't,
 205                  * another process could get scheduled after the regs->msr
 206                  * test but before we have finished saving the FP registers
 207                  * to the thread_struct.  That process could take over the
 208                  * FPU, and then when we get scheduled again we would store
 209                  * bogus values for the remaining FP registers.
 210                  */
 211                 preempt_disable();
 212                 if (tsk->thread.regs->msr & MSR_FP) {
 213                         /*
 214                          * This should only ever be called for current or
 215                          * for a stopped child process.  Since we save away
 216                          * the FP register state on context switch,
 217                          * there is something wrong if a stopped child appears
 218                          * to still have its FP state in the CPU registers.
 219                          */
 220                         BUG_ON(tsk != current);
 221                         giveup_fpu(tsk);
 222                 }
 223                 preempt_enable();
 224         }
 225 }
 226 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
 227
 228 void enable_kernel_fp(void)
 229 {
 230         unsigned long cpumsr;
 231
 232         WARN_ON(preemptible());
 233
 234         cpumsr = msr_check_and_set(MSR_FP);
 235
 236         if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
 237                 check_if_tm_restore_required(current);
 238                 /*
 239                  * If a thread has already been reclaimed then the
 240                  * checkpointed registers are on the CPU but have definitely
 241                  * been saved by the reclaim code. Don't need to and *cannot*
 242                  * giveup as this would save  to the 'live' structure not the
 243                  * checkpointed structure.
 244                  */
 245                 if (!MSR_TM_ACTIVE(cpumsr) &&
 246                      MSR_TM_ACTIVE(current->thread.regs->msr))
 247                         return;
 248                 __giveup_fpu(current);
 249         }
 250 }
 251 EXPORT_SYMBOL(enable_kernel_fp);
 252
 253 static int restore_fp(struct task_struct *tsk)
 254 {
 255         if (tsk->thread.load_fp || tm_active_with_fp(tsk)) {
 256                 load_fp_state(&current->thread.fp_state);
 257                 current->thread.load_fp++;
 258                 return 1;
 259         }
 260         return 0;
 261 }
 262 #else
 263 static int restore_fp(struct task_struct *tsk) { return 0; }
 264 #endif /* CONFIG_PPC_FPU */
 265
 266 #ifdef CONFIG_ALTIVEC
 267 #define loadvec(thr) ((thr).load_vec)
 268
 269 static void __giveup_altivec(struct task_struct *tsk)
 270 {
 271         unsigned long msr;
 272
 273         save_altivec(tsk);
 274         msr = tsk->thread.regs->msr;
 275         msr &= ~MSR_VEC;
 276 #ifdef CONFIG_VSX
 277         if (cpu_has_feature(CPU_FTR_VSX))
 278                 msr &= ~MSR_VSX;
 279 #endif
 280         tsk->thread.regs->msr = msr;
 281 }
 282
 283 void giveup_altivec(struct task_struct *tsk)
 284 {
 285         check_if_tm_restore_required(tsk);
 286
 287         msr_check_and_set(MSR_VEC);
 288         __giveup_altivec(tsk);
 289         msr_check_and_clear(MSR_VEC);
 290 }
 291 EXPORT_SYMBOL(giveup_altivec);
 292
 293 void enable_kernel_altivec(void)
 294 {
 295         unsigned long cpumsr;
 296
 297         WARN_ON(preemptible());
 298
 299         cpumsr = msr_check_and_set(MSR_VEC);
 300
 301         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
 302                 check_if_tm_restore_required(current);
 303                 /*
 304                  * If a thread has already been reclaimed then the
 305                  * checkpointed registers are on the CPU but have definitely
 306                  * been saved by the reclaim code. Don't need to and *cannot*
 307                  * giveup as this would save  to the 'live' structure not the
 308                  * checkpointed structure.
 309                  */
 310                 if (!MSR_TM_ACTIVE(cpumsr) &&
 311                      MSR_TM_ACTIVE(current->thread.regs->msr))
 312                         return;
 313                 __giveup_altivec(current);
 314         }
 315 }
 316 EXPORT_SYMBOL(enable_kernel_altivec);
 317
 318 /*
 319  * Make sure the VMX/Altivec register state in the
 320  * the thread_struct is up to date for task tsk.
 321  */
 322 void flush_altivec_to_thread(struct task_struct *tsk)
 323 {
 324         if (tsk->thread.regs) {
 325                 preempt_disable();
 326                 if (tsk->thread.regs->msr & MSR_VEC) {
 327                         BUG_ON(tsk != current);
 328                         giveup_altivec(tsk);
 329                 }
 330                 preempt_enable();
 331         }
 332 }
 333 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
 334
 335 static int restore_altivec(struct task_struct *tsk)
 336 {
 337         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
 338                 (tsk->thread.load_vec || tm_active_with_altivec(tsk))) {
 339                 load_vr_state(&tsk->thread.vr_state);
 340                 tsk->thread.used_vr = 1;
 341                 tsk->thread.load_vec++;
 342
 343                 return 1;
 344         }
 345         return 0;
 346 }
 347 #else
 348 #define loadvec(thr) 0
 349 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
 350 #endif /* CONFIG_ALTIVEC */
 351
 352 #ifdef CONFIG_VSX
 353 static void __giveup_vsx(struct task_struct *tsk)
 354 {
 355         unsigned long msr = tsk->thread.regs->msr;
 356
 357         /*
 358          * We should never be ssetting MSR_VSX without also setting
 359          * MSR_FP and MSR_VEC
 360          */
 361         WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC)));
 362
 363         /* __giveup_fpu will clear MSR_VSX */
 364         if (msr & MSR_FP)
 365                 __giveup_fpu(tsk);
 366         if (msr & MSR_VEC)
 367                 __giveup_altivec(tsk);
 368 }
 369
 370 static void giveup_vsx(struct task_struct *tsk)
 371 {
 372         check_if_tm_restore_required(tsk);
 373
 374         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 375         __giveup_vsx(tsk);
 376         msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
 377 }
 378
 379 void enable_kernel_vsx(void)
 380 {
 381         unsigned long cpumsr;
 382
 383         WARN_ON(preemptible());
 384
 385         cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 386
 387         if (current->thread.regs &&
 388             (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) {
 389                 check_if_tm_restore_required(current);
 390                 /*
 391                  * If a thread has already been reclaimed then the
 392                  * checkpointed registers are on the CPU but have definitely
 393                  * been saved by the reclaim code. Don't need to and *cannot*
 394                  * giveup as this would save  to the 'live' structure not the
 395                  * checkpointed structure.
 396                  */
 397                 if (!MSR_TM_ACTIVE(cpumsr) &&
 398                      MSR_TM_ACTIVE(current->thread.regs->msr))
 399                         return;
 400                 __giveup_vsx(current);
 401         }
 402 }
 403 EXPORT_SYMBOL(enable_kernel_vsx);
 404
 405 void flush_vsx_to_thread(struct task_struct *tsk)
 406 {
 407         if (tsk->thread.regs) {
 408                 preempt_disable();
 409                 if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) {
 410                         BUG_ON(tsk != current);
 411                         giveup_vsx(tsk);
 412                 }
 413                 preempt_enable();
 414         }
 415 }
 416 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
 417
 418 static int restore_vsx(struct task_struct *tsk)
 419 {
 420         if (cpu_has_feature(CPU_FTR_VSX)) {
 421                 tsk->thread.used_vsr = 1;
 422                 return 1;
 423         }
 424
 425         return 0;
 426 }
 427 #else
 428 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
 429 #endif /* CONFIG_VSX */
 430
 431 #ifdef CONFIG_SPE
 432 void giveup_spe(struct task_struct *tsk)
 433 {
 434         check_if_tm_restore_required(tsk);
 435
 436         msr_check_and_set(MSR_SPE);
 437         __giveup_spe(tsk);
 438         msr_check_and_clear(MSR_SPE);
 439 }
 440 EXPORT_SYMBOL(giveup_spe);
 441
 442 void enable_kernel_spe(void)
 443 {
 444         WARN_ON(preemptible());
 445
 446         msr_check_and_set(MSR_SPE);
 447
 448         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
 449                 check_if_tm_restore_required(current);
 450                 __giveup_spe(current);
 451         }
 452 }
 453 EXPORT_SYMBOL(enable_kernel_spe);
 454
 455 void flush_spe_to_thread(struct task_struct *tsk)
 456 {
 457         if (tsk->thread.regs) {
 458                 preempt_disable();
 459                 if (tsk->thread.regs->msr & MSR_SPE) {
 460                         BUG_ON(tsk != current);
 461                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 462                         giveup_spe(tsk);
 463                 }
 464                 preempt_enable();
 465         }
 466 }
 467 #endif /* CONFIG_SPE */
 468
 469 static unsigned long msr_all_available;
 470
 471 static int __init init_msr_all_available(void)
 472 {
 473 #ifdef CONFIG_PPC_FPU
 474         msr_all_available |= MSR_FP;
 475 #endif
 476 #ifdef CONFIG_ALTIVEC
 477         if (cpu_has_feature(CPU_FTR_ALTIVEC))
 478                 msr_all_available |= MSR_VEC;
 479 #endif
 480 #ifdef CONFIG_VSX
 481         if (cpu_has_feature(CPU_FTR_VSX))
 482                 msr_all_available |= MSR_VSX;
 483 #endif
 484 #ifdef CONFIG_SPE
 485         if (cpu_has_feature(CPU_FTR_SPE))
 486                 msr_all_available |= MSR_SPE;
 487 #endif
 488
 489         return 0;
 490 }
 491 early_initcall(init_msr_all_available);
 492
 493 void giveup_all(struct task_struct *tsk)
 494 {
 495         unsigned long usermsr;
 496
 497         if (!tsk->thread.regs)
 498                 return;
 499
 500         usermsr = tsk->thread.regs->msr;
 501
 502         if ((usermsr & msr_all_available) == 0)
 503                 return;
 504
 505         msr_check_and_set(msr_all_available);
 506         check_if_tm_restore_required(tsk);
 507
 508         WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
 509
 510 #ifdef CONFIG_PPC_FPU
 511         if (usermsr & MSR_FP)
 512                 __giveup_fpu(tsk);
 513 #endif
 514 #ifdef CONFIG_ALTIVEC
 515         if (usermsr & MSR_VEC)
 516                 __giveup_altivec(tsk);
 517 #endif
 518 #ifdef CONFIG_SPE
 519         if (usermsr & MSR_SPE)
 520                 __giveup_spe(tsk);
 521 #endif
 522
 523         msr_check_and_clear(msr_all_available);
 524 }
 525 EXPORT_SYMBOL(giveup_all);
 526
 527 void restore_math(struct pt_regs *regs)
 528 {
 529         unsigned long msr;
 530
 531         if (!MSR_TM_ACTIVE(regs->msr) &&
 532                 !current->thread.load_fp && !loadvec(current->thread))
 533                 return;
 534
 535         msr = regs->msr;
 536         msr_check_and_set(msr_all_available);
 537
 538         /*
 539          * Only reload if the bit is not set in the user MSR, the bit BEING set
 540          * indicates that the registers are hot
 541          */
 542         if ((!(msr & MSR_FP)) && restore_fp(current))
 543                 msr |= MSR_FP | current->thread.fpexc_mode;
 544
 545         if ((!(msr & MSR_VEC)) && restore_altivec(current))
 546                 msr |= MSR_VEC;
 547
 548         if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
 549                         restore_vsx(current)) {
 550                 msr |= MSR_VSX;
 551         }
 552
 553         msr_check_and_clear(msr_all_available);
 554
 555         regs->msr = msr;
 556 }
 557
 558 static void save_all(struct task_struct *tsk)
 559 {
 560         unsigned long usermsr;
 561
 562         if (!tsk->thread.regs)
 563                 return;
 564
 565         usermsr = tsk->thread.regs->msr;
 566
 567         if ((usermsr & msr_all_available) == 0)
 568                 return;
 569
 570         msr_check_and_set(msr_all_available);
 571
 572         WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
 573
 574         if (usermsr & MSR_FP)
 575                 save_fpu(tsk);
 576
 577         if (usermsr & MSR_VEC)
 578                 save_altivec(tsk);
 579
 580         if (usermsr & MSR_SPE)
 581                 __giveup_spe(tsk);
 582
 583         msr_check_and_clear(msr_all_available);
 584         thread_pkey_regs_save(&tsk->thread);
 585 }
 586
 587 void flush_all_to_thread(struct task_struct *tsk)
 588 {
 589         if (tsk->thread.regs) {
 590                 preempt_disable();
 591                 BUG_ON(tsk != current);
 592                 save_all(tsk);
 593
 594 #ifdef CONFIG_SPE
 595                 if (tsk->thread.regs->msr & MSR_SPE)
 596                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 597 #endif
 598
 599                 preempt_enable();
 600         }
 601 }
 602 EXPORT_SYMBOL(flush_all_to_thread);
 603
 604 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 605 void do_send_trap(struct pt_regs *regs, unsigned long address,
 606                   unsigned long error_code, int breakpt)
 607 {
 608         current->thread.trap_nr = TRAP_HWBKPT;
 609         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 610                         11, SIGSEGV) == NOTIFY_STOP)
 611                 return;
 612
 613         /* Deliver the signal to userspace */
 614         force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */
 615                                     (void __user *)address);
 616 }
 617 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 618 void do_break (struct pt_regs *regs, unsigned long address,
 619                     unsigned long error_code)
 620 {
 621         siginfo_t info;
 622
 623         current->thread.trap_nr = TRAP_HWBKPT;
 624         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 625                         11, SIGSEGV) == NOTIFY_STOP)
 626                 return;
 627
 628         if (debugger_break_match(regs))
 629                 return;
 630
 631         /* Clear the breakpoint */
 632         hw_breakpoint_disable();
 633
 634         /* Deliver the signal to userspace */
 635         clear_siginfo(&info);
 636         info.si_signo = SIGTRAP;
 637         info.si_errno = 0;
 638         info.si_code = TRAP_HWBKPT;
 639         info.si_addr = (void __user *)address;
 640         force_sig_info(SIGTRAP, &info, current);
 641 }
 642 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 643
 644 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
 645
 646 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 647 /*
 648  * Set the debug registers back to their default "safe" values.
 649  */
 650 static void set_debug_reg_defaults(struct thread_struct *thread)
 651 {
 652         thread->debug.iac1 = thread->debug.iac2 = 0;
 653 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 654         thread->debug.iac3 = thread->debug.iac4 = 0;
 655 #endif
 656         thread->debug.dac1 = thread->debug.dac2 = 0;
 657 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 658         thread->debug.dvc1 = thread->debug.dvc2 = 0;
 659 #endif
 660         thread->debug.dbcr0 = 0;
 661 #ifdef CONFIG_BOOKE
 662         /*
 663          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
 664          */
 665         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
 666                         DBCR1_IAC3US | DBCR1_IAC4US;
 667         /*
 668          * Force Data Address Compare User/Supervisor bits to be User-only
 669          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
 670          */
 671         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 672 #else
 673         thread->debug.dbcr1 = 0;
 674 #endif
 675 }
 676
 677 static void prime_debug_regs(struct debug_reg *debug)
 678 {
 679         /*
 680          * We could have inherited MSR_DE from userspace, since
 681          * it doesn't get cleared on exception entry.  Make sure
 682          * MSR_DE is clear before we enable any debug events.
 683          */
 684         mtmsr(mfmsr() & ~MSR_DE);
 685
 686         mtspr(SPRN_IAC1, debug->iac1);
 687         mtspr(SPRN_IAC2, debug->iac2);
 688 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 689         mtspr(SPRN_IAC3, debug->iac3);
 690         mtspr(SPRN_IAC4, debug->iac4);
 691 #endif
 692         mtspr(SPRN_DAC1, debug->dac1);
 693         mtspr(SPRN_DAC2, debug->dac2);
 694 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 695         mtspr(SPRN_DVC1, debug->dvc1);
 696         mtspr(SPRN_DVC2, debug->dvc2);
 697 #endif
 698         mtspr(SPRN_DBCR0, debug->dbcr0);
 699         mtspr(SPRN_DBCR1, debug->dbcr1);
 700 #ifdef CONFIG_BOOKE
 701         mtspr(SPRN_DBCR2, debug->dbcr2);
 702 #endif
 703 }
 704 /*
 705  * Unless neither the old or new thread are making use of the
 706  * debug registers, set the debug registers from the values
 707  * stored in the new thread.
 708  */
 709 void switch_booke_debug_regs(struct debug_reg *new_debug)
 710 {
 711         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
 712                 || (new_debug->dbcr0 & DBCR0_IDM))
 713                         prime_debug_regs(new_debug);
 714 }
 715 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
 716 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 717 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 718 static void set_breakpoint(struct arch_hw_breakpoint *brk)
 719 {
 720         preempt_disable();
 721         __set_breakpoint(brk);
 722         preempt_enable();
 723 }
 724
 725 static void set_debug_reg_defaults(struct thread_struct *thread)
 726 {
 727         thread->hw_brk.address = 0;
 728         thread->hw_brk.type = 0;
 729         if (ppc_breakpoint_available())
 730                 set_breakpoint(&thread->hw_brk);
 731 }
 732 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 733 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 734
 735 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 736 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 737 {
 738         mtspr(SPRN_DAC1, dabr);
 739 #ifdef CONFIG_PPC_47x
 740         isync();
 741 #endif
 742         return 0;
 743 }
 744 #elif defined(CONFIG_PPC_BOOK3S)
 745 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 746 {
 747         mtspr(SPRN_DABR, dabr);
 748         if (cpu_has_feature(CPU_FTR_DABRX))
 749                 mtspr(SPRN_DABRX, dabrx);
 750         return 0;
 751 }
 752 #elif defined(CONFIG_PPC_8xx)
 753 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 754 {
 755         unsigned long addr = dabr & ~HW_BRK_TYPE_DABR;
 756         unsigned long lctrl1 = 0x90000000; /* compare type: equal on E & F */
 757         unsigned long lctrl2 = 0x8e000002; /* watchpoint 1 on cmp E | F */
 758
 759         if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
 760                 lctrl1 |= 0xa0000;
 761         else if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
 762                 lctrl1 |= 0xf0000;
 763         else if ((dabr & HW_BRK_TYPE_RDWR) == 0)
 764                 lctrl2 = 0;
 765
 766         mtspr(SPRN_LCTRL2, 0);
 767         mtspr(SPRN_CMPE, addr);
 768         mtspr(SPRN_CMPF, addr + 4);
 769         mtspr(SPRN_LCTRL1, lctrl1);
 770         mtspr(SPRN_LCTRL2, lctrl2);
 771
 772         return 0;
 773 }
 774 #else
 775 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 776 {
 777         return -EINVAL;
 778 }
 779 #endif
 780
 781 static inline int set_dabr(struct arch_hw_breakpoint *brk)
 782 {
 783         unsigned long dabr, dabrx;
 784
 785         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
 786         dabrx = ((brk->type >> 3) & 0x7);
 787
 788         if (ppc_md.set_dabr)
 789                 return ppc_md.set_dabr(dabr, dabrx);
 790
 791         return __set_dabr(dabr, dabrx);
 792 }
 793
 794 static inline int set_dawr(struct arch_hw_breakpoint *brk)
 795 {
 796         unsigned long dawr, dawrx, mrd;
 797
 798         dawr = brk->address;
 799
 800         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
 801                                    << (63 - 58); //* read/write bits */
 802         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
 803                                    << (63 - 59); //* translate */
 804         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
 805                                    >> 3; //* PRIM bits */
 806         /* dawr length is stored in field MDR bits 48:53.  Matches range in
 807            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
 808            0b111111=64DW.
 809            brk->len is in bytes.
 810            This aligns up to double word size, shifts and does the bias.
 811         */
 812         mrd = ((brk->len + 7) >> 3) - 1;
 813         dawrx |= (mrd & 0x3f) << (63 - 53);
 814
 815         if (ppc_md.set_dawr)
 816                 return ppc_md.set_dawr(dawr, dawrx);
 817         mtspr(SPRN_DAWR, dawr);
 818         mtspr(SPRN_DAWRX, dawrx);
 819         return 0;
 820 }
 821
 822 void __set_breakpoint(struct arch_hw_breakpoint *brk)
 823 {
 824         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
 825
 826         if (cpu_has_feature(CPU_FTR_DAWR))
 827                 // Power8 or later
 828                 set_dawr(brk);
 829         else if (!cpu_has_feature(CPU_FTR_ARCH_207S))
 830                 // Power7 or earlier
 831                 set_dabr(brk);
 832         else
 833                 // Shouldn't happen due to higher level checks
 834                 WARN_ON_ONCE(1);
 835 }
 836
 837 /* Check if we have DAWR or DABR hardware */
 838 bool ppc_breakpoint_available(void)
 839 {
 840         if (cpu_has_feature(CPU_FTR_DAWR))
 841                 return true; /* POWER8 DAWR */
 842         if (cpu_has_feature(CPU_FTR_ARCH_207S))
 843                 return false; /* POWER9 with DAWR disabled */
 844         /* DABR: Everything but POWER8 and POWER9 */
 845         return true;
 846 }
 847 EXPORT_SYMBOL_GPL(ppc_breakpoint_available);
 848
 849 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
 850                               struct arch_hw_breakpoint *b)
 851 {
 852         if (a->address != b->address)
 853                 return false;
 854         if (a->type != b->type)
 855                 return false;
 856         if (a->len != b->len)
 857                 return false;
 858         return true;
 859 }
 860
 861 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 862
 863 static inline bool tm_enabled(struct task_struct *tsk)
 864 {
 865         return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
 866 }
 867
 868 static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause)
 869 {
 870         /*
 871          * Use the current MSR TM suspended bit to track if we have
 872          * checkpointed state outstanding.
 873          * On signal delivery, we'd normally reclaim the checkpointed
 874          * state to obtain stack pointer (see:get_tm_stackpointer()).
 875          * This will then directly return to userspace without going
 876          * through __switch_to(). However, if the stack frame is bad,
 877          * we need to exit this thread which calls __switch_to() which
 878          * will again attempt to reclaim the already saved tm state.
 879          * Hence we need to check that we've not already reclaimed
 880          * this state.
 881          * We do this using the current MSR, rather tracking it in
 882          * some specific thread_struct bit, as it has the additional
 883          * benefit of checking for a potential TM bad thing exception.
 884          */
 885         if (!MSR_TM_SUSPENDED(mfmsr()))
 886                 return;
 887
 888         giveup_all(container_of(thr, struct task_struct, thread));
 889
 890         tm_reclaim(thr, cause);
 891
 892         /*
 893          * If we are in a transaction and FP is off then we can't have
 894          * used FP inside that transaction. Hence the checkpointed
 895          * state is the same as the live state. We need to copy the
 896          * live state to the checkpointed state so that when the
 897          * transaction is restored, the checkpointed state is correct
 898          * and the aborted transaction sees the correct state. We use
 899          * ckpt_regs.msr here as that's what tm_reclaim will use to
 900          * determine if it's going to write the checkpointed state or
 901          * not. So either this will write the checkpointed registers,
 902          * or reclaim will. Similarly for VMX.
 903          */
 904         if ((thr->ckpt_regs.msr & MSR_FP) == 0)
 905                 memcpy(&thr->ckfp_state, &thr->fp_state,
 906                        sizeof(struct thread_fp_state));
 907         if ((thr->ckpt_regs.msr & MSR_VEC) == 0)
 908                 memcpy(&thr->ckvr_state, &thr->vr_state,
 909                        sizeof(struct thread_vr_state));
 910 }
 911
 912 void tm_reclaim_current(uint8_t cause)
 913 {
 914         tm_enable();
 915         tm_reclaim_thread(&current->thread, cause);
 916 }
 917
 918 static inline void tm_reclaim_task(struct task_struct *tsk)
 919 {
 920         /* We have to work out if we're switching from/to a task that's in the
 921          * middle of a transaction.
 922          *
 923          * In switching we need to maintain a 2nd register state as
 924          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
 925          * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
 926          * ckvr_state
 927          *
 928          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
 929          */
 930         struct thread_struct *thr = &tsk->thread;
 931
 932         if (!thr->regs)
 933                 return;
 934
 935         if (!MSR_TM_ACTIVE(thr->regs->msr))
 936                 goto out_and_saveregs;
 937
 938         WARN_ON(tm_suspend_disabled);
 939
 940         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
 941                  "ccr=%lx, msr=%lx, trap=%lx)\n",
 942                  tsk->pid, thr->regs->nip,
 943                  thr->regs->ccr, thr->regs->msr,
 944                  thr->regs->trap);
 945
 946         tm_reclaim_thread(thr, TM_CAUSE_RESCHED);
 947
 948         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
 949                  tsk->pid);
 950
 951 out_and_saveregs:
 952         /* Always save the regs here, even if a transaction's not active.
 953          * This context-switches a thread's TM info SPRs.  We do it here to
 954          * be consistent with the restore path (in recheckpoint) which
 955          * cannot happen later in _switch().
 956          */
 957         tm_save_sprs(thr);
 958 }
 959
 960 extern void __tm_recheckpoint(struct thread_struct *thread);
 961
 962 void tm_recheckpoint(struct thread_struct *thread)
 963 {
 964         unsigned long flags;
 965
 966         if (!(thread->regs->msr & MSR_TM))
 967                 return;
 968
 969         /* We really can't be interrupted here as the TEXASR registers can't
 970          * change and later in the trecheckpoint code, we have a userspace R1.
 971          * So let's hard disable over this region.
 972          */
 973         local_irq_save(flags);
 974         hard_irq_disable();
 975
 976         /* The TM SPRs are restored here, so that TEXASR.FS can be set
 977          * before the trecheckpoint and no explosion occurs.
 978          */
 979         tm_restore_sprs(thread);
 980
 981         __tm_recheckpoint(thread);
 982
 983         local_irq_restore(flags);
 984 }
 985
 986 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 987 {
 988         if (!cpu_has_feature(CPU_FTR_TM))
 989                 return;
 990
 991         /* Recheckpoint the registers of the thread we're about to switch to.
 992          *
 993          * If the task was using FP, we non-lazily reload both the original and
 994          * the speculative FP register states.  This is because the kernel
 995          * doesn't see if/when a TM rollback occurs, so if we take an FP
 996          * unavailable later, we are unable to determine which set of FP regs
 997          * need to be restored.
 998          */
 999         if (!tm_enabled(new))
1000                 return;
1001
1002         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
1003                 tm_restore_sprs(&new->thread);
1004                 return;
1005         }
1006         /* Recheckpoint to restore original checkpointed register state. */
1007         TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n",
1008                  new->pid, new->thread.regs->msr);
1009
1010         tm_recheckpoint(&new->thread);
1011
1012         /*
1013          * The checkpointed state has been restored but the live state has
1014          * not, ensure all the math functionality is turned off to trigger
1015          * restore_math() to reload.
1016          */
1017         new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
1018
1019         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
1020                  "(kernel msr 0x%lx)\n",
1021                  new->pid, mfmsr());
1022 }
1023
1024 static inline void __switch_to_tm(struct task_struct *prev,
1025                 struct task_struct *new)
1026 {
1027         if (cpu_has_feature(CPU_FTR_TM)) {
1028                 if (tm_enabled(prev) || tm_enabled(new))
1029                         tm_enable();
1030
1031                 if (tm_enabled(prev)) {
1032                         prev->thread.load_tm++;
1033                         tm_reclaim_task(prev);
1034                         if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
1035                                 prev->thread.regs->msr &= ~MSR_TM;
1036                 }
1037
1038                 tm_recheckpoint_new_task(new);
1039         }
1040 }
1041
1042 /*
1043  * This is called if we are on the way out to userspace and the
1044  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
1045  * FP and/or vector state and does so if necessary.
1046  * If userspace is inside a transaction (whether active or
1047  * suspended) and FP/VMX/VSX instructions have ever been enabled
1048  * inside that transaction, then we have to keep them enabled
1049  * and keep the FP/VMX/VSX state loaded while ever the transaction
1050  * continues.  The reason is that if we didn't, and subsequently
1051  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1052  * we don't know whether it's the same transaction, and thus we
1053  * don't know which of the checkpointed state and the transactional
1054  * state to use.
1055  */
1056 void restore_tm_state(struct pt_regs *regs)
1057 {
1058         unsigned long msr_diff;
1059
1060         /*
1061          * This is the only moment we should clear TIF_RESTORE_TM as
1062          * it is here that ckpt_regs.msr and pt_regs.msr become the same
1063          * again, anything else could lead to an incorrect ckpt_msr being
1064          * saved and therefore incorrect signal contexts.
1065          */
1066         clear_thread_flag(TIF_RESTORE_TM);
1067         if (!MSR_TM_ACTIVE(regs->msr))
1068                 return;
1069
1070         msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
1071         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
1072
1073         /* Ensure that restore_math() will restore */
1074         if (msr_diff & MSR_FP)
1075                 current->thread.load_fp = 1;
1076 #ifdef CONFIG_ALTIVEC
1077         if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1078                 current->thread.load_vec = 1;
1079 #endif
1080         restore_math(regs);
1081
1082         regs->msr |= msr_diff;
1083 }
1084
1085 #else
1086 #define tm_recheckpoint_new_task(new)
1087 #define __switch_to_tm(prev, new)
1088 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1089
1090 static inline void save_sprs(struct thread_struct *t)
1091 {
1092 #ifdef CONFIG_ALTIVEC
1093         if (cpu_has_feature(CPU_FTR_ALTIVEC))
1094                 t->vrsave = mfspr(SPRN_VRSAVE);
1095 #endif
1096 #ifdef CONFIG_PPC_BOOK3S_64
1097         if (cpu_has_feature(CPU_FTR_DSCR))
1098                 t->dscr = mfspr(SPRN_DSCR);
1099
1100         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1101                 t->bescr = mfspr(SPRN_BESCR);
1102                 t->ebbhr = mfspr(SPRN_EBBHR);
1103                 t->ebbrr = mfspr(SPRN_EBBRR);
1104
1105                 t->fscr = mfspr(SPRN_FSCR);
1106
1107                 /*
1108                  * Note that the TAR is not available for use in the kernel.
1109                  * (To provide this, the TAR should be backed up/restored on
1110                  * exception entry/exit instead, and be in pt_regs.  FIXME,
1111                  * this should be in pt_regs anyway (for debug).)
1112                  */
1113                 t->tar = mfspr(SPRN_TAR);
1114         }
1115 #endif
1116
1117         thread_pkey_regs_save(t);
1118 }
1119
1120 static inline void restore_sprs(struct thread_struct *old_thread,
1121                                 struct thread_struct *new_thread)
1122 {
1123 #ifdef CONFIG_ALTIVEC
1124         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1125             old_thread->vrsave != new_thread->vrsave)
1126                 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1127 #endif
1128 #ifdef CONFIG_PPC_BOOK3S_64
1129         if (cpu_has_feature(CPU_FTR_DSCR)) {
1130                 u64 dscr = get_paca()->dscr_default;
1131                 if (new_thread->dscr_inherit)
1132                         dscr = new_thread->dscr;
1133
1134                 if (old_thread->dscr != dscr)
1135                         mtspr(SPRN_DSCR, dscr);
1136         }
1137
1138         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1139                 if (old_thread->bescr != new_thread->bescr)
1140                         mtspr(SPRN_BESCR, new_thread->bescr);
1141                 if (old_thread->ebbhr != new_thread->ebbhr)
1142                         mtspr(SPRN_EBBHR, new_thread->ebbhr);
1143                 if (old_thread->ebbrr != new_thread->ebbrr)
1144                         mtspr(SPRN_EBBRR, new_thread->ebbrr);
1145
1146                 if (old_thread->fscr != new_thread->fscr)
1147                         mtspr(SPRN_FSCR, new_thread->fscr);
1148
1149                 if (old_thread->tar != new_thread->tar)
1150                         mtspr(SPRN_TAR, new_thread->tar);
1151         }
1152
1153         if (cpu_has_feature(CPU_FTR_P9_TIDR) &&
1154             old_thread->tidr != new_thread->tidr)
1155                 mtspr(SPRN_TIDR, new_thread->tidr);
1156 #endif
1157
1158         thread_pkey_regs_restore(new_thread, old_thread);
1159 }
1160
1161 #ifdef CONFIG_PPC_BOOK3S_64
1162 #define CP_SIZE 128
1163 static const u8 dummy_copy_buffer[CP_SIZE] __attribute__((aligned(CP_SIZE)));
1164 #endif
1165
1166 struct task_struct *__switch_to(struct task_struct *prev,
1167         struct task_struct *new)
1168 {
1169         struct thread_struct *new_thread, *old_thread;
1170         struct task_struct *last;
1171 #ifdef CONFIG_PPC_BOOK3S_64
1172         struct ppc64_tlb_batch *batch;
1173 #endif
1174
1175         new_thread = &new->thread;
1176         old_thread = &current->thread;
1177
1178         WARN_ON(!irqs_disabled());
1179
1180 #ifdef CONFIG_PPC_BOOK3S_64
1181         batch = this_cpu_ptr(&ppc64_tlb_batch);
1182         if (batch->active) {
1183                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1184                 if (batch->index)
1185                         __flush_tlb_pending(batch);
1186                 batch->active = 0;
1187         }
1188 #endif /* CONFIG_PPC_BOOK3S_64 */
1189
1190 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1191         switch_booke_debug_regs(&new->thread.debug);
1192 #else
1193 /*
1194  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1195  * schedule DABR
1196  */
1197 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1198         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
1199                 __set_breakpoint(&new->thread.hw_brk);
1200 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1201 #endif
1202
1203         /*
1204          * We need to save SPRs before treclaim/trecheckpoint as these will
1205          * change a number of them.
1206          */
1207         save_sprs(&prev->thread);
1208
1209         /* Save FPU, Altivec, VSX and SPE state */
1210         giveup_all(prev);
1211
1212         __switch_to_tm(prev, new);
1213
1214         if (!radix_enabled()) {
1215                 /*
1216                  * We can't take a PMU exception inside _switch() since there
1217                  * is a window where the kernel stack SLB and the kernel stack
1218                  * are out of sync. Hard disable here.
1219                  */
1220                 hard_irq_disable();
1221         }
1222
1223         /*
1224          * Call restore_sprs() before calling _switch(). If we move it after
1225          * _switch() then we miss out on calling it for new tasks. The reason
1226          * for this is we manually create a stack frame for new tasks that
1227          * directly returns through ret_from_fork() or
1228          * ret_from_kernel_thread(). See copy_thread() for details.
1229          */
1230         restore_sprs(old_thread, new_thread);
1231
1232         last = _switch(old_thread, new_thread);
1233
1234 #ifdef CONFIG_PPC_BOOK3S_64
1235         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1236                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1237                 batch = this_cpu_ptr(&ppc64_tlb_batch);
1238                 batch->active = 1;
1239         }
1240
1241         if (current_thread_info()->task->thread.regs) {
1242                 restore_math(current_thread_info()->task->thread.regs);
1243
1244                 /*
1245                  * The copy-paste buffer can only store into foreign real
1246                  * addresses, so unprivileged processes can not see the
1247                  * data or use it in any way unless they have foreign real
1248                  * mappings. If the new process has the foreign real address
1249                  * mappings, we must issue a cp_abort to clear any state and
1250                  * prevent snooping, corruption or a covert channel.
1251                  */
1252                 if (current_thread_info()->task->thread.used_vas)
1253                         asm volatile(PPC_CP_ABORT);
1254         }
1255 #endif /* CONFIG_PPC_BOOK3S_64 */
1256
1257         return last;
1258 }
1259
1260 static int instructions_to_print = 16;
1261
1262 static void show_instructions(struct pt_regs *regs)
1263 {
1264         int i;
1265         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
1266                         sizeof(int));
1267
1268         printk("Instruction dump:");
1269
1270         for (i = 0; i < instructions_to_print; i++) {
1271                 int instr;
1272
1273                 if (!(i % 8))
1274                         pr_cont("\n");
1275
1276 #if !defined(CONFIG_BOOKE)
1277                 /* If executing with the IMMU off, adjust pc rather
1278                  * than print XXXXXXXX.
1279                  */
1280                 if (!(regs->msr & MSR_IR))
1281                         pc = (unsigned long)phys_to_virt(pc);
1282 #endif
1283
1284                 if (!__kernel_text_address(pc) ||
1285                     probe_kernel_address((const void *)pc, instr)) {
1286                         pr_cont("XXXXXXXX ");
1287                 } else {
1288                         if (regs->nip == pc)
1289                                 pr_cont("<%08x> ", instr);
1290                         else
1291                                 pr_cont("%08x ", instr);
1292                 }
1293
1294                 pc += sizeof(int);
1295         }
1296
1297         pr_cont("\n");
1298 }
1299
1300 void show_user_instructions(struct pt_regs *regs)
1301 {
1302         unsigned long pc;
1303         int i;
1304
1305         pc = regs->nip - (instructions_to_print * 3 / 4 * sizeof(int));
1306
1307         /*
1308          * Make sure the NIP points at userspace, not kernel text/data or
1309          * elsewhere.
1310          */
1311         if (!__access_ok(pc, instructions_to_print * sizeof(int), USER_DS)) {
1312                 pr_info("%s[%d]: Bad NIP, not dumping instructions.\n",
1313                         current->comm, current->pid);
1314                 return;
1315         }
1316
1317         pr_info("%s[%d]: code: ", current->comm, current->pid);
1318
1319         for (i = 0; i < instructions_to_print; i++) {
1320                 int instr;
1321
1322                 if (!(i % 8) && (i > 0)) {
1323                         pr_cont("\n");
1324                         pr_info("%s[%d]: code: ", current->comm, current->pid);
1325                 }
1326
1327                 if (probe_kernel_address((const void *)pc, instr)) {
1328                         pr_cont("XXXXXXXX ");
1329                 } else {
1330                         if (regs->nip == pc)
1331                                 pr_cont("<%08x> ", instr);
1332                         else
1333                                 pr_cont("%08x ", instr);
1334                 }
1335
1336                 pc += sizeof(int);
1337         }
1338
1339         pr_cont("\n");
1340 }
1341
1342 struct regbit {
1343         unsigned long bit;
1344         const char *name;
1345 };
1346
1347 static struct regbit msr_bits[] = {
1348 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1349         {MSR_SF,        "SF"},
1350         {MSR_HV,        "HV"},
1351 #endif
1352         {MSR_VEC,       "VEC"},
1353         {MSR_VSX,       "VSX"},
1354 #ifdef CONFIG_BOOKE
1355         {MSR_CE,        "CE"},
1356 #endif
1357         {MSR_EE,        "EE"},
1358         {MSR_PR,        "PR"},
1359         {MSR_FP,        "FP"},
1360         {MSR_ME,        "ME"},
1361 #ifdef CONFIG_BOOKE
1362         {MSR_DE,        "DE"},
1363 #else
1364         {MSR_SE,        "SE"},
1365         {MSR_BE,        "BE"},
1366 #endif
1367         {MSR_IR,        "IR"},
1368         {MSR_DR,        "DR"},
1369         {MSR_PMM,       "PMM"},
1370 #ifndef CONFIG_BOOKE
1371         {MSR_RI,        "RI"},
1372         {MSR_LE,        "LE"},
1373 #endif
1374         {0,             NULL}
1375 };
1376
1377 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1378 {
1379         const char *s = "";
1380
1381         for (; bits->bit; ++bits)
1382                 if (val & bits->bit) {
1383                         pr_cont("%s%s", s, bits->name);
1384                         s = sep;
1385                 }
1386 }
1387
1388 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1389 static struct regbit msr_tm_bits[] = {
1390         {MSR_TS_T,      "T"},
1391         {MSR_TS_S,      "S"},
1392         {MSR_TM,        "E"},
1393         {0,             NULL}
1394 };
1395
1396 static void print_tm_bits(unsigned long val)
1397 {
1398 /*
1399  * This only prints something if at least one of the TM bit is set.
1400  * Inside the TM[], the output means:
1401  *   E: Enabled         (bit 32)
1402  *   S: Suspended       (bit 33)
1403  *   T: Transactional   (bit 34)
1404  */
1405         if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1406                 pr_cont(",TM[");
1407                 print_bits(val, msr_tm_bits, "");
1408                 pr_cont("]");
1409         }
1410 }
1411 #else
1412 static void print_tm_bits(unsigned long val) {}
1413 #endif
1414
1415 static void print_msr_bits(unsigned long val)
1416 {
1417         pr_cont("<");
1418         print_bits(val, msr_bits, ",");
1419         print_tm_bits(val);
1420         pr_cont(">");
1421 }
1422
1423 #ifdef CONFIG_PPC64
1424 #define REG             "%016lx"
1425 #define REGS_PER_LINE   4
1426 #define LAST_VOLATILE   13
1427 #else
1428 #define REG             "%08lx"
1429 #define REGS_PER_LINE   8
1430 #define LAST_VOLATILE   12
1431 #endif
1432
1433 void show_regs(struct pt_regs * regs)
1434 {
1435         int i, trap;
1436
1437         show_regs_print_info(KERN_DEFAULT);
1438
1439         printk("NIP:  "REG" LR: "REG" CTR: "REG"\n",
1440                regs->nip, regs->link, regs->ctr);
1441         printk("REGS: %px TRAP: %04lx   %s  (%s)\n",
1442                regs, regs->trap, print_tainted(), init_utsname()->release);
1443         printk("MSR:  "REG" ", regs->msr);
1444         print_msr_bits(regs->msr);
1445         pr_cont("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1446         trap = TRAP(regs);
1447         if ((TRAP(regs) != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1448                 pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1449         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1450 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1451                 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1452 #else
1453                 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1454 #endif
1455 #ifdef CONFIG_PPC64
1456         pr_cont("IRQMASK: %lx ", regs->softe);
1457 #endif
1458 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1459         if (MSR_TM_ACTIVE(regs->msr))
1460                 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1461 #endif
1462
1463         for (i = 0;  i < 32;  i++) {
1464                 if ((i % REGS_PER_LINE) == 0)
1465                         pr_cont("\nGPR%02d: ", i);
1466                 pr_cont(REG " ", regs->gpr[i]);
1467                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1468                         break;
1469         }
1470         pr_cont("\n");
1471 #ifdef CONFIG_KALLSYMS
1472         /*
1473          * Lookup NIP late so we have the best change of getting the
1474          * above info out without failing
1475          */
1476         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1477         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1478 #endif
1479         show_stack(current, (unsigned long *) regs->gpr[1]);
1480         if (!user_mode(regs))
1481                 show_instructions(regs);
1482 }
1483
1484 void flush_thread(void)
1485 {
1486 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1487         flush_ptrace_hw_breakpoint(current);
1488 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1489         set_debug_reg_defaults(&current->thread);
1490 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1491 }
1492
1493 int set_thread_uses_vas(void)
1494 {
1495 #ifdef CONFIG_PPC_BOOK3S_64
1496         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1497                 return -EINVAL;
1498
1499         current->thread.used_vas = 1;
1500
1501         /*
1502          * Even a process that has no foreign real address mapping can use
1503          * an unpaired COPY instruction (to no real effect). Issue CP_ABORT
1504          * to clear any pending COPY and prevent a covert channel.
1505          *
1506          * __switch_to() will issue CP_ABORT on future context switches.
1507          */
1508         asm volatile(PPC_CP_ABORT);
1509
1510 #endif /* CONFIG_PPC_BOOK3S_64 */
1511         return 0;
1512 }
1513
1514 #ifdef CONFIG_PPC64
1515 /**
1516  * Assign a TIDR (thread ID) for task @t and set it in the thread
1517  * structure. For now, we only support setting TIDR for 'current' task.
1518  *
1519  * Since the TID value is a truncated form of it PID, it is possible
1520  * (but unlikely) for 2 threads to have the same TID. In the unlikely event
1521  * that 2 threads share the same TID and are waiting, one of the following
1522  * cases will happen:
1523  *
1524  * 1. The correct thread is running, the wrong thread is not
1525  * In this situation, the correct thread is woken and proceeds to pass it's
1526  * condition check.
1527  *
1528  * 2. Neither threads are running
1529  * In this situation, neither thread will be woken. When scheduled, the waiting
1530  * threads will execute either a wait, which will return immediately, followed
1531  * by a condition check, which will pass for the correct thread and fail
1532  * for the wrong thread, or they will execute the condition check immediately.
1533  *
1534  * 3. The wrong thread is running, the correct thread is not
1535  * The wrong thread will be woken, but will fail it's condition check and
1536  * re-execute wait. The correct thread, when scheduled, will execute either
1537  * it's condition check (which will pass), or wait, which returns immediately
1538  * when called the first time after the thread is scheduled, followed by it's
1539  * condition check (which will pass).
1540  *
1541  * 4. Both threads are running
1542  * Both threads will be woken. The wrong thread will fail it's condition check
1543  * and execute another wait, while the correct thread will pass it's condition
1544  * check.
1545  *
1546  * @t: the task to set the thread ID for
1547  */
1548 int set_thread_tidr(struct task_struct *t)
1549 {
1550         if (!cpu_has_feature(CPU_FTR_P9_TIDR))
1551                 return -EINVAL;
1552
1553         if (t != current)
1554                 return -EINVAL;
1555
1556         if (t->thread.tidr)
1557                 return 0;
1558
1559         t->thread.tidr = (u16)task_pid_nr(t);
1560         mtspr(SPRN_TIDR, t->thread.tidr);
1561
1562         return 0;
1563 }
1564 EXPORT_SYMBOL_GPL(set_thread_tidr);
1565
1566 #endif /* CONFIG_PPC64 */
1567
1568 void
1569 release_thread(struct task_struct *t)
1570 {
1571 }
1572
1573 /*
1574  * this gets called so that we can store coprocessor state into memory and
1575  * copy the current task into the new thread.
1576  */
1577 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1578 {
1579         flush_all_to_thread(src);
1580         /*
1581          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1582          * flush but it removes the checkpointed state from the current CPU and
1583          * transitions the CPU out of TM mode.  Hence we need to call
1584          * tm_recheckpoint_new_task() (on the same task) to restore the
1585          * checkpointed state back and the TM mode.
1586          *
1587          * Can't pass dst because it isn't ready. Doesn't matter, passing
1588          * dst is only important for __switch_to()
1589          */
1590         __switch_to_tm(src, src);
1591
1592         *dst = *src;
1593
1594         clear_task_ebb(dst);
1595
1596         return 0;
1597 }
1598
1599 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1600 {
1601 #ifdef CONFIG_PPC_BOOK3S_64
1602         unsigned long sp_vsid;
1603         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1604
1605         if (radix_enabled())
1606                 return;
1607
1608         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1609                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1610                         << SLB_VSID_SHIFT_1T;
1611         else
1612                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1613                         << SLB_VSID_SHIFT;
1614         sp_vsid |= SLB_VSID_KERNEL | llp;
1615         p->thread.ksp_vsid = sp_vsid;
1616 #endif
1617 }
1618
1619 /*
1620  * Copy a thread..
1621  */
1622
1623 /*
1624  * Copy architecture-specific thread state
1625  */
1626 int copy_thread(unsigned long clone_flags, unsigned long usp,
1627                 unsigned long kthread_arg, struct task_struct *p)
1628 {
1629         struct pt_regs *childregs, *kregs;
1630         extern void ret_from_fork(void);
1631         extern void ret_from_kernel_thread(void);
1632         void (*f)(void);
1633         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1634         struct thread_info *ti = task_thread_info(p);
1635
1636         klp_init_thread_info(ti);
1637
1638         /* Copy registers */
1639         sp -= sizeof(struct pt_regs);
1640         childregs = (struct pt_regs *) sp;
1641         if (unlikely(p->flags & PF_KTHREAD)) {
1642                 /* kernel thread */
1643                 memset(childregs, 0, sizeof(struct pt_regs));
1644                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1645                 /* function */
1646                 if (usp)
1647                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1648 #ifdef CONFIG_PPC64
1649                 clear_tsk_thread_flag(p, TIF_32BIT);
1650                 childregs->softe = IRQS_ENABLED;
1651 #endif
1652                 childregs->gpr[15] = kthread_arg;
1653                 p->thread.regs = NULL;  /* no user register state */
1654                 ti->flags |= _TIF_RESTOREALL;
1655                 f = ret_from_kernel_thread;
1656         } else {
1657                 /* user thread */
1658                 struct pt_regs *regs = current_pt_regs();
1659                 CHECK_FULL_REGS(regs);
1660                 *childregs = *regs;
1661                 if (usp)
1662                         childregs->gpr[1] = usp;
1663                 p->thread.regs = childregs;
1664                 childregs->gpr[3] = 0;  /* Result from fork() */
1665                 if (clone_flags & CLONE_SETTLS) {
1666 #ifdef CONFIG_PPC64
1667                         if (!is_32bit_task())
1668                                 childregs->gpr[13] = childregs->gpr[6];
1669                         else
1670 #endif
1671                                 childregs->gpr[2] = childregs->gpr[6];
1672                 }
1673
1674                 f = ret_from_fork;
1675         }
1676         childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1677         sp -= STACK_FRAME_OVERHEAD;
1678
1679         /*
1680          * The way this works is that at some point in the future
1681          * some task will call _switch to switch to the new task.
1682          * That will pop off the stack frame created below and start
1683          * the new task running at ret_from_fork.  The new task will
1684          * do some house keeping and then return from the fork or clone
1685          * system call, using the stack frame created above.
1686          */
1687         ((unsigned long *)sp)[0] = 0;
1688         sp -= sizeof(struct pt_regs);
1689         kregs = (struct pt_regs *) sp;
1690         sp -= STACK_FRAME_OVERHEAD;
1691         p->thread.ksp = sp;
1692 #ifdef CONFIG_PPC32
1693         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1694                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1695 #endif
1696 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1697         p->thread.ptrace_bps[0] = NULL;
1698 #endif
1699
1700         p->thread.fp_save_area = NULL;
1701 #ifdef CONFIG_ALTIVEC
1702         p->thread.vr_save_area = NULL;
1703 #endif
1704
1705         setup_ksp_vsid(p, sp);
1706
1707 #ifdef CONFIG_PPC64
1708         if (cpu_has_feature(CPU_FTR_DSCR)) {
1709                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1710                 p->thread.dscr = mfspr(SPRN_DSCR);
1711         }
1712         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1713                 p->thread.ppr = INIT_PPR;
1714
1715         p->thread.tidr = 0;
1716 #endif
1717         kregs->nip = ppc_function_entry(f);
1718         return 0;
1719 }
1720
1721 /*
1722  * Set up a thread for executing a new program
1723  */
1724 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1725 {
1726 #ifdef CONFIG_PPC64
1727         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1728 #endif
1729
1730         /*
1731          * If we exec out of a kernel thread then thread.regs will not be
1732          * set.  Do it now.
1733          */
1734         if (!current->thread.regs) {
1735                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1736                 current->thread.regs = regs - 1;
1737         }
1738
1739 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1740         /*
1741          * Clear any transactional state, we're exec()ing. The cause is
1742          * not important as there will never be a recheckpoint so it's not
1743          * user visible.
1744          */
1745         if (MSR_TM_SUSPENDED(mfmsr()))
1746                 tm_reclaim_current(0);
1747 #endif
1748
1749         memset(regs->gpr, 0, sizeof(regs->gpr));
1750         regs->ctr = 0;
1751         regs->link = 0;
1752         regs->xer = 0;
1753         regs->ccr = 0;
1754         regs->gpr[1] = sp;
1755
1756         /*
1757          * We have just cleared all the nonvolatile GPRs, so make
1758          * FULL_REGS(regs) return true.  This is necessary to allow
1759          * ptrace to examine the thread immediately after exec.
1760          */
1761         regs->trap &= ~1UL;
1762
1763 #ifdef CONFIG_PPC32
1764         regs->mq = 0;
1765         regs->nip = start;
1766         regs->msr = MSR_USER;
1767 #else
1768         if (!is_32bit_task()) {
1769                 unsigned long entry;
1770
1771                 if (is_elf2_task()) {
1772                         /* Look ma, no function descriptors! */
1773                         entry = start;
1774
1775                         /*
1776                          * Ulrich says:
1777                          *   The latest iteration of the ABI requires that when
1778                          *   calling a function (at its global entry point),
1779                          *   the caller must ensure r12 holds the entry point
1780                          *   address (so that the function can quickly
1781                          *   establish addressability).
1782                          */
1783                         regs->gpr[12] = start;
1784                         /* Make sure that's restored on entry to userspace. */
1785                         set_thread_flag(TIF_RESTOREALL);
1786                 } else {
1787                         unsigned long toc;
1788
1789                         /* start is a relocated pointer to the function
1790                          * descriptor for the elf _start routine.  The first
1791                          * entry in the function descriptor is the entry
1792                          * address of _start and the second entry is the TOC
1793                          * value we need to use.
1794                          */
1795                         __get_user(entry, (unsigned long __user *)start);
1796                         __get_user(toc, (unsigned long __user *)start+1);
1797
1798                         /* Check whether the e_entry function descriptor entries
1799                          * need to be relocated before we can use them.
1800                          */
1801                         if (load_addr != 0) {
1802                                 entry += load_addr;
1803                                 toc   += load_addr;
1804                         }
1805                         regs->gpr[2] = toc;
1806                 }
1807                 regs->nip = entry;
1808                 regs->msr = MSR_USER64;
1809         } else {
1810                 regs->nip = start;
1811                 regs->gpr[2] = 0;
1812                 regs->msr = MSR_USER32;
1813         }
1814 #endif
1815 #ifdef CONFIG_VSX
1816         current->thread.used_vsr = 0;
1817 #endif
1818         current->thread.load_fp = 0;
1819         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1820         current->thread.fp_save_area = NULL;
1821 #ifdef CONFIG_ALTIVEC
1822         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1823         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1824         current->thread.vr_save_area = NULL;
1825         current->thread.vrsave = 0;
1826         current->thread.used_vr = 0;
1827         current->thread.load_vec = 0;
1828 #endif /* CONFIG_ALTIVEC */
1829 #ifdef CONFIG_SPE
1830         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1831         current->thread.acc = 0;
1832         current->thread.spefscr = 0;
1833         current->thread.used_spe = 0;
1834 #endif /* CONFIG_SPE */
1835 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1836         current->thread.tm_tfhar = 0;
1837         current->thread.tm_texasr = 0;
1838         current->thread.tm_tfiar = 0;
1839         current->thread.load_tm = 0;
1840 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1841
1842         thread_pkey_regs_init(&current->thread);
1843 }
1844 EXPORT_SYMBOL(start_thread);
1845
1846 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1847                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1848
1849 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1850 {
1851         struct pt_regs *regs = tsk->thread.regs;
1852
1853         /* This is a bit hairy.  If we are an SPE enabled  processor
1854          * (have embedded fp) we store the IEEE exception enable flags in
1855          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1856          * mode (asyn, precise, disabled) for 'Classic' FP. */
1857         if (val & PR_FP_EXC_SW_ENABLE) {
1858 #ifdef CONFIG_SPE
1859                 if (cpu_has_feature(CPU_FTR_SPE)) {
1860                         /*
1861                          * When the sticky exception bits are set
1862                          * directly by userspace, it must call prctl
1863                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1864                          * in the existing prctl settings) or
1865                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1866                          * the bits being set).  <fenv.h> functions
1867                          * saving and restoring the whole
1868                          * floating-point environment need to do so
1869                          * anyway to restore the prctl settings from
1870                          * the saved environment.
1871                          */
1872                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1873                         tsk->thread.fpexc_mode = val &
1874                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1875                         return 0;
1876                 } else {
1877                         return -EINVAL;
1878                 }
1879 #else
1880                 return -EINVAL;
1881 #endif
1882         }
1883
1884         /* on a CONFIG_SPE this does not hurt us.  The bits that
1885          * __pack_fe01 use do not overlap with bits used for
1886          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1887          * on CONFIG_SPE implementations are reserved so writing to
1888          * them does not change anything */
1889         if (val > PR_FP_EXC_PRECISE)
1890                 return -EINVAL;
1891         tsk->thread.fpexc_mode = __pack_fe01(val);
1892         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1893                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1894                         | tsk->thread.fpexc_mode;
1895         return 0;
1896 }
1897
1898 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1899 {
1900         unsigned int val;
1901
1902         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1903 #ifdef CONFIG_SPE
1904                 if (cpu_has_feature(CPU_FTR_SPE)) {
1905                         /*
1906                          * When the sticky exception bits are set
1907                          * directly by userspace, it must call prctl
1908                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1909                          * in the existing prctl settings) or
1910                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1911                          * the bits being set).  <fenv.h> functions
1912                          * saving and restoring the whole
1913                          * floating-point environment need to do so
1914                          * anyway to restore the prctl settings from
1915                          * the saved environment.
1916                          */
1917                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1918                         val = tsk->thread.fpexc_mode;
1919                 } else
1920                         return -EINVAL;
1921 #else
1922                 return -EINVAL;
1923 #endif
1924         else
1925                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1926         return put_user(val, (unsigned int __user *) adr);
1927 }
1928
1929 int set_endian(struct task_struct *tsk, unsigned int val)
1930 {
1931         struct pt_regs *regs = tsk->thread.regs;
1932
1933         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1934             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1935                 return -EINVAL;
1936
1937         if (regs == NULL)
1938                 return -EINVAL;
1939
1940         if (val == PR_ENDIAN_BIG)
1941                 regs->msr &= ~MSR_LE;
1942         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1943                 regs->msr |= MSR_LE;
1944         else
1945                 return -EINVAL;
1946
1947         return 0;
1948 }
1949
1950 int get_endian(struct task_struct *tsk, unsigned long adr)
1951 {
1952         struct pt_regs *regs = tsk->thread.regs;
1953         unsigned int val;
1954
1955         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1956             !cpu_has_feature(CPU_FTR_REAL_LE))
1957                 return -EINVAL;
1958
1959         if (regs == NULL)
1960                 return -EINVAL;
1961
1962         if (regs->msr & MSR_LE) {
1963                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1964                         val = PR_ENDIAN_LITTLE;
1965                 else
1966                         val = PR_ENDIAN_PPC_LITTLE;
1967         } else
1968                 val = PR_ENDIAN_BIG;
1969
1970         return put_user(val, (unsigned int __user *)adr);
1971 }
1972
1973 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1974 {
1975         tsk->thread.align_ctl = val;
1976         return 0;
1977 }
1978
1979 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1980 {
1981         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1982 }
1983
1984 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1985                                   unsigned long nbytes)
1986 {
1987         unsigned long stack_page;
1988         unsigned long cpu = task_cpu(p);
1989
1990         /*
1991          * Avoid crashing if the stack has overflowed and corrupted
1992          * task_cpu(p), which is in the thread_info struct.
1993          */
1994         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1995                 stack_page = (unsigned long) hardirq_ctx[cpu];
1996                 if (sp >= stack_page + sizeof(struct thread_struct)
1997                     && sp <= stack_page + THREAD_SIZE - nbytes)
1998                         return 1;
1999
2000                 stack_page = (unsigned long) softirq_ctx[cpu];
2001                 if (sp >= stack_page + sizeof(struct thread_struct)
2002                     && sp <= stack_page + THREAD_SIZE - nbytes)
2003                         return 1;
2004         }
2005         return 0;
2006 }
2007
2008 int validate_sp(unsigned long sp, struct task_struct *p,
2009                        unsigned long nbytes)
2010 {
2011         unsigned long stack_page = (unsigned long)task_stack_page(p);
2012
2013         if (sp >= stack_page + sizeof(struct thread_struct)
2014             && sp <= stack_page + THREAD_SIZE - nbytes)
2015                 return 1;
2016
2017         return valid_irq_stack(sp, p, nbytes);
2018 }
2019
2020 EXPORT_SYMBOL(validate_sp);
2021
2022 unsigned long get_wchan(struct task_struct *p)
2023 {
2024         unsigned long ip, sp;
2025         int count = 0;
2026
2027         if (!p || p == current || p->state == TASK_RUNNING)
2028                 return 0;
2029
2030         sp = p->thread.ksp;
2031         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
2032                 return 0;
2033
2034         do {
2035                 sp = *(unsigned long *)sp;
2036                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) ||
2037                     p->state == TASK_RUNNING)
2038                         return 0;
2039                 if (count > 0) {
2040                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
2041                         if (!in_sched_functions(ip))
2042                                 return ip;
2043                 }
2044         } while (count++ < 16);
2045         return 0;
2046 }
2047
2048 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
2049
2050 void show_stack(struct task_struct *tsk, unsigned long *stack)
2051 {
2052         unsigned long sp, ip, lr, newsp;
2053         int count = 0;
2054         int firstframe = 1;
2055 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2056         int curr_frame = current->curr_ret_stack;
2057         extern void return_to_handler(void);
2058         unsigned long rth = (unsigned long)return_to_handler;
2059 #endif
2060
2061         sp = (unsigned long) stack;
2062         if (tsk == NULL)
2063                 tsk = current;
2064         if (sp == 0) {
2065                 if (tsk == current)
2066                         sp = current_stack_pointer();
2067                 else
2068                         sp = tsk->thread.ksp;
2069         }
2070
2071         lr = 0;
2072         printk("Call Trace:\n");
2073         do {
2074                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
2075                         return;
2076
2077                 stack = (unsigned long *) sp;
2078                 newsp = stack[0];
2079                 ip = stack[STACK_FRAME_LR_SAVE];
2080                 if (!firstframe || ip != lr) {
2081                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
2082 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2083                         if ((ip == rth) && curr_frame >= 0) {
2084                                 pr_cont(" (%pS)",
2085                                        (void *)current->ret_stack[curr_frame].ret);
2086                                 curr_frame--;
2087                         }
2088 #endif
2089                         if (firstframe)
2090                                 pr_cont(" (unreliable)");
2091                         pr_cont("\n");
2092                 }
2093                 firstframe = 0;
2094
2095                 /*
2096                  * See if this is an exception frame.
2097                  * We look for the "regshere" marker in the current frame.
2098                  */
2099                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
2100                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
2101                         struct pt_regs *regs = (struct pt_regs *)
2102                                 (sp + STACK_FRAME_OVERHEAD);
2103                         lr = regs->link;
2104                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
2105                                regs->trap, (void *)regs->nip, (void *)lr);
2106                         firstframe = 1;
2107                 }
2108
2109                 sp = newsp;
2110         } while (count++ < kstack_depth_to_print);
2111 }
2112
2113 #ifdef CONFIG_PPC64
2114 /* Called with hard IRQs off */
2115 void notrace __ppc64_runlatch_on(void)
2116 {
2117         struct thread_info *ti = current_thread_info();
2118
2119         if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2120                 /*
2121                  * Least significant bit (RUN) is the only writable bit of
2122                  * the CTRL register, so we can avoid mfspr. 2.06 is not the
2123                  * earliest ISA where this is the case, but it's convenient.
2124                  */
2125                 mtspr(SPRN_CTRLT, CTRL_RUNLATCH);
2126         } else {
2127                 unsigned long ctrl;
2128
2129                 /*
2130                  * Some architectures (e.g., Cell) have writable fields other
2131                  * than RUN, so do the read-modify-write.
2132                  */
2133                 ctrl = mfspr(SPRN_CTRLF);
2134                 ctrl |= CTRL_RUNLATCH;
2135                 mtspr(SPRN_CTRLT, ctrl);
2136         }
2137
2138         ti->local_flags |= _TLF_RUNLATCH;
2139 }
2140
2141 /* Called with hard IRQs off */
2142 void notrace __ppc64_runlatch_off(void)
2143 {
2144         struct thread_info *ti = current_thread_info();
2145
2146         ti->local_flags &= ~_TLF_RUNLATCH;
2147
2148         if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2149                 mtspr(SPRN_CTRLT, 0);
2150         } else {
2151                 unsigned long ctrl;
2152
2153                 ctrl = mfspr(SPRN_CTRLF);
2154                 ctrl &= ~CTRL_RUNLATCH;
2155                 mtspr(SPRN_CTRLT, ctrl);
2156         }
2157 }
2158 #endif /* CONFIG_PPC64 */
2159
2160 unsigned long arch_align_stack(unsigned long sp)
2161 {
2162         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
2163                 sp -= get_random_int() & ~PAGE_MASK;
2164         return sp & ~0xf;
2165 }
2166
2167 static inline unsigned long brk_rnd(void)
2168 {
2169         unsigned long rnd = 0;
2170
2171         /* 8MB for 32bit, 1GB for 64bit */
2172         if (is_32bit_task())
2173                 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
2174         else
2175                 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
2176
2177         return rnd << PAGE_SHIFT;
2178 }
2179
2180 unsigned long arch_randomize_brk(struct mm_struct *mm)
2181 {
2182         unsigned long base = mm->brk;
2183         unsigned long ret;
2184
2185 #ifdef CONFIG_PPC_BOOK3S_64
2186         /*
2187          * If we are using 1TB segments and we are allowed to randomise
2188          * the heap, we can put it above 1TB so it is backed by a 1TB
2189          * segment. Otherwise the heap will be in the bottom 1TB
2190          * which always uses 256MB segments and this may result in a
2191          * performance penalty. We don't need to worry about radix. For
2192          * radix, mmu_highuser_ssize remains unchanged from 256MB.
2193          */
2194         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
2195                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
2196 #endif
2197
2198         ret = PAGE_ALIGN(base + brk_rnd());
2199
2200         if (ret < mm->brk)
2201                 return mm->brk;
2202
2203         return ret;
2204 }
2205