2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
15 * This file handles the architecture-dependent parts of hardware exceptions
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/sched/debug.h>
21 #include <linux/kernel.h>
23 #include <linux/pkeys.h>
24 #include <linux/stddef.h>
25 #include <linux/unistd.h>
26 #include <linux/ptrace.h>
27 #include <linux/user.h>
28 #include <linux/interrupt.h>
29 #include <linux/init.h>
30 #include <linux/extable.h>
31 #include <linux/module.h> /* print_modules */
32 #include <linux/prctl.h>
33 #include <linux/delay.h>
34 #include <linux/kprobes.h>
35 #include <linux/kexec.h>
36 #include <linux/backlight.h>
37 #include <linux/bug.h>
38 #include <linux/kdebug.h>
39 #include <linux/ratelimit.h>
40 #include <linux/context_tracking.h>
41 #include <linux/smp.h>
42 #include <linux/console.h>
43 #include <linux/kmsg_dump.h>
45 #include <asm/emulated_ops.h>
46 #include <asm/pgtable.h>
47 #include <linux/uaccess.h>
48 #include <asm/debugfs.h>
50 #include <asm/machdep.h>
54 #ifdef CONFIG_PMAC_BACKLIGHT
55 #include <asm/backlight.h>
58 #include <asm/firmware.h>
59 #include <asm/processor.h>
62 #include <asm/kexec.h>
63 #include <asm/ppc-opcode.h>
65 #include <asm/fadump.h>
66 #include <asm/switch_to.h>
68 #include <asm/debug.h>
69 #include <asm/asm-prototypes.h>
71 #include <sysdev/fsl_pci.h>
72 #include <asm/kprobes.h>
74 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE)
75 int (*__debugger)(struct pt_regs *regs) __read_mostly;
76 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
77 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
78 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
79 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
80 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
81 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
83 EXPORT_SYMBOL(__debugger);
84 EXPORT_SYMBOL(__debugger_ipi);
85 EXPORT_SYMBOL(__debugger_bpt);
86 EXPORT_SYMBOL(__debugger_sstep);
87 EXPORT_SYMBOL(__debugger_iabr_match);
88 EXPORT_SYMBOL(__debugger_break_match);
89 EXPORT_SYMBOL(__debugger_fault_handler);
92 /* Transactional Memory trap debug */
94 #define TM_DEBUG(x...) printk(KERN_INFO x)
96 #define TM_DEBUG(x...) do { } while(0)
100 * Trap & Exception support
103 #ifdef CONFIG_PMAC_BACKLIGHT
104 static void pmac_backlight_unblank(void)
106 mutex_lock(&pmac_backlight_mutex);
107 if (pmac_backlight) {
108 struct backlight_properties *props;
110 props = &pmac_backlight->props;
111 props->brightness = props->max_brightness;
112 props->power = FB_BLANK_UNBLANK;
113 backlight_update_status(pmac_backlight);
115 mutex_unlock(&pmac_backlight_mutex);
118 static inline void pmac_backlight_unblank(void) { }
122 * If oops/die is expected to crash the machine, return true here.
124 * This should not be expected to be 100% accurate, there may be
125 * notifiers registered or other unexpected conditions that may bring
126 * down the kernel. Or if the current process in the kernel is holding
127 * locks or has other critical state, the kernel may become effectively
130 bool die_will_crash(void)
132 if (should_fadump_crash())
134 if (kexec_should_crash(current))
136 if (in_interrupt() || panic_on_oops ||
137 !current->pid || is_global_init(current))
143 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
144 static int die_owner = -1;
145 static unsigned int die_nest_count;
146 static int die_counter;
148 extern void panic_flush_kmsg_start(void)
151 * These are mostly taken from kernel/panic.c, but tries to do
152 * relatively minimal work. Don't use delay functions (TB may
153 * be broken), don't crash dump (need to set a firmware log),
154 * don't run notifiers. We do want to get some information to
161 extern void panic_flush_kmsg_end(void)
163 printk_safe_flush_on_panic();
164 kmsg_dump(KMSG_DUMP_PANIC);
167 console_flush_on_panic();
170 static unsigned long oops_begin(struct pt_regs *regs)
177 /* racy, but better than risking deadlock. */
178 raw_local_irq_save(flags);
179 cpu = smp_processor_id();
180 if (!arch_spin_trylock(&die_lock)) {
181 if (cpu == die_owner)
182 /* nested oops. should stop eventually */;
184 arch_spin_lock(&die_lock);
190 if (machine_is(powermac))
191 pmac_backlight_unblank();
194 NOKPROBE_SYMBOL(oops_begin);
196 static void oops_end(unsigned long flags, struct pt_regs *regs,
200 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
204 if (!die_nest_count) {
205 /* Nest count reaches zero, release the lock. */
207 arch_spin_unlock(&die_lock);
209 raw_local_irq_restore(flags);
212 * system_reset_excption handles debugger, crash dump, panic, for 0x100
214 if (TRAP(regs) == 0x100)
217 crash_fadump(regs, "die oops");
219 if (kexec_should_crash(current))
226 * While our oops output is serialised by a spinlock, output
227 * from panic() called below can race and corrupt it. If we
228 * know we are going to panic, delay for 1 second so we have a
229 * chance to get clean backtraces from all CPUs that are oopsing.
231 if (in_interrupt() || panic_on_oops || !current->pid ||
232 is_global_init(current)) {
233 mdelay(MSEC_PER_SEC);
237 panic("Fatal exception in interrupt");
239 panic("Fatal exception");
242 NOKPROBE_SYMBOL(oops_end);
244 static int __die(const char *str, struct pt_regs *regs, long err)
246 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
248 if (IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN))
253 if (IS_ENABLED(CONFIG_PREEMPT))
256 if (IS_ENABLED(CONFIG_SMP))
257 pr_cont("SMP NR_CPUS=%d ", NR_CPUS);
259 if (debug_pagealloc_enabled())
260 pr_cont("DEBUG_PAGEALLOC ");
262 if (IS_ENABLED(CONFIG_NUMA))
265 pr_cont("%s\n", ppc_md.name ? ppc_md.name : "");
267 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
275 NOKPROBE_SYMBOL(__die);
277 void die(const char *str, struct pt_regs *regs, long err)
282 * system_reset_excption handles debugger, crash dump, panic, for 0x100
284 if (TRAP(regs) != 0x100) {
289 flags = oops_begin(regs);
290 if (__die(str, regs, err))
292 oops_end(flags, regs, err);
294 NOKPROBE_SYMBOL(die);
296 void user_single_step_siginfo(struct task_struct *tsk,
297 struct pt_regs *regs, siginfo_t *info)
299 memset(info, 0, sizeof(*info));
300 info->si_signo = SIGTRAP;
301 info->si_code = TRAP_TRACE;
302 info->si_addr = (void __user *)regs->nip;
306 void _exception_pkey(int signr, struct pt_regs *regs, int code,
307 unsigned long addr, int key)
310 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
311 "at %08lx nip %08lx lr %08lx code %x\n";
312 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
313 "at %016lx nip %016lx lr %016lx code %x\n";
315 if (!user_mode(regs)) {
316 die("Exception in kernel mode", regs, signr);
320 if (show_unhandled_signals && unhandled_signal(current, signr)) {
321 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
322 current->comm, current->pid, signr,
323 addr, regs->nip, regs->link, code);
326 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
329 current->thread.trap_nr = code;
332 * Save all the pkey registers AMR/IAMR/UAMOR. Eg: Core dumps need
333 * to capture the content, if the task gets killed.
335 thread_pkey_regs_save(¤t->thread);
337 memset(&info, 0, sizeof(info));
338 info.si_signo = signr;
340 info.si_addr = (void __user *) addr;
343 force_sig_info(signr, &info, current);
346 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
348 _exception_pkey(signr, regs, code, addr, 0);
351 void system_reset_exception(struct pt_regs *regs)
354 * Avoid crashes in case of nested NMI exceptions. Recoverability
355 * is determined by RI and in_nmi
357 bool nested = in_nmi();
361 __this_cpu_inc(irq_stat.sreset_irqs);
363 /* See if any machine dependent calls */
364 if (ppc_md.system_reset_exception) {
365 if (ppc_md.system_reset_exception(regs))
373 * A system reset is a request to dump, so we always send
374 * it through the crashdump code (if fadump or kdump are
377 crash_fadump(regs, "System Reset");
382 * We aren't the primary crash CPU. We need to send it
383 * to a holding pattern to avoid it ending up in the panic
386 crash_kexec_secondary(regs);
389 * No debugger or crash dump registered, print logs then
392 die("System Reset", regs, SIGABRT);
394 mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */
395 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
396 nmi_panic(regs, "System Reset");
399 #ifdef CONFIG_PPC_BOOK3S_64
400 BUG_ON(get_paca()->in_nmi == 0);
401 if (get_paca()->in_nmi > 1)
402 nmi_panic(regs, "Unrecoverable nested System Reset");
404 /* Must die if the interrupt is not recoverable */
405 if (!(regs->msr & MSR_RI))
406 nmi_panic(regs, "Unrecoverable System Reset");
411 /* What should we do here? We could issue a shutdown or hard reset. */
415 * I/O accesses can cause machine checks on powermacs.
416 * Check if the NIP corresponds to the address of a sync
417 * instruction for which there is an entry in the exception
419 * Note that the 601 only takes a machine check on TEA
420 * (transfer error ack) signal assertion, and does not
421 * set any of the top 16 bits of SRR1.
424 static inline int check_io_access(struct pt_regs *regs)
427 unsigned long msr = regs->msr;
428 const struct exception_table_entry *entry;
429 unsigned int *nip = (unsigned int *)regs->nip;
431 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
432 && (entry = search_exception_tables(regs->nip)) != NULL) {
434 * Check that it's a sync instruction, or somewhere
435 * in the twi; isync; nop sequence that inb/inw/inl uses.
436 * As the address is in the exception table
437 * we should be able to read the instr there.
438 * For the debug message, we look at the preceding
441 if (*nip == PPC_INST_NOP)
443 else if (*nip == PPC_INST_ISYNC)
445 if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) {
449 rb = (*nip >> 11) & 0x1f;
450 printk(KERN_DEBUG "%s bad port %lx at %p\n",
451 (*nip & 0x100)? "OUT to": "IN from",
452 regs->gpr[rb] - _IO_BASE, nip);
454 regs->nip = extable_fixup(entry);
458 #endif /* CONFIG_PPC32 */
462 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
463 /* On 4xx, the reason for the machine check or program exception
465 #define get_reason(regs) ((regs)->dsisr)
466 #define REASON_FP ESR_FP
467 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
468 #define REASON_PRIVILEGED ESR_PPR
469 #define REASON_TRAP ESR_PTR
471 /* single-step stuff */
472 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
473 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
474 #define clear_br_trace(regs) do {} while(0)
476 /* On non-4xx, the reason for the machine check or program
477 exception is in the MSR. */
478 #define get_reason(regs) ((regs)->msr)
479 #define REASON_TM SRR1_PROGTM
480 #define REASON_FP SRR1_PROGFPE
481 #define REASON_ILLEGAL SRR1_PROGILL
482 #define REASON_PRIVILEGED SRR1_PROGPRIV
483 #define REASON_TRAP SRR1_PROGTRAP
485 #define single_stepping(regs) ((regs)->msr & MSR_SE)
486 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
487 #define clear_br_trace(regs) ((regs)->msr &= ~MSR_BE)
490 #if defined(CONFIG_E500)
491 int machine_check_e500mc(struct pt_regs *regs)
493 unsigned long mcsr = mfspr(SPRN_MCSR);
494 unsigned long pvr = mfspr(SPRN_PVR);
495 unsigned long reason = mcsr;
498 if (reason & MCSR_LD) {
499 recoverable = fsl_rio_mcheck_exception(regs);
500 if (recoverable == 1)
504 printk("Machine check in kernel mode.\n");
505 printk("Caused by (from MCSR=%lx): ", reason);
507 if (reason & MCSR_MCP)
508 printk("Machine Check Signal\n");
510 if (reason & MCSR_ICPERR) {
511 printk("Instruction Cache Parity Error\n");
514 * This is recoverable by invalidating the i-cache.
516 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
517 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
521 * This will generally be accompanied by an instruction
522 * fetch error report -- only treat MCSR_IF as fatal
523 * if it wasn't due to an L1 parity error.
528 if (reason & MCSR_DCPERR_MC) {
529 printk("Data Cache Parity Error\n");
532 * In write shadow mode we auto-recover from the error, but it
533 * may still get logged and cause a machine check. We should
534 * only treat the non-write shadow case as non-recoverable.
536 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit
537 * is not implemented but L1 data cache always runs in write
538 * shadow mode. Hence on data cache parity errors HW will
539 * automatically invalidate the L1 Data Cache.
541 if (PVR_VER(pvr) != PVR_VER_E6500) {
542 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
547 if (reason & MCSR_L2MMU_MHIT) {
548 printk("Hit on multiple TLB entries\n");
552 if (reason & MCSR_NMI)
553 printk("Non-maskable interrupt\n");
555 if (reason & MCSR_IF) {
556 printk("Instruction Fetch Error Report\n");
560 if (reason & MCSR_LD) {
561 printk("Load Error Report\n");
565 if (reason & MCSR_ST) {
566 printk("Store Error Report\n");
570 if (reason & MCSR_LDG) {
571 printk("Guarded Load Error Report\n");
575 if (reason & MCSR_TLBSYNC)
576 printk("Simultaneous tlbsync operations\n");
578 if (reason & MCSR_BSL2_ERR) {
579 printk("Level 2 Cache Error\n");
583 if (reason & MCSR_MAV) {
586 addr = mfspr(SPRN_MCAR);
587 addr |= (u64)mfspr(SPRN_MCARU) << 32;
589 printk("Machine Check %s Address: %#llx\n",
590 reason & MCSR_MEA ? "Effective" : "Physical", addr);
594 mtspr(SPRN_MCSR, mcsr);
595 return mfspr(SPRN_MCSR) == 0 && recoverable;
598 int machine_check_e500(struct pt_regs *regs)
600 unsigned long reason = mfspr(SPRN_MCSR);
602 if (reason & MCSR_BUS_RBERR) {
603 if (fsl_rio_mcheck_exception(regs))
605 if (fsl_pci_mcheck_exception(regs))
609 printk("Machine check in kernel mode.\n");
610 printk("Caused by (from MCSR=%lx): ", reason);
612 if (reason & MCSR_MCP)
613 printk("Machine Check Signal\n");
614 if (reason & MCSR_ICPERR)
615 printk("Instruction Cache Parity Error\n");
616 if (reason & MCSR_DCP_PERR)
617 printk("Data Cache Push Parity Error\n");
618 if (reason & MCSR_DCPERR)
619 printk("Data Cache Parity Error\n");
620 if (reason & MCSR_BUS_IAERR)
621 printk("Bus - Instruction Address Error\n");
622 if (reason & MCSR_BUS_RAERR)
623 printk("Bus - Read Address Error\n");
624 if (reason & MCSR_BUS_WAERR)
625 printk("Bus - Write Address Error\n");
626 if (reason & MCSR_BUS_IBERR)
627 printk("Bus - Instruction Data Error\n");
628 if (reason & MCSR_BUS_RBERR)
629 printk("Bus - Read Data Bus Error\n");
630 if (reason & MCSR_BUS_WBERR)
631 printk("Bus - Write Data Bus Error\n");
632 if (reason & MCSR_BUS_IPERR)
633 printk("Bus - Instruction Parity Error\n");
634 if (reason & MCSR_BUS_RPERR)
635 printk("Bus - Read Parity Error\n");
640 int machine_check_generic(struct pt_regs *regs)
644 #elif defined(CONFIG_E200)
645 int machine_check_e200(struct pt_regs *regs)
647 unsigned long reason = mfspr(SPRN_MCSR);
649 printk("Machine check in kernel mode.\n");
650 printk("Caused by (from MCSR=%lx): ", reason);
652 if (reason & MCSR_MCP)
653 printk("Machine Check Signal\n");
654 if (reason & MCSR_CP_PERR)
655 printk("Cache Push Parity Error\n");
656 if (reason & MCSR_CPERR)
657 printk("Cache Parity Error\n");
658 if (reason & MCSR_EXCP_ERR)
659 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
660 if (reason & MCSR_BUS_IRERR)
661 printk("Bus - Read Bus Error on instruction fetch\n");
662 if (reason & MCSR_BUS_DRERR)
663 printk("Bus - Read Bus Error on data load\n");
664 if (reason & MCSR_BUS_WRERR)
665 printk("Bus - Write Bus Error on buffered store or cache line push\n");
669 #elif defined(CONFIG_PPC32)
670 int machine_check_generic(struct pt_regs *regs)
672 unsigned long reason = regs->msr;
674 printk("Machine check in kernel mode.\n");
675 printk("Caused by (from SRR1=%lx): ", reason);
676 switch (reason & 0x601F0000) {
678 printk("Machine check signal\n");
680 case 0: /* for 601 */
682 case 0x140000: /* 7450 MSS error and TEA */
683 printk("Transfer error ack signal\n");
686 printk("Data parity error signal\n");
689 printk("Address parity error signal\n");
692 printk("L1 Data Cache error\n");
695 printk("L1 Instruction Cache error\n");
698 printk("L2 data cache parity error\n");
701 printk("Unknown values in msr\n");
705 #endif /* everything else */
707 void machine_check_exception(struct pt_regs *regs)
710 bool nested = in_nmi();
714 /* 64s accounts the mce in machine_check_early when in HVMODE */
715 if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64) || !cpu_has_feature(CPU_FTR_HVMODE))
716 __this_cpu_inc(irq_stat.mce_exceptions);
718 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
720 /* See if any machine dependent calls. In theory, we would want
721 * to call the CPU first, and call the ppc_md. one if the CPU
722 * one returns a positive number. However there is existing code
723 * that assumes the board gets a first chance, so let's keep it
724 * that way for now and fix things later. --BenH.
726 if (ppc_md.machine_check_exception)
727 recover = ppc_md.machine_check_exception(regs);
728 else if (cur_cpu_spec->machine_check)
729 recover = cur_cpu_spec->machine_check(regs);
734 if (debugger_fault_handler(regs))
737 if (check_io_access(regs))
740 die("Machine check", regs, SIGBUS);
742 /* Must die if the interrupt is not recoverable */
743 if (!(regs->msr & MSR_RI))
744 nmi_panic(regs, "Unrecoverable Machine check");
751 void SMIException(struct pt_regs *regs)
753 die("System Management Interrupt", regs, SIGABRT);
757 static void p9_hmi_special_emu(struct pt_regs *regs)
759 unsigned int ra, rb, t, i, sel, instr, rc;
760 const void __user *addr;
762 unsigned long ea, msr, msr_mask;
765 if (__get_user_inatomic(instr, (unsigned int __user *)regs->nip))
769 * lxvb16x opcode: 0x7c0006d8
770 * lxvd2x opcode: 0x7c000698
771 * lxvh8x opcode: 0x7c000658
772 * lxvw4x opcode: 0x7c000618
774 if ((instr & 0xfc00073e) != 0x7c000618) {
775 pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx"
777 smp_processor_id(), current->comm, current->pid,
782 /* Grab vector registers into the task struct */
783 msr = regs->msr; /* Grab msr before we flush the bits */
784 flush_vsx_to_thread(current);
785 enable_kernel_altivec();
788 * Is userspace running with a different endian (this is rare but
791 swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
793 /* Decode the instruction */
794 ra = (instr >> 16) & 0x1f;
795 rb = (instr >> 11) & 0x1f;
796 t = (instr >> 21) & 0x1f;
798 vdst = (u8 *)¤t->thread.vr_state.vr[t];
800 vdst = (u8 *)¤t->thread.fp_state.fpr[t][0];
802 /* Grab the vector address */
803 ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0);
806 addr = (__force const void __user *)ea;
809 if (!access_ok(VERIFY_READ, addr, 16)) {
810 pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx"
811 " instr=%08x addr=%016lx\n",
812 smp_processor_id(), current->comm, current->pid,
813 regs->nip, instr, (unsigned long)addr);
817 /* Read the vector */
819 if ((unsigned long)addr & 0xfUL)
821 rc = __copy_from_user_inatomic(vbuf, addr, 16);
823 __get_user_atomic_128_aligned(vbuf, addr, rc);
825 pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx"
826 " instr=%08x addr=%016lx\n",
827 smp_processor_id(), current->comm, current->pid,
828 regs->nip, instr, (unsigned long)addr);
832 pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx"
833 " instr=%08x addr=%016lx\n",
834 smp_processor_id(), current->comm, current->pid, regs->nip,
835 instr, (unsigned long) addr);
837 /* Grab instruction "selector" */
838 sel = (instr >> 6) & 3;
841 * Check to make sure the facility is actually enabled. This
842 * could happen if we get a false positive hit.
844 * lxvd2x/lxvw4x always check MSR VSX sel = 0,2
845 * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3
848 if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */
850 if (!(msr & msr_mask)) {
851 pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx"
852 " instr=%08x msr:%016lx\n",
853 smp_processor_id(), current->comm, current->pid,
854 regs->nip, instr, msr);
858 /* Do logging here before we modify sel based on endian */
861 PPC_WARN_EMULATED(lxvw4x, regs);
864 PPC_WARN_EMULATED(lxvh8x, regs);
867 PPC_WARN_EMULATED(lxvd2x, regs);
869 case 3: /* lxvb16x */
870 PPC_WARN_EMULATED(lxvb16x, regs);
874 #ifdef __LITTLE_ENDIAN__
876 * An LE kernel stores the vector in the task struct as an LE
877 * byte array (effectively swapping both the components and
878 * the content of the components). Those instructions expect
879 * the components to remain in ascending address order, so we
882 * If we are running a BE user space, the expectation is that
883 * of a simple memcpy, so forcing the emulation to look like
884 * a lxvb16x should do the trick.
891 for (i = 0; i < 4; i++)
892 ((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i];
895 for (i = 0; i < 8; i++)
896 ((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i];
899 for (i = 0; i < 2; i++)
900 ((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i];
902 case 3: /* lxvb16x */
903 for (i = 0; i < 16; i++)
904 vdst[i] = vbuf[15-i];
907 #else /* __LITTLE_ENDIAN__ */
908 /* On a big endian kernel, a BE userspace only needs a memcpy */
912 /* Otherwise, we need to swap the content of the components */
915 for (i = 0; i < 4; i++)
916 ((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]);
919 for (i = 0; i < 8; i++)
920 ((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]);
923 for (i = 0; i < 2; i++)
924 ((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]);
926 case 3: /* lxvb16x */
927 memcpy(vdst, vbuf, 16);
930 #endif /* !__LITTLE_ENDIAN__ */
932 /* Go to next instruction */
935 #endif /* CONFIG_VSX */
937 void handle_hmi_exception(struct pt_regs *regs)
939 struct pt_regs *old_regs;
941 old_regs = set_irq_regs(regs);
945 /* Real mode flagged P9 special emu is needed */
946 if (local_paca->hmi_p9_special_emu) {
947 local_paca->hmi_p9_special_emu = 0;
950 * We don't want to take page faults while doing the
951 * emulation, we just replay the instruction if necessary.
954 p9_hmi_special_emu(regs);
957 #endif /* CONFIG_VSX */
959 if (ppc_md.handle_hmi_exception)
960 ppc_md.handle_hmi_exception(regs);
963 set_irq_regs(old_regs);
966 void unknown_exception(struct pt_regs *regs)
968 enum ctx_state prev_state = exception_enter();
970 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
971 regs->nip, regs->msr, regs->trap);
973 _exception(SIGTRAP, regs, TRAP_FIXME, 0);
975 exception_exit(prev_state);
978 void instruction_breakpoint_exception(struct pt_regs *regs)
980 enum ctx_state prev_state = exception_enter();
982 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
983 5, SIGTRAP) == NOTIFY_STOP)
985 if (debugger_iabr_match(regs))
987 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
990 exception_exit(prev_state);
993 void RunModeException(struct pt_regs *regs)
995 _exception(SIGTRAP, regs, TRAP_FIXME, 0);
998 void single_step_exception(struct pt_regs *regs)
1000 enum ctx_state prev_state = exception_enter();
1002 clear_single_step(regs);
1003 clear_br_trace(regs);
1005 if (kprobe_post_handler(regs))
1008 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1009 5, SIGTRAP) == NOTIFY_STOP)
1011 if (debugger_sstep(regs))
1014 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1017 exception_exit(prev_state);
1019 NOKPROBE_SYMBOL(single_step_exception);
1022 * After we have successfully emulated an instruction, we have to
1023 * check if the instruction was being single-stepped, and if so,
1024 * pretend we got a single-step exception. This was pointed out
1025 * by Kumar Gala. -- paulus
1027 static void emulate_single_step(struct pt_regs *regs)
1029 if (single_stepping(regs))
1030 single_step_exception(regs);
1033 static inline int __parse_fpscr(unsigned long fpscr)
1035 int ret = FPE_FIXME;
1037 /* Invalid operation */
1038 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
1042 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
1046 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
1049 /* Divide by zero */
1050 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
1053 /* Inexact result */
1054 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
1060 static void parse_fpe(struct pt_regs *regs)
1064 flush_fp_to_thread(current);
1066 code = __parse_fpscr(current->thread.fp_state.fpscr);
1068 _exception(SIGFPE, regs, code, regs->nip);
1072 * Illegal instruction emulation support. Originally written to
1073 * provide the PVR to user applications using the mfspr rd, PVR.
1074 * Return non-zero if we can't emulate, or -EFAULT if the associated
1075 * memory access caused an access fault. Return zero on success.
1077 * There are a couple of ways to do this, either "decode" the instruction
1078 * or directly match lots of bits. In this case, matching lots of
1079 * bits is faster and easier.
1082 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
1084 u8 rT = (instword >> 21) & 0x1f;
1085 u8 rA = (instword >> 16) & 0x1f;
1086 u8 NB_RB = (instword >> 11) & 0x1f;
1091 /* Early out if we are an invalid form of lswx */
1092 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
1093 if ((rT == rA) || (rT == NB_RB))
1096 EA = (rA == 0) ? 0 : regs->gpr[rA];
1098 switch (instword & PPC_INST_STRING_MASK) {
1100 case PPC_INST_STSWX:
1102 num_bytes = regs->xer & 0x7f;
1105 case PPC_INST_STSWI:
1106 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
1112 while (num_bytes != 0)
1115 u32 shift = 8 * (3 - (pos & 0x3));
1117 /* if process is 32-bit, clear upper 32 bits of EA */
1118 if ((regs->msr & MSR_64BIT) == 0)
1121 switch ((instword & PPC_INST_STRING_MASK)) {
1124 if (get_user(val, (u8 __user *)EA))
1126 /* first time updating this reg,
1130 regs->gpr[rT] |= val << shift;
1132 case PPC_INST_STSWI:
1133 case PPC_INST_STSWX:
1134 val = regs->gpr[rT] >> shift;
1135 if (put_user(val, (u8 __user *)EA))
1139 /* move EA to next address */
1143 /* manage our position within the register */
1154 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
1159 ra = (instword >> 16) & 0x1f;
1160 rs = (instword >> 21) & 0x1f;
1162 tmp = regs->gpr[rs];
1163 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
1164 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
1165 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1166 regs->gpr[ra] = tmp;
1171 static int emulate_isel(struct pt_regs *regs, u32 instword)
1173 u8 rT = (instword >> 21) & 0x1f;
1174 u8 rA = (instword >> 16) & 0x1f;
1175 u8 rB = (instword >> 11) & 0x1f;
1176 u8 BC = (instword >> 6) & 0x1f;
1180 tmp = (rA == 0) ? 0 : regs->gpr[rA];
1181 bit = (regs->ccr >> (31 - BC)) & 0x1;
1183 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
1188 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1189 static inline bool tm_abort_check(struct pt_regs *regs, int cause)
1191 /* If we're emulating a load/store in an active transaction, we cannot
1192 * emulate it as the kernel operates in transaction suspended context.
1193 * We need to abort the transaction. This creates a persistent TM
1194 * abort so tell the user what caused it with a new code.
1196 if (MSR_TM_TRANSACTIONAL(regs->msr)) {
1204 static inline bool tm_abort_check(struct pt_regs *regs, int reason)
1210 static int emulate_instruction(struct pt_regs *regs)
1215 if (!user_mode(regs))
1217 CHECK_FULL_REGS(regs);
1219 if (get_user(instword, (u32 __user *)(regs->nip)))
1222 /* Emulate the mfspr rD, PVR. */
1223 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
1224 PPC_WARN_EMULATED(mfpvr, regs);
1225 rd = (instword >> 21) & 0x1f;
1226 regs->gpr[rd] = mfspr(SPRN_PVR);
1230 /* Emulating the dcba insn is just a no-op. */
1231 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
1232 PPC_WARN_EMULATED(dcba, regs);
1236 /* Emulate the mcrxr insn. */
1237 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
1238 int shift = (instword >> 21) & 0x1c;
1239 unsigned long msk = 0xf0000000UL >> shift;
1241 PPC_WARN_EMULATED(mcrxr, regs);
1242 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
1243 regs->xer &= ~0xf0000000UL;
1247 /* Emulate load/store string insn. */
1248 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
1249 if (tm_abort_check(regs,
1250 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
1252 PPC_WARN_EMULATED(string, regs);
1253 return emulate_string_inst(regs, instword);
1256 /* Emulate the popcntb (Population Count Bytes) instruction. */
1257 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
1258 PPC_WARN_EMULATED(popcntb, regs);
1259 return emulate_popcntb_inst(regs, instword);
1262 /* Emulate isel (Integer Select) instruction */
1263 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
1264 PPC_WARN_EMULATED(isel, regs);
1265 return emulate_isel(regs, instword);
1268 /* Emulate sync instruction variants */
1269 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) {
1270 PPC_WARN_EMULATED(sync, regs);
1271 asm volatile("sync");
1276 /* Emulate the mfspr rD, DSCR. */
1277 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
1278 PPC_INST_MFSPR_DSCR_USER) ||
1279 ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
1280 PPC_INST_MFSPR_DSCR)) &&
1281 cpu_has_feature(CPU_FTR_DSCR)) {
1282 PPC_WARN_EMULATED(mfdscr, regs);
1283 rd = (instword >> 21) & 0x1f;
1284 regs->gpr[rd] = mfspr(SPRN_DSCR);
1287 /* Emulate the mtspr DSCR, rD. */
1288 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
1289 PPC_INST_MTSPR_DSCR_USER) ||
1290 ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
1291 PPC_INST_MTSPR_DSCR)) &&
1292 cpu_has_feature(CPU_FTR_DSCR)) {
1293 PPC_WARN_EMULATED(mtdscr, regs);
1294 rd = (instword >> 21) & 0x1f;
1295 current->thread.dscr = regs->gpr[rd];
1296 current->thread.dscr_inherit = 1;
1297 mtspr(SPRN_DSCR, current->thread.dscr);
1305 int is_valid_bugaddr(unsigned long addr)
1307 return is_kernel_addr(addr);
1310 #ifdef CONFIG_MATH_EMULATION
1311 static int emulate_math(struct pt_regs *regs)
1314 extern int do_mathemu(struct pt_regs *regs);
1316 ret = do_mathemu(regs);
1318 PPC_WARN_EMULATED(math, regs);
1322 emulate_single_step(regs);
1326 code = __parse_fpscr(current->thread.fp_state.fpscr);
1327 _exception(SIGFPE, regs, code, regs->nip);
1331 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1338 static inline int emulate_math(struct pt_regs *regs) { return -1; }
1341 void program_check_exception(struct pt_regs *regs)
1343 enum ctx_state prev_state = exception_enter();
1344 unsigned int reason = get_reason(regs);
1346 /* We can now get here via a FP Unavailable exception if the core
1347 * has no FPU, in that case the reason flags will be 0 */
1349 if (reason & REASON_FP) {
1350 /* IEEE FP exception */
1354 if (reason & REASON_TRAP) {
1355 unsigned long bugaddr;
1356 /* Debugger is first in line to stop recursive faults in
1357 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1358 if (debugger_bpt(regs))
1361 if (kprobe_handler(regs))
1364 /* trap exception */
1365 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1369 bugaddr = regs->nip;
1371 * Fixup bugaddr for BUG_ON() in real mode
1373 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR))
1374 bugaddr += PAGE_OFFSET;
1376 if (!(regs->msr & MSR_PR) && /* not user-mode */
1377 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) {
1381 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1384 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1385 if (reason & REASON_TM) {
1386 /* This is a TM "Bad Thing Exception" program check.
1388 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1389 * transition in TM states.
1390 * - A trechkpt is attempted when transactional.
1391 * - A treclaim is attempted when non transactional.
1392 * - A tend is illegally attempted.
1393 * - writing a TM SPR when transactional.
1395 * If usermode caused this, it's done something illegal and
1396 * gets a SIGILL slap on the wrist. We call it an illegal
1397 * operand to distinguish from the instruction just being bad
1398 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1399 * illegal /placement/ of a valid instruction.
1401 if (user_mode(regs)) {
1402 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
1405 printk(KERN_EMERG "Unexpected TM Bad Thing exception "
1406 "at %lx (msr 0x%x)\n", regs->nip, reason);
1407 die("Unrecoverable exception", regs, SIGABRT);
1413 * If we took the program check in the kernel skip down to sending a
1414 * SIGILL. The subsequent cases all relate to emulating instructions
1415 * which we should only do for userspace. We also do not want to enable
1416 * interrupts for kernel faults because that might lead to further
1417 * faults, and loose the context of the original exception.
1419 if (!user_mode(regs))
1422 /* We restore the interrupt state now */
1423 if (!arch_irq_disabled_regs(regs))
1426 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1427 * but there seems to be a hardware bug on the 405GP (RevD)
1428 * that means ESR is sometimes set incorrectly - either to
1429 * ESR_DST (!?) or 0. In the process of chasing this with the
1430 * hardware people - not sure if it can happen on any illegal
1431 * instruction or only on FP instructions, whether there is a
1432 * pattern to occurrences etc. -dgibson 31/Mar/2003
1434 if (!emulate_math(regs))
1437 /* Try to emulate it if we should. */
1438 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
1439 switch (emulate_instruction(regs)) {
1442 emulate_single_step(regs);
1445 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1451 if (reason & REASON_PRIVILEGED)
1452 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1454 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1457 exception_exit(prev_state);
1459 NOKPROBE_SYMBOL(program_check_exception);
1462 * This occurs when running in hypervisor mode on POWER6 or later
1463 * and an illegal instruction is encountered.
1465 void emulation_assist_interrupt(struct pt_regs *regs)
1467 regs->msr |= REASON_ILLEGAL;
1468 program_check_exception(regs);
1470 NOKPROBE_SYMBOL(emulation_assist_interrupt);
1472 void alignment_exception(struct pt_regs *regs)
1474 enum ctx_state prev_state = exception_enter();
1475 int sig, code, fixed = 0;
1477 /* We restore the interrupt state now */
1478 if (!arch_irq_disabled_regs(regs))
1481 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
1484 /* we don't implement logging of alignment exceptions */
1485 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1486 fixed = fix_alignment(regs);
1489 regs->nip += 4; /* skip over emulated instruction */
1490 emulate_single_step(regs);
1494 /* Operand address was bad */
1495 if (fixed == -EFAULT) {
1502 if (user_mode(regs))
1503 _exception(sig, regs, code, regs->dar);
1505 bad_page_fault(regs, regs->dar, sig);
1508 exception_exit(prev_state);
1511 void StackOverflow(struct pt_regs *regs)
1513 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
1514 current, regs->gpr[1]);
1517 panic("kernel stack overflow");
1520 void nonrecoverable_exception(struct pt_regs *regs)
1522 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
1523 regs->nip, regs->msr);
1525 die("nonrecoverable exception", regs, SIGKILL);
1528 void kernel_fp_unavailable_exception(struct pt_regs *regs)
1530 enum ctx_state prev_state = exception_enter();
1532 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1533 "%lx at %lx\n", regs->trap, regs->nip);
1534 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1536 exception_exit(prev_state);
1539 void altivec_unavailable_exception(struct pt_regs *regs)
1541 enum ctx_state prev_state = exception_enter();
1543 if (user_mode(regs)) {
1544 /* A user program has executed an altivec instruction,
1545 but this kernel doesn't support altivec. */
1546 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1550 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1551 "%lx at %lx\n", regs->trap, regs->nip);
1552 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1555 exception_exit(prev_state);
1558 void vsx_unavailable_exception(struct pt_regs *regs)
1560 if (user_mode(regs)) {
1561 /* A user program has executed an vsx instruction,
1562 but this kernel doesn't support vsx. */
1563 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1567 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1568 "%lx at %lx\n", regs->trap, regs->nip);
1569 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1573 static void tm_unavailable(struct pt_regs *regs)
1575 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1576 if (user_mode(regs)) {
1577 current->thread.load_tm++;
1578 regs->msr |= MSR_TM;
1580 tm_restore_sprs(¤t->thread);
1584 pr_emerg("Unrecoverable TM Unavailable Exception "
1585 "%lx at %lx\n", regs->trap, regs->nip);
1586 die("Unrecoverable TM Unavailable Exception", regs, SIGABRT);
1589 void facility_unavailable_exception(struct pt_regs *regs)
1591 static char *facility_strings[] = {
1592 [FSCR_FP_LG] = "FPU",
1593 [FSCR_VECVSX_LG] = "VMX/VSX",
1594 [FSCR_DSCR_LG] = "DSCR",
1595 [FSCR_PM_LG] = "PMU SPRs",
1596 [FSCR_BHRB_LG] = "BHRB",
1597 [FSCR_TM_LG] = "TM",
1598 [FSCR_EBB_LG] = "EBB",
1599 [FSCR_TAR_LG] = "TAR",
1600 [FSCR_MSGP_LG] = "MSGP",
1601 [FSCR_SCV_LG] = "SCV",
1603 char *facility = "unknown";
1609 hv = (TRAP(regs) == 0xf80);
1611 value = mfspr(SPRN_HFSCR);
1613 value = mfspr(SPRN_FSCR);
1615 status = value >> 56;
1616 if (status == FSCR_DSCR_LG) {
1618 * User is accessing the DSCR register using the problem
1619 * state only SPR number (0x03) either through a mfspr or
1620 * a mtspr instruction. If it is a write attempt through
1621 * a mtspr, then we set the inherit bit. This also allows
1622 * the user to write or read the register directly in the
1623 * future by setting via the FSCR DSCR bit. But in case it
1624 * is a read DSCR attempt through a mfspr instruction, we
1625 * just emulate the instruction instead. This code path will
1626 * always emulate all the mfspr instructions till the user
1627 * has attempted at least one mtspr instruction. This way it
1628 * preserves the same behaviour when the user is accessing
1629 * the DSCR through privilege level only SPR number (0x11)
1630 * which is emulated through illegal instruction exception.
1631 * We always leave HFSCR DSCR set.
1633 if (get_user(instword, (u32 __user *)(regs->nip))) {
1634 pr_err("Failed to fetch the user instruction\n");
1638 /* Write into DSCR (mtspr 0x03, RS) */
1639 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK)
1640 == PPC_INST_MTSPR_DSCR_USER) {
1641 rd = (instword >> 21) & 0x1f;
1642 current->thread.dscr = regs->gpr[rd];
1643 current->thread.dscr_inherit = 1;
1644 current->thread.fscr |= FSCR_DSCR;
1645 mtspr(SPRN_FSCR, current->thread.fscr);
1648 /* Read from DSCR (mfspr RT, 0x03) */
1649 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK)
1650 == PPC_INST_MFSPR_DSCR_USER) {
1651 if (emulate_instruction(regs)) {
1652 pr_err("DSCR based mfspr emulation failed\n");
1656 emulate_single_step(regs);
1661 if (status == FSCR_TM_LG) {
1663 * If we're here then the hardware is TM aware because it
1664 * generated an exception with FSRM_TM set.
1666 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware
1667 * told us not to do TM, or the kernel is not built with TM
1670 * If both of those things are true, then userspace can spam the
1671 * console by triggering the printk() below just by continually
1672 * doing tbegin (or any TM instruction). So in that case just
1673 * send the process a SIGILL immediately.
1675 if (!cpu_has_feature(CPU_FTR_TM))
1678 tm_unavailable(regs);
1682 if ((hv || status >= 2) &&
1683 (status < ARRAY_SIZE(facility_strings)) &&
1684 facility_strings[status])
1685 facility = facility_strings[status];
1687 /* We restore the interrupt state now */
1688 if (!arch_irq_disabled_regs(regs))
1691 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n",
1692 hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr);
1695 if (user_mode(regs)) {
1696 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1700 die("Unexpected facility unavailable exception", regs, SIGABRT);
1704 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1706 void fp_unavailable_tm(struct pt_regs *regs)
1708 /* Note: This does not handle any kind of FP laziness. */
1710 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1711 regs->nip, regs->msr);
1713 /* We can only have got here if the task started using FP after
1714 * beginning the transaction. So, the transactional regs are just a
1715 * copy of the checkpointed ones. But, we still need to recheckpoint
1716 * as we're enabling FP for the process; it will return, abort the
1717 * transaction, and probably retry but now with FP enabled. So the
1718 * checkpointed FP registers need to be loaded.
1720 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1721 /* Reclaim didn't save out any FPRs to transact_fprs. */
1723 /* Enable FP for the task: */
1724 current->thread.load_fp = 1;
1726 /* This loads and recheckpoints the FP registers from
1727 * thread.fpr[]. They will remain in registers after the
1728 * checkpoint so we don't need to reload them after.
1729 * If VMX is in use, the VRs now hold checkpointed values,
1730 * so we don't want to load the VRs from the thread_struct.
1732 tm_recheckpoint(¤t->thread);
1735 void altivec_unavailable_tm(struct pt_regs *regs)
1737 /* See the comments in fp_unavailable_tm(). This function operates
1741 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1743 regs->nip, regs->msr);
1744 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1745 current->thread.load_vec = 1;
1746 tm_recheckpoint(¤t->thread);
1747 current->thread.used_vr = 1;
1750 void vsx_unavailable_tm(struct pt_regs *regs)
1752 /* See the comments in fp_unavailable_tm(). This works similarly,
1753 * though we're loading both FP and VEC registers in here.
1755 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1756 * regs. Either way, set MSR_VSX.
1759 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1761 regs->nip, regs->msr);
1763 current->thread.used_vsr = 1;
1765 /* This reclaims FP and/or VR regs if they're already enabled */
1766 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1768 current->thread.load_vec = 1;
1769 current->thread.load_fp = 1;
1771 tm_recheckpoint(¤t->thread);
1773 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1775 void performance_monitor_exception(struct pt_regs *regs)
1777 __this_cpu_inc(irq_stat.pmu_irqs);
1782 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1783 static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1787 * Determine the cause of the debug event, clear the
1788 * event flags and send a trap to the handler. Torez
1790 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1791 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1792 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1793 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
1795 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status,
1798 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1799 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1800 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status,
1803 } else if (debug_status & DBSR_IAC1) {
1804 current->thread.debug.dbcr0 &= ~DBCR0_IAC1;
1805 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1806 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status,
1809 } else if (debug_status & DBSR_IAC2) {
1810 current->thread.debug.dbcr0 &= ~DBCR0_IAC2;
1811 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status,
1814 } else if (debug_status & DBSR_IAC3) {
1815 current->thread.debug.dbcr0 &= ~DBCR0_IAC3;
1816 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1817 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status,
1820 } else if (debug_status & DBSR_IAC4) {
1821 current->thread.debug.dbcr0 &= ~DBCR0_IAC4;
1822 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status,
1827 * At the point this routine was called, the MSR(DE) was turned off.
1828 * Check all other debug flags and see if that bit needs to be turned
1831 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1832 current->thread.debug.dbcr1))
1833 regs->msr |= MSR_DE;
1835 /* Make sure the IDM flag is off */
1836 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1839 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0);
1842 void DebugException(struct pt_regs *regs, unsigned long debug_status)
1844 current->thread.debug.dbsr = debug_status;
1846 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1847 * on server, it stops on the target of the branch. In order to simulate
1848 * the server behaviour, we thus restart right away with a single step
1849 * instead of stopping here when hitting a BT
1851 if (debug_status & DBSR_BT) {
1852 regs->msr &= ~MSR_DE;
1855 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1856 /* Clear the BT event */
1857 mtspr(SPRN_DBSR, DBSR_BT);
1859 /* Do the single step trick only when coming from userspace */
1860 if (user_mode(regs)) {
1861 current->thread.debug.dbcr0 &= ~DBCR0_BT;
1862 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1863 regs->msr |= MSR_DE;
1867 if (kprobe_post_handler(regs))
1870 if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1871 5, SIGTRAP) == NOTIFY_STOP) {
1874 if (debugger_sstep(regs))
1876 } else if (debug_status & DBSR_IC) { /* Instruction complete */
1877 regs->msr &= ~MSR_DE;
1879 /* Disable instruction completion */
1880 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
1881 /* Clear the instruction completion event */
1882 mtspr(SPRN_DBSR, DBSR_IC);
1884 if (kprobe_post_handler(regs))
1887 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1888 5, SIGTRAP) == NOTIFY_STOP) {
1892 if (debugger_sstep(regs))
1895 if (user_mode(regs)) {
1896 current->thread.debug.dbcr0 &= ~DBCR0_IC;
1897 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1898 current->thread.debug.dbcr1))
1899 regs->msr |= MSR_DE;
1901 /* Make sure the IDM bit is off */
1902 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1905 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1907 handle_debug(regs, debug_status);
1909 NOKPROBE_SYMBOL(DebugException);
1910 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1912 #if !defined(CONFIG_TAU_INT)
1913 void TAUException(struct pt_regs *regs)
1915 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1916 regs->nip, regs->msr, regs->trap, print_tainted());
1918 #endif /* CONFIG_INT_TAU */
1920 #ifdef CONFIG_ALTIVEC
1921 void altivec_assist_exception(struct pt_regs *regs)
1925 if (!user_mode(regs)) {
1926 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
1927 " at %lx\n", regs->nip);
1928 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
1931 flush_altivec_to_thread(current);
1933 PPC_WARN_EMULATED(altivec, regs);
1934 err = emulate_altivec(regs);
1936 regs->nip += 4; /* skip emulated instruction */
1937 emulate_single_step(regs);
1941 if (err == -EFAULT) {
1942 /* got an error reading the instruction */
1943 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1945 /* didn't recognize the instruction */
1946 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1947 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
1948 "in %s at %lx\n", current->comm, regs->nip);
1949 current->thread.vr_state.vscr.u[3] |= 0x10000;
1952 #endif /* CONFIG_ALTIVEC */
1954 #ifdef CONFIG_FSL_BOOKE
1955 void CacheLockingException(struct pt_regs *regs, unsigned long address,
1956 unsigned long error_code)
1958 /* We treat cache locking instructions from the user
1959 * as priv ops, in the future we could try to do
1962 if (error_code & (ESR_DLK|ESR_ILK))
1963 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1966 #endif /* CONFIG_FSL_BOOKE */
1969 void SPEFloatingPointException(struct pt_regs *regs)
1971 extern int do_spe_mathemu(struct pt_regs *regs);
1972 unsigned long spefscr;
1974 int code = FPE_FIXME;
1977 flush_spe_to_thread(current);
1979 spefscr = current->thread.spefscr;
1980 fpexc_mode = current->thread.fpexc_mode;
1982 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1985 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1988 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1990 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1993 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1996 err = do_spe_mathemu(regs);
1998 regs->nip += 4; /* skip emulated instruction */
1999 emulate_single_step(regs);
2003 if (err == -EFAULT) {
2004 /* got an error reading the instruction */
2005 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
2006 } else if (err == -EINVAL) {
2007 /* didn't recognize the instruction */
2008 printk(KERN_ERR "unrecognized spe instruction "
2009 "in %s at %lx\n", current->comm, regs->nip);
2011 _exception(SIGFPE, regs, code, regs->nip);
2017 void SPEFloatingPointRoundException(struct pt_regs *regs)
2019 extern int speround_handler(struct pt_regs *regs);
2023 if (regs->msr & MSR_SPE)
2024 giveup_spe(current);
2028 err = speround_handler(regs);
2030 regs->nip += 4; /* skip emulated instruction */
2031 emulate_single_step(regs);
2035 if (err == -EFAULT) {
2036 /* got an error reading the instruction */
2037 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
2038 } else if (err == -EINVAL) {
2039 /* didn't recognize the instruction */
2040 printk(KERN_ERR "unrecognized spe instruction "
2041 "in %s at %lx\n", current->comm, regs->nip);
2043 _exception(SIGFPE, regs, FPE_FIXME, regs->nip);
2050 * We enter here if we get an unrecoverable exception, that is, one
2051 * that happened at a point where the RI (recoverable interrupt) bit
2052 * in the MSR is 0. This indicates that SRR0/1 are live, and that
2053 * we therefore lost state by taking this exception.
2055 void unrecoverable_exception(struct pt_regs *regs)
2057 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
2058 regs->trap, regs->nip);
2059 die("Unrecoverable exception", regs, SIGABRT);
2061 NOKPROBE_SYMBOL(unrecoverable_exception);
2063 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
2065 * Default handler for a Watchdog exception,
2066 * spins until a reboot occurs
2068 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
2070 /* Generic WatchdogHandler, implement your own */
2071 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
2075 void WatchdogException(struct pt_regs *regs)
2077 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
2078 WatchdogHandler(regs);
2083 * We enter here if we discover during exception entry that we are
2084 * running in supervisor mode with a userspace value in the stack pointer.
2086 void kernel_bad_stack(struct pt_regs *regs)
2088 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
2089 regs->gpr[1], regs->nip);
2090 die("Bad kernel stack pointer", regs, SIGABRT);
2092 NOKPROBE_SYMBOL(kernel_bad_stack);
2094 void __init trap_init(void)
2099 #ifdef CONFIG_PPC_EMULATED_STATS
2101 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
2103 struct ppc_emulated ppc_emulated = {
2104 #ifdef CONFIG_ALTIVEC
2105 WARN_EMULATED_SETUP(altivec),
2107 WARN_EMULATED_SETUP(dcba),
2108 WARN_EMULATED_SETUP(dcbz),
2109 WARN_EMULATED_SETUP(fp_pair),
2110 WARN_EMULATED_SETUP(isel),
2111 WARN_EMULATED_SETUP(mcrxr),
2112 WARN_EMULATED_SETUP(mfpvr),
2113 WARN_EMULATED_SETUP(multiple),
2114 WARN_EMULATED_SETUP(popcntb),
2115 WARN_EMULATED_SETUP(spe),
2116 WARN_EMULATED_SETUP(string),
2117 WARN_EMULATED_SETUP(sync),
2118 WARN_EMULATED_SETUP(unaligned),
2119 #ifdef CONFIG_MATH_EMULATION
2120 WARN_EMULATED_SETUP(math),
2123 WARN_EMULATED_SETUP(vsx),
2126 WARN_EMULATED_SETUP(mfdscr),
2127 WARN_EMULATED_SETUP(mtdscr),
2128 WARN_EMULATED_SETUP(lq_stq),
2129 WARN_EMULATED_SETUP(lxvw4x),
2130 WARN_EMULATED_SETUP(lxvh8x),
2131 WARN_EMULATED_SETUP(lxvd2x),
2132 WARN_EMULATED_SETUP(lxvb16x),
2136 u32 ppc_warn_emulated;
2138 void ppc_warn_emulated_print(const char *type)
2140 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
2144 static int __init ppc_warn_emulated_init(void)
2146 struct dentry *dir, *d;
2148 struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
2150 if (!powerpc_debugfs_root)
2153 dir = debugfs_create_dir("emulated_instructions",
2154 powerpc_debugfs_root);
2158 d = debugfs_create_u32("do_warn", 0644, dir,
2159 &ppc_warn_emulated);
2163 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
2164 d = debugfs_create_u32(entries[i].name, 0644, dir,
2165 (u32 *)&entries[i].val.counter);
2173 debugfs_remove_recursive(dir);
2177 device_initcall(ppc_warn_emulated_init);
2179 #endif /* CONFIG_PPC_EMULATED_STATS */