2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * Copyright 2010-2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
9 #include <linux/types.h>
10 #include <linux/string.h>
11 #include <linux/kvm.h>
12 #include <linux/kvm_host.h>
13 #include <linux/hugetlb.h>
14 #include <linux/module.h>
15 #include <linux/log2.h>
17 #include <asm/tlbflush.h>
18 #include <asm/trace.h>
19 #include <asm/kvm_ppc.h>
20 #include <asm/kvm_book3s.h>
21 #include <asm/book3s/64/mmu-hash.h>
22 #include <asm/hvcall.h>
23 #include <asm/synch.h>
24 #include <asm/ppc-opcode.h>
25 #include <asm/pte-walk.h>
27 /* Translate address of a vmalloc'd thing to a linear map address */
28 static void *real_vmalloc_addr(void *x)
30 unsigned long addr = (unsigned long) x;
33 * assume we don't have huge pages in vmalloc space...
34 * So don't worry about THP collapse/split. Called
35 * Only in realmode with MSR_EE = 0, hence won't need irq_save/restore.
37 p = find_init_mm_pte(addr, NULL);
38 if (!p || !pte_present(*p))
40 addr = (pte_pfn(*p) << PAGE_SHIFT) | (addr & ~PAGE_MASK);
44 /* Return 1 if we need to do a global tlbie, 0 if we can use tlbiel */
45 static int global_invalidates(struct kvm *kvm)
51 * If there is only one vcore, and it's currently running,
52 * as indicated by local_paca->kvm_hstate.kvm_vcpu being set,
53 * we can use tlbiel as long as we mark all other physical
54 * cores as potentially having stale TLB entries for this lpid.
55 * Otherwise, don't use tlbiel.
57 if (kvm->arch.online_vcores == 1 && local_paca->kvm_hstate.kvm_vcpu)
63 /* any other core might now have stale TLB entries... */
65 cpumask_setall(&kvm->arch.need_tlb_flush);
66 cpu = local_paca->kvm_hstate.kvm_vcore->pcpu;
68 * On POWER9, threads are independent but the TLB is shared,
69 * so use the bit for the first thread to represent the core.
71 if (cpu_has_feature(CPU_FTR_ARCH_300))
72 cpu = cpu_first_thread_sibling(cpu);
73 cpumask_clear_cpu(cpu, &kvm->arch.need_tlb_flush);
80 * Add this HPTE into the chain for the real page.
81 * Must be called with the chain locked; it unlocks the chain.
83 void kvmppc_add_revmap_chain(struct kvm *kvm, struct revmap_entry *rev,
84 unsigned long *rmap, long pte_index, int realmode)
86 struct revmap_entry *head, *tail;
89 if (*rmap & KVMPPC_RMAP_PRESENT) {
90 i = *rmap & KVMPPC_RMAP_INDEX;
91 head = &kvm->arch.hpt.rev[i];
93 head = real_vmalloc_addr(head);
94 tail = &kvm->arch.hpt.rev[head->back];
96 tail = real_vmalloc_addr(tail);
98 rev->back = head->back;
99 tail->forw = pte_index;
100 head->back = pte_index;
102 rev->forw = rev->back = pte_index;
103 *rmap = (*rmap & ~KVMPPC_RMAP_INDEX) |
104 pte_index | KVMPPC_RMAP_PRESENT;
108 EXPORT_SYMBOL_GPL(kvmppc_add_revmap_chain);
110 /* Update the dirty bitmap of a memslot */
111 void kvmppc_update_dirty_map(struct kvm_memory_slot *memslot,
112 unsigned long gfn, unsigned long psize)
114 unsigned long npages;
116 if (!psize || !memslot->dirty_bitmap)
118 npages = (psize + PAGE_SIZE - 1) / PAGE_SIZE;
119 gfn -= memslot->base_gfn;
120 set_dirty_bits_atomic(memslot->dirty_bitmap, gfn, npages);
122 EXPORT_SYMBOL_GPL(kvmppc_update_dirty_map);
124 static void kvmppc_set_dirty_from_hpte(struct kvm *kvm,
125 unsigned long hpte_v, unsigned long hpte_gr)
127 struct kvm_memory_slot *memslot;
131 psize = kvmppc_actual_pgsz(hpte_v, hpte_gr);
132 gfn = hpte_rpn(hpte_gr, psize);
133 memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);
134 if (memslot && memslot->dirty_bitmap)
135 kvmppc_update_dirty_map(memslot, gfn, psize);
138 /* Returns a pointer to the revmap entry for the page mapped by a HPTE */
139 static unsigned long *revmap_for_hpte(struct kvm *kvm, unsigned long hpte_v,
140 unsigned long hpte_gr,
141 struct kvm_memory_slot **memslotp,
144 struct kvm_memory_slot *memslot;
148 gfn = hpte_rpn(hpte_gr, kvmppc_actual_pgsz(hpte_v, hpte_gr));
149 memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);
157 rmap = real_vmalloc_addr(&memslot->arch.rmap[gfn - memslot->base_gfn]);
161 /* Remove this HPTE from the chain for a real page */
162 static void remove_revmap_chain(struct kvm *kvm, long pte_index,
163 struct revmap_entry *rev,
164 unsigned long hpte_v, unsigned long hpte_r)
166 struct revmap_entry *next, *prev;
167 unsigned long ptel, head;
169 unsigned long rcbits;
170 struct kvm_memory_slot *memslot;
173 rcbits = hpte_r & (HPTE_R_R | HPTE_R_C);
174 ptel = rev->guest_rpte |= rcbits;
175 rmap = revmap_for_hpte(kvm, hpte_v, ptel, &memslot, &gfn);
180 head = *rmap & KVMPPC_RMAP_INDEX;
181 next = real_vmalloc_addr(&kvm->arch.hpt.rev[rev->forw]);
182 prev = real_vmalloc_addr(&kvm->arch.hpt.rev[rev->back]);
183 next->back = rev->back;
184 prev->forw = rev->forw;
185 if (head == pte_index) {
187 if (head == pte_index)
188 *rmap &= ~(KVMPPC_RMAP_PRESENT | KVMPPC_RMAP_INDEX);
190 *rmap = (*rmap & ~KVMPPC_RMAP_INDEX) | head;
192 *rmap |= rcbits << KVMPPC_RMAP_RC_SHIFT;
193 if (rcbits & HPTE_R_C)
194 kvmppc_update_dirty_map(memslot, gfn,
195 kvmppc_actual_pgsz(hpte_v, hpte_r));
199 long kvmppc_do_h_enter(struct kvm *kvm, unsigned long flags,
200 long pte_index, unsigned long pteh, unsigned long ptel,
201 pgd_t *pgdir, bool realmode, unsigned long *pte_idx_ret)
203 unsigned long i, pa, gpa, gfn, psize;
204 unsigned long slot_fn, hva;
206 struct revmap_entry *rev;
207 unsigned long g_ptel;
208 struct kvm_memory_slot *memslot;
209 unsigned hpage_shift;
213 unsigned int writing;
214 unsigned long mmu_seq;
215 unsigned long rcbits, irq_flags = 0;
217 if (kvm_is_radix(kvm))
219 psize = kvmppc_actual_pgsz(pteh, ptel);
222 writing = hpte_is_writable(ptel);
223 pteh &= ~(HPTE_V_HVLOCK | HPTE_V_ABSENT | HPTE_V_VALID);
224 ptel &= ~HPTE_GR_RESERVED;
227 /* used later to detect if we might have been invalidated */
228 mmu_seq = kvm->mmu_notifier_seq;
231 /* Find the memslot (if any) for this address */
232 gpa = (ptel & HPTE_R_RPN) & ~(psize - 1);
233 gfn = gpa >> PAGE_SHIFT;
234 memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);
238 if (!(memslot && !(memslot->flags & KVM_MEMSLOT_INVALID))) {
239 /* Emulated MMIO - mark this with key=31 */
240 pteh |= HPTE_V_ABSENT;
241 ptel |= HPTE_R_KEY_HI | HPTE_R_KEY_LO;
245 /* Check if the requested page fits entirely in the memslot. */
246 if (!slot_is_aligned(memslot, psize))
248 slot_fn = gfn - memslot->base_gfn;
249 rmap = &memslot->arch.rmap[slot_fn];
251 /* Translate to host virtual address */
252 hva = __gfn_to_hva_memslot(memslot, gfn);
254 * If we had a page table table change after lookup, we would
255 * retry via mmu_notifier_retry.
258 local_irq_save(irq_flags);
260 * If called in real mode we have MSR_EE = 0. Otherwise
261 * we disable irq above.
263 ptep = __find_linux_pte(pgdir, hva, NULL, &hpage_shift);
266 unsigned int host_pte_size;
269 host_pte_size = 1ul << hpage_shift;
271 host_pte_size = PAGE_SIZE;
273 * We should always find the guest page size
274 * to <= host page size, if host is using hugepage
276 if (host_pte_size < psize) {
278 local_irq_restore(flags);
281 pte = kvmppc_read_update_linux_pte(ptep, writing);
282 if (pte_present(pte) && !pte_protnone(pte)) {
283 if (writing && !__pte_write(pte))
284 /* make the actual HPTE be read-only */
285 ptel = hpte_make_readonly(ptel);
287 pa = pte_pfn(pte) << PAGE_SHIFT;
288 pa |= hva & (host_pte_size - 1);
289 pa |= gpa & ~PAGE_MASK;
293 local_irq_restore(irq_flags);
295 ptel &= HPTE_R_KEY | HPTE_R_PP0 | (psize-1);
299 pteh |= HPTE_V_VALID;
301 pteh |= HPTE_V_ABSENT;
302 ptel &= ~(HPTE_R_KEY_HI | HPTE_R_KEY_LO);
305 /*If we had host pte mapping then Check WIMG */
306 if (ptep && !hpte_cache_flags_ok(ptel, is_ci)) {
310 * Allow guest to map emulated device memory as
311 * uncacheable, but actually make it cacheable.
313 ptel &= ~(HPTE_R_W|HPTE_R_I|HPTE_R_G);
317 /* Find and lock the HPTEG slot to use */
319 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
321 if (likely((flags & H_EXACT) == 0)) {
323 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
324 for (i = 0; i < 8; ++i) {
325 if ((be64_to_cpu(*hpte) & HPTE_V_VALID) == 0 &&
326 try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID |
333 * Since try_lock_hpte doesn't retry (not even stdcx.
334 * failures), it could be that there is a free slot
335 * but we transiently failed to lock it. Try again,
336 * actually locking each slot and checking it.
339 for (i = 0; i < 8; ++i) {
341 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
343 pte = be64_to_cpu(hpte[0]);
344 if (!(pte & (HPTE_V_VALID | HPTE_V_ABSENT)))
346 __unlock_hpte(hpte, pte);
354 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
355 if (!try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID |
357 /* Lock the slot and check again */
360 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
362 pte = be64_to_cpu(hpte[0]);
363 if (pte & (HPTE_V_VALID | HPTE_V_ABSENT)) {
364 __unlock_hpte(hpte, pte);
370 /* Save away the guest's idea of the second HPTE dword */
371 rev = &kvm->arch.hpt.rev[pte_index];
373 rev = real_vmalloc_addr(rev);
375 rev->guest_rpte = g_ptel;
376 note_hpte_modification(kvm, rev);
379 /* Link HPTE into reverse-map chain */
380 if (pteh & HPTE_V_VALID) {
382 rmap = real_vmalloc_addr(rmap);
384 /* Check for pending invalidations under the rmap chain lock */
385 if (mmu_notifier_retry(kvm, mmu_seq)) {
386 /* inval in progress, write a non-present HPTE */
387 pteh |= HPTE_V_ABSENT;
388 pteh &= ~HPTE_V_VALID;
389 ptel &= ~(HPTE_R_KEY_HI | HPTE_R_KEY_LO);
392 kvmppc_add_revmap_chain(kvm, rev, rmap, pte_index,
394 /* Only set R/C in real HPTE if already set in *rmap */
395 rcbits = *rmap >> KVMPPC_RMAP_RC_SHIFT;
396 ptel &= rcbits | ~(HPTE_R_R | HPTE_R_C);
400 /* Convert to new format on P9 */
401 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
402 ptel = hpte_old_to_new_r(pteh, ptel);
403 pteh = hpte_old_to_new_v(pteh);
405 hpte[1] = cpu_to_be64(ptel);
407 /* Write the first HPTE dword, unlocking the HPTE and making it valid */
409 __unlock_hpte(hpte, pteh);
410 asm volatile("ptesync" : : : "memory");
412 *pte_idx_ret = pte_index;
415 EXPORT_SYMBOL_GPL(kvmppc_do_h_enter);
417 long kvmppc_h_enter(struct kvm_vcpu *vcpu, unsigned long flags,
418 long pte_index, unsigned long pteh, unsigned long ptel)
420 return kvmppc_do_h_enter(vcpu->kvm, flags, pte_index, pteh, ptel,
421 vcpu->arch.pgdir, true,
422 &vcpu->arch.regs.gpr[4]);
425 #ifdef __BIG_ENDIAN__
426 #define LOCK_TOKEN (*(u32 *)(&get_paca()->lock_token))
428 #define LOCK_TOKEN (*(u32 *)(&get_paca()->paca_index))
431 static inline int is_mmio_hpte(unsigned long v, unsigned long r)
433 return ((v & HPTE_V_ABSENT) &&
434 (r & (HPTE_R_KEY_HI | HPTE_R_KEY_LO)) ==
435 (HPTE_R_KEY_HI | HPTE_R_KEY_LO));
438 static void do_tlbies(struct kvm *kvm, unsigned long *rbvalues,
439 long npages, int global, bool need_sync)
444 * We use the POWER9 5-operand versions of tlbie and tlbiel here.
445 * Since we are using RIC=0 PRS=0 R=0, and P7/P8 tlbiel ignores
446 * the RS field, this is backwards-compatible with P7 and P8.
450 asm volatile("ptesync" : : : "memory");
451 for (i = 0; i < npages; ++i) {
452 asm volatile(PPC_TLBIE_5(%0,%1,0,0,0) : :
453 "r" (rbvalues[i]), "r" (kvm->arch.lpid));
456 if (cpu_has_feature(CPU_FTR_P9_TLBIE_BUG)) {
458 * Need the extra ptesync to make sure we don't
461 asm volatile("ptesync": : :"memory");
462 asm volatile(PPC_TLBIE_5(%0,%1,0,0,0) : :
463 "r" (rbvalues[0]), "r" (kvm->arch.lpid));
466 asm volatile("eieio; tlbsync; ptesync" : : : "memory");
469 asm volatile("ptesync" : : : "memory");
470 for (i = 0; i < npages; ++i) {
471 asm volatile(PPC_TLBIEL(%0,%1,0,0,0) : :
472 "r" (rbvalues[i]), "r" (0));
474 asm volatile("ptesync" : : : "memory");
478 long kvmppc_do_h_remove(struct kvm *kvm, unsigned long flags,
479 unsigned long pte_index, unsigned long avpn,
480 unsigned long *hpret)
483 unsigned long v, r, rb;
484 struct revmap_entry *rev;
485 u64 pte, orig_pte, pte_r;
487 if (kvm_is_radix(kvm))
489 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
491 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
492 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
494 pte = orig_pte = be64_to_cpu(hpte[0]);
495 pte_r = be64_to_cpu(hpte[1]);
496 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
497 pte = hpte_new_to_old_v(pte, pte_r);
498 pte_r = hpte_new_to_old_r(pte_r);
500 if ((pte & (HPTE_V_ABSENT | HPTE_V_VALID)) == 0 ||
501 ((flags & H_AVPN) && (pte & ~0x7fUL) != avpn) ||
502 ((flags & H_ANDCOND) && (pte & avpn) != 0)) {
503 __unlock_hpte(hpte, orig_pte);
507 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
508 v = pte & ~HPTE_V_HVLOCK;
509 if (v & HPTE_V_VALID) {
510 hpte[0] &= ~cpu_to_be64(HPTE_V_VALID);
511 rb = compute_tlbie_rb(v, pte_r, pte_index);
512 do_tlbies(kvm, &rb, 1, global_invalidates(kvm), true);
514 * The reference (R) and change (C) bits in a HPT
515 * entry can be set by hardware at any time up until
516 * the HPTE is invalidated and the TLB invalidation
517 * sequence has completed. This means that when
518 * removing a HPTE, we need to re-read the HPTE after
519 * the invalidation sequence has completed in order to
520 * obtain reliable values of R and C.
522 remove_revmap_chain(kvm, pte_index, rev, v,
523 be64_to_cpu(hpte[1]));
525 r = rev->guest_rpte & ~HPTE_GR_RESERVED;
526 note_hpte_modification(kvm, rev);
527 unlock_hpte(hpte, 0);
529 if (is_mmio_hpte(v, pte_r))
530 atomic64_inc(&kvm->arch.mmio_update);
532 if (v & HPTE_V_ABSENT)
533 v = (v & ~HPTE_V_ABSENT) | HPTE_V_VALID;
538 EXPORT_SYMBOL_GPL(kvmppc_do_h_remove);
540 long kvmppc_h_remove(struct kvm_vcpu *vcpu, unsigned long flags,
541 unsigned long pte_index, unsigned long avpn)
543 return kvmppc_do_h_remove(vcpu->kvm, flags, pte_index, avpn,
544 &vcpu->arch.regs.gpr[4]);
547 long kvmppc_h_bulk_remove(struct kvm_vcpu *vcpu)
549 struct kvm *kvm = vcpu->kvm;
550 unsigned long *args = &vcpu->arch.regs.gpr[4];
551 __be64 *hp, *hptes[4];
552 unsigned long tlbrb[4];
553 long int i, j, k, n, found, indexes[4];
554 unsigned long flags, req, pte_index, rcbits;
556 long int ret = H_SUCCESS;
557 struct revmap_entry *rev, *revs[4];
560 if (kvm_is_radix(kvm))
562 global = global_invalidates(kvm);
563 for (i = 0; i < 4 && ret == H_SUCCESS; ) {
568 flags = pte_index >> 56;
569 pte_index &= ((1ul << 56) - 1);
572 if (req == 3) { /* no more requests */
576 if (req != 1 || flags == 3 ||
577 pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt)) {
578 /* parameter error */
579 args[j] = ((0xa0 | flags) << 56) + pte_index;
583 hp = (__be64 *) (kvm->arch.hpt.virt + (pte_index << 4));
584 /* to avoid deadlock, don't spin except for first */
585 if (!try_lock_hpte(hp, HPTE_V_HVLOCK)) {
588 while (!try_lock_hpte(hp, HPTE_V_HVLOCK))
592 hp0 = be64_to_cpu(hp[0]);
593 hp1 = be64_to_cpu(hp[1]);
594 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
595 hp0 = hpte_new_to_old_v(hp0, hp1);
596 hp1 = hpte_new_to_old_r(hp1);
598 if (hp0 & (HPTE_V_ABSENT | HPTE_V_VALID)) {
600 case 0: /* absolute */
603 case 1: /* andcond */
604 if (!(hp0 & args[j + 1]))
608 if ((hp0 & ~0x7fUL) == args[j + 1])
614 hp[0] &= ~cpu_to_be64(HPTE_V_HVLOCK);
615 args[j] = ((0x90 | flags) << 56) + pte_index;
619 args[j] = ((0x80 | flags) << 56) + pte_index;
620 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
621 note_hpte_modification(kvm, rev);
623 if (!(hp0 & HPTE_V_VALID)) {
624 /* insert R and C bits from PTE */
625 rcbits = rev->guest_rpte & (HPTE_R_R|HPTE_R_C);
626 args[j] |= rcbits << (56 - 5);
628 if (is_mmio_hpte(hp0, hp1))
629 atomic64_inc(&kvm->arch.mmio_update);
633 /* leave it locked */
634 hp[0] &= ~cpu_to_be64(HPTE_V_VALID);
635 tlbrb[n] = compute_tlbie_rb(hp0, hp1, pte_index);
645 /* Now that we've collected a batch, do the tlbies */
646 do_tlbies(kvm, tlbrb, n, global, true);
648 /* Read PTE low words after tlbie to get final R/C values */
649 for (k = 0; k < n; ++k) {
651 pte_index = args[j] & ((1ul << 56) - 1);
654 remove_revmap_chain(kvm, pte_index, rev,
655 be64_to_cpu(hp[0]), be64_to_cpu(hp[1]));
656 rcbits = rev->guest_rpte & (HPTE_R_R|HPTE_R_C);
657 args[j] |= rcbits << (56 - 5);
658 __unlock_hpte(hp, 0);
665 long kvmppc_h_protect(struct kvm_vcpu *vcpu, unsigned long flags,
666 unsigned long pte_index, unsigned long avpn,
669 struct kvm *kvm = vcpu->kvm;
671 struct revmap_entry *rev;
672 unsigned long v, r, rb, mask, bits;
675 if (kvm_is_radix(kvm))
677 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
680 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
681 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
683 v = pte_v = be64_to_cpu(hpte[0]);
684 if (cpu_has_feature(CPU_FTR_ARCH_300))
685 v = hpte_new_to_old_v(v, be64_to_cpu(hpte[1]));
686 if ((v & (HPTE_V_ABSENT | HPTE_V_VALID)) == 0 ||
687 ((flags & H_AVPN) && (v & ~0x7fUL) != avpn)) {
688 __unlock_hpte(hpte, pte_v);
692 pte_r = be64_to_cpu(hpte[1]);
693 bits = (flags << 55) & HPTE_R_PP0;
694 bits |= (flags << 48) & HPTE_R_KEY_HI;
695 bits |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO);
697 /* Update guest view of 2nd HPTE dword */
698 mask = HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N |
699 HPTE_R_KEY_HI | HPTE_R_KEY_LO;
700 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
702 r = (rev->guest_rpte & ~mask) | bits;
704 note_hpte_modification(kvm, rev);
708 if (v & HPTE_V_VALID) {
710 * If the page is valid, don't let it transition from
711 * readonly to writable. If it should be writable, we'll
712 * take a trap and let the page fault code sort it out.
714 r = (pte_r & ~mask) | bits;
715 if (hpte_is_writable(r) && !hpte_is_writable(pte_r))
716 r = hpte_make_readonly(r);
717 /* If the PTE is changing, invalidate it first */
719 rb = compute_tlbie_rb(v, r, pte_index);
720 hpte[0] = cpu_to_be64((pte_v & ~HPTE_V_VALID) |
722 do_tlbies(kvm, &rb, 1, global_invalidates(kvm), true);
723 /* Don't lose R/C bit updates done by hardware */
724 r |= be64_to_cpu(hpte[1]) & (HPTE_R_R | HPTE_R_C);
725 hpte[1] = cpu_to_be64(r);
728 unlock_hpte(hpte, pte_v & ~HPTE_V_HVLOCK);
729 asm volatile("ptesync" : : : "memory");
730 if (is_mmio_hpte(v, pte_r))
731 atomic64_inc(&kvm->arch.mmio_update);
736 long kvmppc_h_read(struct kvm_vcpu *vcpu, unsigned long flags,
737 unsigned long pte_index)
739 struct kvm *kvm = vcpu->kvm;
743 struct revmap_entry *rev = NULL;
745 if (kvm_is_radix(kvm))
747 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
749 if (flags & H_READ_4) {
753 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
754 for (i = 0; i < n; ++i, ++pte_index) {
755 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
756 v = be64_to_cpu(hpte[0]) & ~HPTE_V_HVLOCK;
757 r = be64_to_cpu(hpte[1]);
758 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
759 v = hpte_new_to_old_v(v, r);
760 r = hpte_new_to_old_r(r);
762 if (v & HPTE_V_ABSENT) {
766 if (v & HPTE_V_VALID) {
767 r = rev[i].guest_rpte | (r & (HPTE_R_R | HPTE_R_C));
768 r &= ~HPTE_GR_RESERVED;
770 vcpu->arch.regs.gpr[4 + i * 2] = v;
771 vcpu->arch.regs.gpr[5 + i * 2] = r;
776 long kvmppc_h_clear_ref(struct kvm_vcpu *vcpu, unsigned long flags,
777 unsigned long pte_index)
779 struct kvm *kvm = vcpu->kvm;
781 unsigned long v, r, gr;
782 struct revmap_entry *rev;
784 long ret = H_NOT_FOUND;
786 if (kvm_is_radix(kvm))
788 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
791 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
792 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
793 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
795 v = be64_to_cpu(hpte[0]);
796 r = be64_to_cpu(hpte[1]);
797 if (!(v & (HPTE_V_VALID | HPTE_V_ABSENT)))
800 gr = rev->guest_rpte;
801 if (rev->guest_rpte & HPTE_R_R) {
802 rev->guest_rpte &= ~HPTE_R_R;
803 note_hpte_modification(kvm, rev);
805 if (v & HPTE_V_VALID) {
806 gr |= r & (HPTE_R_R | HPTE_R_C);
808 kvmppc_clear_ref_hpte(kvm, hpte, pte_index);
809 rmap = revmap_for_hpte(kvm, v, gr, NULL, NULL);
812 *rmap |= KVMPPC_RMAP_REFERENCED;
817 vcpu->arch.regs.gpr[4] = gr;
820 unlock_hpte(hpte, v & ~HPTE_V_HVLOCK);
824 long kvmppc_h_clear_mod(struct kvm_vcpu *vcpu, unsigned long flags,
825 unsigned long pte_index)
827 struct kvm *kvm = vcpu->kvm;
829 unsigned long v, r, gr;
830 struct revmap_entry *rev;
831 long ret = H_NOT_FOUND;
833 if (kvm_is_radix(kvm))
835 if (pte_index >= kvmppc_hpt_npte(&kvm->arch.hpt))
838 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[pte_index]);
839 hpte = (__be64 *)(kvm->arch.hpt.virt + (pte_index << 4));
840 while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
842 v = be64_to_cpu(hpte[0]);
843 r = be64_to_cpu(hpte[1]);
844 if (!(v & (HPTE_V_VALID | HPTE_V_ABSENT)))
847 gr = rev->guest_rpte;
849 rev->guest_rpte &= ~HPTE_R_C;
850 note_hpte_modification(kvm, rev);
852 if (v & HPTE_V_VALID) {
853 /* need to make it temporarily absent so C is stable */
854 hpte[0] |= cpu_to_be64(HPTE_V_ABSENT);
855 kvmppc_invalidate_hpte(kvm, hpte, pte_index);
856 r = be64_to_cpu(hpte[1]);
857 gr |= r & (HPTE_R_R | HPTE_R_C);
859 hpte[1] = cpu_to_be64(r & ~HPTE_R_C);
861 kvmppc_set_dirty_from_hpte(kvm, v, gr);
864 vcpu->arch.regs.gpr[4] = gr;
867 unlock_hpte(hpte, v & ~HPTE_V_HVLOCK);
871 void kvmppc_invalidate_hpte(struct kvm *kvm, __be64 *hptep,
872 unsigned long pte_index)
877 hptep[0] &= ~cpu_to_be64(HPTE_V_VALID);
878 hp0 = be64_to_cpu(hptep[0]);
879 hp1 = be64_to_cpu(hptep[1]);
880 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
881 hp0 = hpte_new_to_old_v(hp0, hp1);
882 hp1 = hpte_new_to_old_r(hp1);
884 rb = compute_tlbie_rb(hp0, hp1, pte_index);
885 do_tlbies(kvm, &rb, 1, 1, true);
887 EXPORT_SYMBOL_GPL(kvmppc_invalidate_hpte);
889 void kvmppc_clear_ref_hpte(struct kvm *kvm, __be64 *hptep,
890 unsigned long pte_index)
896 hp0 = be64_to_cpu(hptep[0]);
897 hp1 = be64_to_cpu(hptep[1]);
898 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
899 hp0 = hpte_new_to_old_v(hp0, hp1);
900 hp1 = hpte_new_to_old_r(hp1);
902 rb = compute_tlbie_rb(hp0, hp1, pte_index);
903 rbyte = (be64_to_cpu(hptep[1]) & ~HPTE_R_R) >> 8;
904 /* modify only the second-last byte, which contains the ref bit */
905 *((char *)hptep + 14) = rbyte;
906 do_tlbies(kvm, &rb, 1, 1, false);
908 EXPORT_SYMBOL_GPL(kvmppc_clear_ref_hpte);
910 static int slb_base_page_shift[4] = {
914 20, /* 1M, unsupported */
917 static struct mmio_hpte_cache_entry *mmio_cache_search(struct kvm_vcpu *vcpu,
918 unsigned long eaddr, unsigned long slb_v, long mmio_update)
920 struct mmio_hpte_cache_entry *entry = NULL;
924 for (i = 0; i < MMIO_HPTE_CACHE_SIZE; i++) {
925 entry = &vcpu->arch.mmio_cache.entry[i];
926 if (entry->mmio_update == mmio_update) {
927 pshift = entry->slb_base_pshift;
928 if ((entry->eaddr >> pshift) == (eaddr >> pshift) &&
929 entry->slb_v == slb_v)
936 static struct mmio_hpte_cache_entry *
937 next_mmio_cache_entry(struct kvm_vcpu *vcpu)
939 unsigned int index = vcpu->arch.mmio_cache.index;
941 vcpu->arch.mmio_cache.index++;
942 if (vcpu->arch.mmio_cache.index == MMIO_HPTE_CACHE_SIZE)
943 vcpu->arch.mmio_cache.index = 0;
945 return &vcpu->arch.mmio_cache.entry[index];
948 /* When called from virtmode, this func should be protected by
949 * preempt_disable(), otherwise, the holding of HPTE_V_HVLOCK
950 * can trigger deadlock issue.
952 long kvmppc_hv_find_lock_hpte(struct kvm *kvm, gva_t eaddr, unsigned long slb_v,
957 unsigned long somask;
958 unsigned long vsid, hash;
961 unsigned long mask, val;
962 unsigned long v, r, orig_v;
964 /* Get page shift, work out hash and AVPN etc. */
965 mask = SLB_VSID_B | HPTE_V_AVPN | HPTE_V_SECONDARY;
968 if (slb_v & SLB_VSID_L) {
969 mask |= HPTE_V_LARGE;
971 pshift = slb_base_page_shift[(slb_v & SLB_VSID_LP) >> 4];
973 if (slb_v & SLB_VSID_B_1T) {
974 somask = (1UL << 40) - 1;
975 vsid = (slb_v & ~SLB_VSID_B) >> SLB_VSID_SHIFT_1T;
978 somask = (1UL << 28) - 1;
979 vsid = (slb_v & ~SLB_VSID_B) >> SLB_VSID_SHIFT;
981 hash = (vsid ^ ((eaddr & somask) >> pshift)) & kvmppc_hpt_mask(&kvm->arch.hpt);
982 avpn = slb_v & ~(somask >> 16); /* also includes B */
983 avpn |= (eaddr & somask) >> 16;
986 avpn &= ~((1UL << (pshift - 16)) - 1);
992 hpte = (__be64 *)(kvm->arch.hpt.virt + (hash << 7));
994 for (i = 0; i < 16; i += 2) {
995 /* Read the PTE racily */
996 v = be64_to_cpu(hpte[i]) & ~HPTE_V_HVLOCK;
997 if (cpu_has_feature(CPU_FTR_ARCH_300))
998 v = hpte_new_to_old_v(v, be64_to_cpu(hpte[i+1]));
1000 /* Check valid/absent, hash, segment size and AVPN */
1001 if (!(v & valid) || (v & mask) != val)
1004 /* Lock the PTE and read it under the lock */
1005 while (!try_lock_hpte(&hpte[i], HPTE_V_HVLOCK))
1007 v = orig_v = be64_to_cpu(hpte[i]) & ~HPTE_V_HVLOCK;
1008 r = be64_to_cpu(hpte[i+1]);
1009 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1010 v = hpte_new_to_old_v(v, r);
1011 r = hpte_new_to_old_r(r);
1015 * Check the HPTE again, including base page size
1017 if ((v & valid) && (v & mask) == val &&
1018 kvmppc_hpte_base_page_shift(v, r) == pshift)
1019 /* Return with the HPTE still locked */
1020 return (hash << 3) + (i >> 1);
1022 __unlock_hpte(&hpte[i], orig_v);
1025 if (val & HPTE_V_SECONDARY)
1027 val |= HPTE_V_SECONDARY;
1028 hash = hash ^ kvmppc_hpt_mask(&kvm->arch.hpt);
1032 EXPORT_SYMBOL(kvmppc_hv_find_lock_hpte);
1035 * Called in real mode to check whether an HPTE not found fault
1036 * is due to accessing a paged-out page or an emulated MMIO page,
1037 * or if a protection fault is due to accessing a page that the
1038 * guest wanted read/write access to but which we made read-only.
1039 * Returns a possibly modified status (DSISR) value if not
1040 * (i.e. pass the interrupt to the guest),
1041 * -1 to pass the fault up to host kernel mode code, -2 to do that
1042 * and also load the instruction word (for MMIO emulation),
1043 * or 0 if we should make the guest retry the access.
1045 long kvmppc_hpte_hv_fault(struct kvm_vcpu *vcpu, unsigned long addr,
1046 unsigned long slb_v, unsigned int status, bool data)
1048 struct kvm *kvm = vcpu->kvm;
1050 unsigned long v, r, gr, orig_v;
1052 unsigned long valid;
1053 struct revmap_entry *rev;
1054 unsigned long pp, key;
1055 struct mmio_hpte_cache_entry *cache_entry = NULL;
1056 long mmio_update = 0;
1058 /* For protection fault, expect to find a valid HPTE */
1059 valid = HPTE_V_VALID;
1060 if (status & DSISR_NOHPTE) {
1061 valid |= HPTE_V_ABSENT;
1062 mmio_update = atomic64_read(&kvm->arch.mmio_update);
1063 cache_entry = mmio_cache_search(vcpu, addr, slb_v, mmio_update);
1066 index = cache_entry->pte_index;
1067 v = cache_entry->hpte_v;
1068 r = cache_entry->hpte_r;
1069 gr = cache_entry->rpte;
1071 index = kvmppc_hv_find_lock_hpte(kvm, addr, slb_v, valid);
1073 if (status & DSISR_NOHPTE)
1074 return status; /* there really was no HPTE */
1075 return 0; /* for prot fault, HPTE disappeared */
1077 hpte = (__be64 *)(kvm->arch.hpt.virt + (index << 4));
1078 v = orig_v = be64_to_cpu(hpte[0]) & ~HPTE_V_HVLOCK;
1079 r = be64_to_cpu(hpte[1]);
1080 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1081 v = hpte_new_to_old_v(v, r);
1082 r = hpte_new_to_old_r(r);
1084 rev = real_vmalloc_addr(&kvm->arch.hpt.rev[index]);
1085 gr = rev->guest_rpte;
1087 unlock_hpte(hpte, orig_v);
1090 /* For not found, if the HPTE is valid by now, retry the instruction */
1091 if ((status & DSISR_NOHPTE) && (v & HPTE_V_VALID))
1094 /* Check access permissions to the page */
1095 pp = gr & (HPTE_R_PP0 | HPTE_R_PP);
1096 key = (vcpu->arch.shregs.msr & MSR_PR) ? SLB_VSID_KP : SLB_VSID_KS;
1097 status &= ~DSISR_NOHPTE; /* DSISR_NOHPTE == SRR1_ISI_NOPT */
1099 if (gr & (HPTE_R_N | HPTE_R_G))
1100 return status | SRR1_ISI_N_OR_G;
1101 if (!hpte_read_permission(pp, slb_v & key))
1102 return status | SRR1_ISI_PROT;
1103 } else if (status & DSISR_ISSTORE) {
1104 /* check write permission */
1105 if (!hpte_write_permission(pp, slb_v & key))
1106 return status | DSISR_PROTFAULT;
1108 if (!hpte_read_permission(pp, slb_v & key))
1109 return status | DSISR_PROTFAULT;
1112 /* Check storage key, if applicable */
1113 if (data && (vcpu->arch.shregs.msr & MSR_DR)) {
1114 unsigned int perm = hpte_get_skey_perm(gr, vcpu->arch.amr);
1115 if (status & DSISR_ISSTORE)
1118 return status | DSISR_KEYFAULT;
1121 /* Save HPTE info for virtual-mode handler */
1122 vcpu->arch.pgfault_addr = addr;
1123 vcpu->arch.pgfault_index = index;
1124 vcpu->arch.pgfault_hpte[0] = v;
1125 vcpu->arch.pgfault_hpte[1] = r;
1126 vcpu->arch.pgfault_cache = cache_entry;
1128 /* Check the storage key to see if it is possibly emulated MMIO */
1129 if ((r & (HPTE_R_KEY_HI | HPTE_R_KEY_LO)) ==
1130 (HPTE_R_KEY_HI | HPTE_R_KEY_LO)) {
1132 unsigned int pshift = 12;
1133 unsigned int pshift_index;
1135 if (slb_v & SLB_VSID_L) {
1136 pshift_index = ((slb_v & SLB_VSID_LP) >> 4);
1137 pshift = slb_base_page_shift[pshift_index];
1139 cache_entry = next_mmio_cache_entry(vcpu);
1140 cache_entry->eaddr = addr;
1141 cache_entry->slb_base_pshift = pshift;
1142 cache_entry->pte_index = index;
1143 cache_entry->hpte_v = v;
1144 cache_entry->hpte_r = r;
1145 cache_entry->rpte = gr;
1146 cache_entry->slb_v = slb_v;
1147 cache_entry->mmio_update = mmio_update;
1149 if (data && (vcpu->arch.shregs.msr & MSR_IR))
1150 return -2; /* MMIO emulation - load instr word */
1153 return -1; /* send fault up to host kernel mode */