1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
6 * Derived from book3s_rmhandlers.S and other files, which are:
8 * Copyright SUSE Linux Products GmbH 2009
10 * Authors: Alexander Graf <agraf@suse.de>
13 #include <asm/ppc_asm.h>
14 #include <asm/kvm_asm.h>
18 #include <asm/ptrace.h>
19 #include <asm/hvcall.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/exception-64s.h>
22 #include <asm/kvm_book3s_asm.h>
23 #include <asm/book3s/64/mmu-hash.h>
24 #include <asm/export.h>
27 #include <asm/xive-regs.h>
28 #include <asm/thread_info.h>
29 #include <asm/asm-compat.h>
30 #include <asm/feature-fixups.h>
31 #include <asm/cpuidle.h>
33 /* Sign-extend HDEC if not on POWER9 */
34 #define EXTEND_HDEC(reg) \
37 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
39 /* Values in HSTATE_NAPPING(r13) */
40 #define NAPPING_CEDE 1
41 #define NAPPING_NOVCPU 2
42 #define NAPPING_UNSPLIT 3
44 /* Stack frame offsets for kvmppc_hv_entry */
46 #define STACK_SLOT_TRAP (SFS-4)
47 #define STACK_SLOT_SHORT_PATH (SFS-8)
48 #define STACK_SLOT_TID (SFS-16)
49 #define STACK_SLOT_PSSCR (SFS-24)
50 #define STACK_SLOT_PID (SFS-32)
51 #define STACK_SLOT_IAMR (SFS-40)
52 #define STACK_SLOT_CIABR (SFS-48)
53 #define STACK_SLOT_DAWR (SFS-56)
54 #define STACK_SLOT_DAWRX (SFS-64)
55 #define STACK_SLOT_HFSCR (SFS-72)
56 #define STACK_SLOT_AMR (SFS-80)
57 #define STACK_SLOT_UAMOR (SFS-88)
58 /* the following is used by the P9 short path */
59 #define STACK_SLOT_NVGPRS (SFS-152) /* 18 gprs */
62 * Call kvmppc_hv_entry in real mode.
63 * Must be called with interrupts hard-disabled.
67 * LR = return address to continue at after eventually re-enabling MMU
69 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
71 std r0, PPC_LR_STKOFF(r1)
74 std r10, HSTATE_HOST_MSR(r13)
75 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
80 mtmsrd r0,1 /* clear RI in MSR */
87 /* On P9, do LPCR setting, if necessary */
88 ld r3, HSTATE_SPLIT_MODE(r13)
91 lwz r4, KVM_SPLIT_DO_SET(r3)
97 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
99 ld r4, HSTATE_KVM_VCPU(r13)
102 /* Back from guest - restore host state and return to caller */
105 /* Restore host DABR and DABRX */
106 ld r5,HSTATE_DABR(r13)
110 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
113 ld r3,PACA_SPRG_VDSO(r13)
114 mtspr SPRN_SPRG_VDSO_WRITE,r3
116 /* Reload the host's PMU registers */
117 bl kvmhv_load_host_pmu
120 * Reload DEC. HDEC interrupts were disabled when
121 * we reloaded the host's LPCR value.
123 ld r3, HSTATE_DECEXP(r13)
128 /* hwthread_req may have got set by cede or no vcpu, so clear it */
130 stb r0, HSTATE_HWTHREAD_REQ(r13)
133 * For external interrupts we need to call the Linux
134 * handler to process the interrupt. We do that by jumping
135 * to absolute address 0x500 for external interrupts.
136 * The [h]rfid at the end of the handler will return to
137 * the book3s_hv_interrupts.S code. For other interrupts
138 * we do the rfid to get back to the book3s_hv_interrupts.S
141 ld r8, 112+PPC_LR_STKOFF(r1)
143 ld r7, HSTATE_HOST_MSR(r13)
145 /* Return the trap number on this thread as the return value */
149 * If we came back from the guest via a relocation-on interrupt,
150 * we will be in virtual mode at this point, which makes it a
151 * little easier to get back to the caller.
154 andi. r0, r0, MSR_IR /* in real mode? */
157 /* RFI into the highmem handler */
161 mtmsrd r6, 1 /* Clear RI in MSR */
166 /* Virtual-mode return */
171 kvmppc_primary_no_guest:
172 /* We handle this much like a ceded vcpu */
173 /* put the HDEC into the DEC, since HDEC interrupts don't wake us */
174 /* HDEC may be larger than DEC for arch >= v3.00, but since the */
175 /* HDEC value came from DEC in the first place, it will fit */
179 * Make sure the primary has finished the MMU switch.
180 * We should never get here on a secondary thread, but
181 * check it for robustness' sake.
183 ld r5, HSTATE_KVM_VCORE(r13)
184 65: lbz r0, VCORE_IN_GUEST(r5)
191 /* set our bit in napping_threads */
192 ld r5, HSTATE_KVM_VCORE(r13)
193 lbz r7, HSTATE_PTID(r13)
196 addi r6, r5, VCORE_NAPPING_THREADS
201 /* order napping_threads update vs testing entry_exit_map */
204 lwz r7, VCORE_ENTRY_EXIT(r5)
206 bge kvm_novcpu_exit /* another thread already exiting */
207 li r3, NAPPING_NOVCPU
208 stb r3, HSTATE_NAPPING(r13)
210 li r3, 0 /* Don't wake on privileged (OS) doorbell */
215 * Entered from kvm_start_guest if kvm_hstate.napping is set
221 ld r1, HSTATE_HOST_R1(r13)
222 ld r5, HSTATE_KVM_VCORE(r13)
224 stb r0, HSTATE_NAPPING(r13)
226 /* check the wake reason */
227 bl kvmppc_check_wake_reason
230 * Restore volatile registers since we could have called
231 * a C routine in kvmppc_check_wake_reason.
234 ld r5, HSTATE_KVM_VCORE(r13)
236 /* see if any other thread is already exiting */
237 lwz r0, VCORE_ENTRY_EXIT(r5)
241 /* clear our bit in napping_threads */
242 lbz r7, HSTATE_PTID(r13)
245 addi r6, r5, VCORE_NAPPING_THREADS
251 /* See if the wake reason means we need to exit */
255 /* See if our timeslice has expired (HDEC is negative) */
258 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
262 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
263 ld r4, HSTATE_KVM_VCPU(r13)
265 beq kvmppc_primary_no_guest
267 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
268 addi r3, r4, VCPU_TB_RMENTRY
269 bl kvmhv_start_timing
274 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
275 ld r4, HSTATE_KVM_VCPU(r13)
278 addi r3, r4, VCPU_TB_RMEXIT
279 bl kvmhv_accumulate_time
282 stw r12, STACK_SLOT_TRAP(r1)
283 bl kvmhv_commence_exit
285 b kvmhv_switch_to_host
288 * We come in here when wakened from Linux offline idle code.
290 * r3 contains the SRR1 wakeup value, SRR1 is trashed.
292 _GLOBAL(idle_kvm_start_guest)
293 ld r4,PACAEMERGSP(r13)
299 subi r1,r4,STACK_FRAME_OVERHEAD
303 * Could avoid this and pass it through in r3. For now,
304 * code expects it to be in SRR1.
309 stb r0,PACA_FTRACE_ENABLED(r13)
311 li r0,KVM_HWTHREAD_IN_KVM
312 stb r0,HSTATE_HWTHREAD_STATE(r13)
314 /* kvm cede / napping does not come through here */
315 lbz r0,HSTATE_NAPPING(r13)
322 stb r0, HSTATE_NAPPING(r13)
327 * We weren't napping due to cede, so this must be a secondary
328 * thread being woken up to run a guest, or being woken up due
329 * to a stray IPI. (Or due to some machine check or hypervisor
330 * maintenance interrupt while the core is in KVM.)
333 /* Check the wake reason in SRR1 to see why we got here */
334 bl kvmppc_check_wake_reason
336 * kvmppc_check_wake_reason could invoke a C routine, but we
337 * have no volatile registers to restore when we return.
343 /* get vcore pointer, NULL if we have nothing to run */
344 ld r5,HSTATE_KVM_VCORE(r13)
346 /* if we have no vcore to run, go back to sleep */
349 kvm_secondary_got_guest:
351 /* Set HSTATE_DSCR(r13) to something sensible */
352 ld r6, PACA_DSCR_DEFAULT(r13)
353 std r6, HSTATE_DSCR(r13)
355 /* On thread 0 of a subcore, set HDEC to max */
356 lbz r4, HSTATE_PTID(r13)
359 LOAD_REG_ADDR(r6, decrementer_max)
362 /* and set per-LPAR registers, if doing dynamic micro-threading */
363 ld r6, HSTATE_SPLIT_MODE(r13)
367 ld r0, KVM_SPLIT_RPR(r6)
369 ld r0, KVM_SPLIT_PMMAR(r6)
371 ld r0, KVM_SPLIT_LDBAR(r6)
375 /* On P9 we use the split_info for coordinating LPCR changes */
376 lwz r4, KVM_SPLIT_DO_SET(r6)
383 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
385 /* Order load of vcpu after load of vcore */
387 ld r4, HSTATE_KVM_VCPU(r13)
390 /* Back from the guest, go back to nap */
391 /* Clear our vcpu and vcore pointers so we don't come back in early */
393 std r0, HSTATE_KVM_VCPU(r13)
395 * Once we clear HSTATE_KVM_VCORE(r13), the code in
396 * kvmppc_run_core() is going to assume that all our vcpu
397 * state is visible in memory. This lwsync makes sure
401 std r0, HSTATE_KVM_VCORE(r13)
404 * All secondaries exiting guest will fall through this path.
405 * Before proceeding, just check for HMI interrupt and
406 * invoke opal hmi handler. By now we are sure that the
407 * primary thread on this core/subcore has already made partition
408 * switch/TB resync and we are good to call opal hmi handler.
410 cmpwi r12, BOOK3S_INTERRUPT_HMI
413 li r3,0 /* NULL argument */
414 bl hmi_exception_realmode
416 * At this point we have finished executing in the guest.
417 * We need to wait for hwthread_req to become zero, since
418 * we may not turn on the MMU while hwthread_req is non-zero.
419 * While waiting we also need to check if we get given a vcpu to run.
422 lbz r3, HSTATE_HWTHREAD_REQ(r13)
426 li r0, KVM_HWTHREAD_IN_KERNEL
427 stb r0, HSTATE_HWTHREAD_STATE(r13)
428 /* need to recheck hwthread_req after a barrier, to avoid race */
430 lbz r3, HSTATE_HWTHREAD_REQ(r13)
435 * Jump to idle_return_gpr_loss, which returns to the
436 * idle_kvm_start_guest caller.
440 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
442 /* set up r3 for return */
445 addi r1, r1, STACK_FRAME_OVERHEAD
454 ld r5, HSTATE_KVM_VCORE(r13)
457 ld r3, HSTATE_SPLIT_MODE(r13)
460 lwz r0, KVM_SPLIT_DO_SET(r3)
463 lwz r0, KVM_SPLIT_DO_RESTORE(r3)
466 lbz r0, KVM_SPLIT_DO_NAP(r3)
472 b kvm_secondary_got_guest
474 54: li r0, KVM_HWTHREAD_IN_KVM
475 stb r0, HSTATE_HWTHREAD_STATE(r13)
479 /* Set LPCR, LPIDR etc. on P9 */
487 bl kvmhv_p9_restore_lpcr
492 * Here the primary thread is trying to return the core to
493 * whole-core mode, so we need to nap.
497 * When secondaries are napping in kvm_unsplit_nap() with
498 * hwthread_req = 1, HMI goes ignored even though subcores are
499 * already exited the guest. Hence HMI keeps waking up secondaries
500 * from nap in a loop and secondaries always go back to nap since
501 * no vcore is assigned to them. This makes impossible for primary
502 * thread to get hold of secondary threads resulting into a soft
503 * lockup in KVM path.
505 * Let us check if HMI is pending and handle it before we go to nap.
507 cmpwi r12, BOOK3S_INTERRUPT_HMI
509 li r3, 0 /* NULL argument */
510 bl hmi_exception_realmode
513 * Ensure that secondary doesn't nap when it has
514 * its vcore pointer set.
516 sync /* matches smp_mb() before setting split_info.do_nap */
517 ld r0, HSTATE_KVM_VCORE(r13)
520 /* clear any pending message */
522 lis r6, (PPC_DBELL_SERVER << (63-36))@h
524 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
525 /* Set kvm_split_mode.napped[tid] = 1 */
526 ld r3, HSTATE_SPLIT_MODE(r13)
528 lbz r4, HSTATE_TID(r13)
529 addi r4, r4, KVM_SPLIT_NAPPED
531 /* Check the do_nap flag again after setting napped[] */
533 lbz r0, KVM_SPLIT_DO_NAP(r3)
536 li r3, NAPPING_UNSPLIT
537 stb r3, HSTATE_NAPPING(r13)
538 li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
540 rlwimi r5, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
547 /******************************************************************************
551 *****************************************************************************/
553 .global kvmppc_hv_entry
558 * R4 = vcpu pointer (or NULL)
563 * all other volatile GPRS = free
564 * Does not preserve non-volatile GPRs or CR fields
567 std r0, PPC_LR_STKOFF(r1)
570 /* Save R1 in the PACA */
571 std r1, HSTATE_HOST_R1(r13)
573 li r6, KVM_GUEST_MODE_HOST_HV
574 stb r6, HSTATE_IN_GUEST(r13)
576 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
577 /* Store initial timestamp */
580 addi r3, r4, VCPU_TB_RMENTRY
581 bl kvmhv_start_timing
585 ld r5, HSTATE_KVM_VCORE(r13)
586 ld r9, VCORE_KVM(r5) /* pointer to struct kvm */
589 * POWER7/POWER8 host -> guest partition switch code.
590 * We don't have to lock against concurrent tlbies,
591 * but we do have to coordinate across hardware threads.
593 /* Set bit in entry map iff exit map is zero. */
595 lbz r6, HSTATE_PTID(r13)
597 addi r8, r5, VCORE_ENTRY_EXIT
599 cmpwi r3, 0x100 /* any threads starting to exit? */
600 bge secondary_too_late /* if so we're too late to the party */
605 /* Primary thread switches to guest partition. */
612 li r0,LPID_RSVD /* switch to reserved LPID */
615 mtspr SPRN_SDR1,r6 /* switch to partition page table */
616 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
620 /* See if we need to flush the TLB. */
621 mr r3, r9 /* kvm pointer */
622 lhz r4, PACAPACAINDEX(r13) /* physical cpu number */
623 li r5, 0 /* nested vcpu pointer */
624 bl kvmppc_check_need_tlb_flush
626 ld r5, HSTATE_KVM_VCORE(r13)
628 /* Add timebase offset onto timebase */
629 22: ld r8,VCORE_TB_OFFSET(r5)
632 std r8, VCORE_TB_OFFSET_APPL(r5)
633 mftb r6 /* current host timebase */
635 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
636 mftb r7 /* check if lower 24 bits overflowed */
641 addis r8,r8,0x100 /* if so, increment upper 40 bits */
644 /* Load guest PCR value to select appropriate compat mode */
645 37: ld r7, VCORE_PCR(r5)
652 /* DPDES and VTB are shared between threads */
653 ld r8, VCORE_DPDES(r5)
657 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
659 /* Mark the subcore state as inside guest */
660 bl kvmppc_subcore_enter_guest
662 ld r5, HSTATE_KVM_VCORE(r13)
663 ld r4, HSTATE_KVM_VCPU(r13)
665 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
667 /* Do we have a guest vcpu to run? */
669 beq kvmppc_primary_no_guest
671 /* Increment yield count if they have a VPA */
675 li r6, LPPACA_YIELDCOUNT
680 stb r6, VCPU_VPA_DIRTY(r4)
683 /* Save purr/spurr */
686 std r5,HSTATE_PURR(r13)
687 std r6,HSTATE_SPURR(r13)
693 /* Save host values of some registers */
698 std r5, STACK_SLOT_TID(r1)
699 std r6, STACK_SLOT_PSSCR(r1)
700 std r7, STACK_SLOT_PID(r1)
702 std r5, STACK_SLOT_HFSCR(r1)
703 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
709 std r5, STACK_SLOT_CIABR(r1)
710 std r6, STACK_SLOT_DAWR(r1)
711 std r7, STACK_SLOT_DAWRX(r1)
712 std r8, STACK_SLOT_IAMR(r1)
713 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
716 std r5, STACK_SLOT_AMR(r1)
718 std r6, STACK_SLOT_UAMOR(r1)
721 /* Set partition DABR */
722 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
723 lwz r5,VCPU_DABRX(r4)
728 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
730 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
732 * Branch around the call if both CPU_FTR_TM and
733 * CPU_FTR_P9_TM_HV_ASSIST are off.
737 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
739 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
743 li r5, 0 /* don't preserve non-vol regs */
744 bl kvmppc_restore_tm_hv
746 ld r4, HSTATE_KVM_VCPU(r13)
750 /* Load guest PMU registers; r4 = vcpu pointer here */
752 bl kvmhv_load_guest_pmu
754 /* Load up FP, VMX and VSX registers */
755 ld r4, HSTATE_KVM_VCPU(r13)
758 ld r14, VCPU_GPR(R14)(r4)
759 ld r15, VCPU_GPR(R15)(r4)
760 ld r16, VCPU_GPR(R16)(r4)
761 ld r17, VCPU_GPR(R17)(r4)
762 ld r18, VCPU_GPR(R18)(r4)
763 ld r19, VCPU_GPR(R19)(r4)
764 ld r20, VCPU_GPR(R20)(r4)
765 ld r21, VCPU_GPR(R21)(r4)
766 ld r22, VCPU_GPR(R22)(r4)
767 ld r23, VCPU_GPR(R23)(r4)
768 ld r24, VCPU_GPR(R24)(r4)
769 ld r25, VCPU_GPR(R25)(r4)
770 ld r26, VCPU_GPR(R26)(r4)
771 ld r27, VCPU_GPR(R27)(r4)
772 ld r28, VCPU_GPR(R28)(r4)
773 ld r29, VCPU_GPR(R29)(r4)
774 ld r30, VCPU_GPR(R30)(r4)
775 ld r31, VCPU_GPR(R31)(r4)
777 /* Switch DSCR to guest value */
782 /* Skip next section on POWER7 */
784 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
785 /* Load up POWER8-specific registers */
787 lwz r6, VCPU_PSPB(r4)
793 * Handle broken DAWR case by not writing it. This means we
794 * can still store the DAWR register for migration.
796 LOAD_REG_ADDR(r5, dawr_force_enable)
801 ld r6, VCPU_DAWRX(r4)
805 ld r7, VCPU_CIABR(r4)
810 ld r8, VCPU_EBBHR(r4)
813 ld r5, VCPU_EBBRR(r4)
814 ld r6, VCPU_BESCR(r4)
815 lwz r7, VCPU_GUEST_PID(r4)
822 /* POWER8-only registers */
823 ld r5, VCPU_TCSCR(r4)
825 ld r7, VCPU_CSIGR(r4)
833 /* POWER9-only registers */
835 ld r6, VCPU_PSSCR(r4)
836 lbz r8, HSTATE_FAKE_SUSPEND(r13)
837 oris r6, r6, PSSCR_EC@h /* This makes stop trap to HV */
838 rldimi r6, r8, PSSCR_FAKE_SUSPEND_LG, 63 - PSSCR_FAKE_SUSPEND_LG
839 ld r7, VCPU_HFSCR(r4)
843 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
846 ld r5, VCPU_SPRG0(r4)
847 ld r6, VCPU_SPRG1(r4)
848 ld r7, VCPU_SPRG2(r4)
849 ld r8, VCPU_SPRG3(r4)
855 /* Load up DAR and DSISR */
857 lwz r6, VCPU_DSISR(r4)
861 /* Restore AMR and UAMOR, set AMOR to all 1s */
869 /* Restore state of CTRL run bit; assume 1 on entry */
877 /* Secondary threads wait for primary to have done partition switch */
878 ld r5, HSTATE_KVM_VCORE(r13)
879 lbz r6, HSTATE_PTID(r13)
882 lbz r0, VCORE_IN_GUEST(r5)
886 20: lwz r3, VCORE_ENTRY_EXIT(r5)
889 lbz r0, VCORE_IN_GUEST(r5)
900 * Set the decrementer to the guest decrementer.
902 ld r8,VCPU_DEC_EXPIRES(r4)
903 /* r8 is a host timebase value here, convert to guest TB */
904 ld r5,HSTATE_KVM_VCORE(r13)
905 ld r6,VCORE_TB_OFFSET_APPL(r5)
911 /* Check if HDEC expires soon */
914 cmpdi r3, 512 /* 1 microsecond */
917 /* For hash guest, clear out and reload the SLB */
919 lbz r0, KVM_RADIX(r6)
927 /* Load up guest SLB entries (N.B. slb_max will be 0 for radix) */
928 lwz r5,VCPU_SLB_MAX(r4)
933 1: ld r8,VCPU_SLB_E(r6)
936 addi r6,r6,VCPU_SLB_SIZE
940 #ifdef CONFIG_KVM_XICS
941 /* We are entering the guest on that thread, push VCPU to XIVE */
942 ld r11, VCPU_XIVE_SAVED_STATE(r4)
944 lwz r8, VCPU_XIVE_CAM_WORD(r4)
945 li r7, TM_QW1_OS + TM_WORD2
947 andi. r0, r0, MSR_DR /* in real mode? */
949 ld r10, HSTATE_XIVE_TIMA_VIRT(r13)
956 2: ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
963 stb r9, VCPU_XIVE_PUSHED(r4)
967 * We clear the irq_pending flag. There is a small chance of a
968 * race vs. the escalation interrupt happening on another
969 * processor setting it again, but the only consequence is to
970 * cause a spurrious wakeup on the next H_CEDE which is not an
974 stb r0, VCPU_IRQ_PENDING(r4)
977 * In single escalation mode, if the escalation interrupt is
980 lbz r0, VCPU_XIVE_ESC_ON(r4)
983 li r9, XIVE_ESB_SET_PQ_01
984 beq 4f /* in real mode? */
985 ld r10, VCPU_XIVE_ESC_VADDR(r4)
988 4: ld r10, VCPU_XIVE_ESC_RADDR(r4)
992 /* We have a possible subtle race here: The escalation interrupt might
993 * have fired and be on its way to the host queue while we mask it,
994 * and if we unmask it early enough (re-cede right away), there is
995 * a theorical possibility that it fires again, thus landing in the
996 * target queue more than once which is a big no-no.
998 * Fortunately, solving this is rather easy. If the above load setting
999 * PQ to 01 returns a previous value where P is set, then we know the
1000 * escalation interrupt is somewhere on its way to the host. In that
1001 * case we simply don't clear the xive_esc_on flag below. It will be
1002 * eventually cleared by the handler for the escalation interrupt.
1004 * Then, when doing a cede, we check that flag again before re-enabling
1005 * the escalation interrupt, and if set, we abort the cede.
1007 andi. r0, r0, XIVE_ESB_VAL_P
1010 /* Now P is 0, we can clear the flag */
1012 stb r0, VCPU_XIVE_ESC_ON(r4)
1015 #endif /* CONFIG_KVM_XICS */
1018 stw r0, STACK_SLOT_SHORT_PATH(r1)
1020 deliver_guest_interrupt: /* r4 = vcpu, r13 = paca */
1021 /* Check if we can deliver an external or decrementer interrupt now */
1022 ld r0, VCPU_PENDING_EXC(r4)
1024 /* On POWER9, also check for emulated doorbell interrupt */
1025 lbz r3, VCPU_DBELL_REQ(r4)
1027 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1031 bl kvmppc_guest_entry_inject_int
1032 ld r4, HSTATE_KVM_VCPU(r13)
1034 ld r6, VCPU_SRR0(r4)
1035 ld r7, VCPU_SRR1(r4)
1041 ld r11, VCPU_MSR(r4)
1042 /* r11 = vcpu->arch.msr & ~MSR_HV */
1043 rldicl r11, r11, 63 - MSR_HV_LG, 1
1044 rotldi r11, r11, 1 + MSR_HV_LG
1045 ori r11, r11, MSR_ME
1055 * R10: value for HSRR0
1056 * R11: value for HSRR1
1061 stb r0,VCPU_CEDED(r4) /* cancel cede */
1062 mtspr SPRN_HSRR0,r10
1063 mtspr SPRN_HSRR1,r11
1065 /* Activate guest mode, so faults get handled by KVM */
1066 li r9, KVM_GUEST_MODE_GUEST_HV
1067 stb r9, HSTATE_IN_GUEST(r13)
1069 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1070 /* Accumulate timing */
1071 addi r3, r4, VCPU_TB_GUEST
1072 bl kvmhv_accumulate_time
1078 ld r5, VCPU_CFAR(r4)
1080 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1083 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1090 ld r1, VCPU_GPR(R1)(r4)
1091 ld r2, VCPU_GPR(R2)(r4)
1092 ld r3, VCPU_GPR(R3)(r4)
1093 ld r5, VCPU_GPR(R5)(r4)
1094 ld r6, VCPU_GPR(R6)(r4)
1095 ld r7, VCPU_GPR(R7)(r4)
1096 ld r8, VCPU_GPR(R8)(r4)
1097 ld r9, VCPU_GPR(R9)(r4)
1098 ld r10, VCPU_GPR(R10)(r4)
1099 ld r11, VCPU_GPR(R11)(r4)
1100 ld r12, VCPU_GPR(R12)(r4)
1101 ld r13, VCPU_GPR(R13)(r4)
1105 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1107 /* Move canary into DSISR to check for later */
1110 mtspr SPRN_HDSISR, r0
1111 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1113 ld r0, VCPU_GPR(R0)(r4)
1114 ld r4, VCPU_GPR(R4)(r4)
1119 * Enter the guest on a P9 or later system where we have exactly
1120 * one vcpu per vcore and we don't need to go to real mode
1121 * (which implies that host and guest are both using radix MMU mode).
1123 * Most SPRs and all the VSRs have been loaded already.
1125 _GLOBAL(__kvmhv_vcpu_entry_p9)
1126 EXPORT_SYMBOL_GPL(__kvmhv_vcpu_entry_p9)
1128 std r0, PPC_LR_STKOFF(r1)
1132 stw r0, STACK_SLOT_SHORT_PATH(r1)
1134 std r3, HSTATE_KVM_VCPU(r13)
1138 std r1, HSTATE_HOST_R1(r13)
1142 std reg, STACK_SLOT_NVGPRS + ((reg - 14) * 8)(r1)
1148 ld reg, __VCPU_GPR(reg)(r3)
1153 std r10, HSTATE_HOST_MSR(r13)
1156 b fast_guest_entry_c
1157 guest_exit_short_path:
1159 li r0, KVM_GUEST_MODE_NONE
1160 stb r0, HSTATE_IN_GUEST(r13)
1164 std reg, __VCPU_GPR(reg)(r9)
1170 ld reg, STACK_SLOT_NVGPRS + ((reg - 14) * 8)(r1)
1177 mr r3, r12 /* trap number */
1180 ld r0, PPC_LR_STKOFF(r1)
1183 /* If we are in real mode, do a rfid to get back to the caller */
1185 andi. r5, r4, MSR_IR
1187 rldicl r5, r4, 64 - MSR_TS_S_LG, 62 /* extract TS field */
1189 ld r10, HSTATE_HOST_MSR(r13)
1190 rldimi r10, r5, MSR_TS_S_LG, 63 - MSR_TS_T_LG
1191 mtspr SPRN_SRR1, r10
1197 stw r12, STACK_SLOT_TRAP(r1)
1200 stw r12, VCPU_TRAP(r4)
1201 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1202 addi r3, r4, VCPU_TB_RMEXIT
1203 bl kvmhv_accumulate_time
1205 11: b kvmhv_switch_to_host
1212 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
1213 12: stw r12, VCPU_TRAP(r4)
1215 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1216 addi r3, r4, VCPU_TB_RMEXIT
1217 bl kvmhv_accumulate_time
1221 /******************************************************************************
1225 *****************************************************************************/
1228 * We come here from the first-level interrupt handlers.
1230 .globl kvmppc_interrupt_hv
1231 kvmppc_interrupt_hv:
1233 * Register contents:
1234 * R12 = (guest CR << 32) | interrupt vector
1236 * guest R12 saved in shadow VCPU SCRATCH0
1237 * guest CTR saved in shadow VCPU SCRATCH1 if RELOCATABLE
1238 * guest R13 saved in SPRN_SCRATCH0
1240 std r9, HSTATE_SCRATCH2(r13)
1241 lbz r9, HSTATE_IN_GUEST(r13)
1242 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1243 beq kvmppc_bad_host_intr
1244 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1245 cmpwi r9, KVM_GUEST_MODE_GUEST
1246 ld r9, HSTATE_SCRATCH2(r13)
1247 beq kvmppc_interrupt_pr
1249 /* We're now back in the host but in guest MMU context */
1250 li r9, KVM_GUEST_MODE_HOST_HV
1251 stb r9, HSTATE_IN_GUEST(r13)
1253 ld r9, HSTATE_KVM_VCPU(r13)
1255 /* Save registers */
1257 std r0, VCPU_GPR(R0)(r9)
1258 std r1, VCPU_GPR(R1)(r9)
1259 std r2, VCPU_GPR(R2)(r9)
1260 std r3, VCPU_GPR(R3)(r9)
1261 std r4, VCPU_GPR(R4)(r9)
1262 std r5, VCPU_GPR(R5)(r9)
1263 std r6, VCPU_GPR(R6)(r9)
1264 std r7, VCPU_GPR(R7)(r9)
1265 std r8, VCPU_GPR(R8)(r9)
1266 ld r0, HSTATE_SCRATCH2(r13)
1267 std r0, VCPU_GPR(R9)(r9)
1268 std r10, VCPU_GPR(R10)(r9)
1269 std r11, VCPU_GPR(R11)(r9)
1270 ld r3, HSTATE_SCRATCH0(r13)
1271 std r3, VCPU_GPR(R12)(r9)
1272 /* CR is in the high half of r12 */
1276 ld r3, HSTATE_CFAR(r13)
1277 std r3, VCPU_CFAR(r9)
1278 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1280 ld r4, HSTATE_PPR(r13)
1281 std r4, VCPU_PPR(r9)
1282 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1284 /* Restore R1/R2 so we can handle faults */
1285 ld r1, HSTATE_HOST_R1(r13)
1288 mfspr r10, SPRN_SRR0
1289 mfspr r11, SPRN_SRR1
1290 std r10, VCPU_SRR0(r9)
1291 std r11, VCPU_SRR1(r9)
1292 /* trap is in the low half of r12, clear CR from the high half */
1294 andi. r0, r12, 2 /* need to read HSRR0/1? */
1296 mfspr r10, SPRN_HSRR0
1297 mfspr r11, SPRN_HSRR1
1299 1: std r10, VCPU_PC(r9)
1300 std r11, VCPU_MSR(r9)
1304 std r3, VCPU_GPR(R13)(r9)
1307 stw r12,VCPU_TRAP(r9)
1310 * Now that we have saved away SRR0/1 and HSRR0/1,
1311 * interrupts are recoverable in principle, so set MSR_RI.
1312 * This becomes important for relocation-on interrupts from
1313 * the guest, which we can get in radix mode on POWER9.
1318 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1319 addi r3, r9, VCPU_TB_RMINTR
1321 bl kvmhv_accumulate_time
1322 ld r5, VCPU_GPR(R5)(r9)
1323 ld r6, VCPU_GPR(R6)(r9)
1324 ld r7, VCPU_GPR(R7)(r9)
1325 ld r8, VCPU_GPR(R8)(r9)
1328 /* Save HEIR (HV emulation assist reg) in emul_inst
1329 if this is an HEI (HV emulation interrupt, e40) */
1330 li r3,KVM_INST_FETCH_FAILED
1331 stw r3,VCPU_LAST_INST(r9)
1332 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1335 11: stw r3,VCPU_HEIR(r9)
1337 /* these are volatile across C function calls */
1338 #ifdef CONFIG_RELOCATABLE
1339 ld r3, HSTATE_SCRATCH1(r13)
1345 std r3, VCPU_CTR(r9)
1346 std r4, VCPU_XER(r9)
1348 /* Save more register state */
1351 std r3, VCPU_DAR(r9)
1352 stw r4, VCPU_DSISR(r9)
1354 /* If this is a page table miss then see if it's theirs or ours */
1355 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1357 std r3, VCPU_FAULT_DAR(r9)
1358 stw r4, VCPU_FAULT_DSISR(r9)
1359 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1362 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1363 /* For softpatch interrupt, go off and do TM instruction emulation */
1364 cmpwi r12, BOOK3S_INTERRUPT_HV_SOFTPATCH
1368 /* See if this is a leftover HDEC interrupt */
1369 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1375 bge fast_guest_return
1377 /* See if this is an hcall we can handle in real mode */
1378 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1379 beq hcall_try_real_mode
1381 /* Hypervisor doorbell - exit only if host IPI flag set */
1382 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
1387 /* always exit if we're running a nested guest */
1388 ld r0, VCPU_NESTED(r9)
1391 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1392 lbz r0, HSTATE_HOST_IPI(r13)
1394 beq maybe_reenter_guest
1397 /* If it's a hypervisor facility unavailable interrupt, save HFSCR */
1398 cmpwi r12, BOOK3S_INTERRUPT_H_FAC_UNAVAIL
1400 mfspr r3, SPRN_HFSCR
1401 std r3, VCPU_HFSCR(r9)
1404 /* External interrupt ? */
1405 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1406 beq kvmppc_guest_external
1407 /* See if it is a machine check */
1408 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1409 beq machine_check_realmode
1410 /* Or a hypervisor maintenance interrupt */
1411 cmpwi r12, BOOK3S_INTERRUPT_HMI
1414 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1416 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1417 addi r3, r9, VCPU_TB_RMEXIT
1419 bl kvmhv_accumulate_time
1421 #ifdef CONFIG_KVM_XICS
1422 /* We are exiting, pull the VP from the XIVE */
1423 lbz r0, VCPU_XIVE_PUSHED(r9)
1426 li r7, TM_SPC_PULL_OS_CTX
1429 andi. r0, r0, MSR_DR /* in real mode? */
1431 ld r10, HSTATE_XIVE_TIMA_VIRT(r13)
1434 /* First load to pull the context, we ignore the value */
1437 /* Second load to recover the context state (Words 0 and 1) */
1440 2: ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
1443 /* First load to pull the context, we ignore the value */
1446 /* Second load to recover the context state (Words 0 and 1) */
1448 3: std r11, VCPU_XIVE_SAVED_STATE(r9)
1449 /* Fixup some of the state for the next load */
1452 stb r10, VCPU_XIVE_PUSHED(r9)
1453 stb r10, (VCPU_XIVE_SAVED_STATE+3)(r9)
1454 stb r0, (VCPU_XIVE_SAVED_STATE+4)(r9)
1457 #endif /* CONFIG_KVM_XICS */
1459 /* If we came in through the P9 short path, go back out to C now */
1460 lwz r0, STACK_SLOT_SHORT_PATH(r1)
1462 bne guest_exit_short_path
1464 /* For hash guest, read the guest SLB and save it away */
1466 lbz r0, KVM_RADIX(r5)
1469 bne 3f /* for radix, save 0 entries */
1470 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1475 andis. r0,r8,SLB_ESID_V@h
1477 add r8,r8,r6 /* put index in */
1479 std r8,VCPU_SLB_E(r7)
1480 std r3,VCPU_SLB_V(r7)
1481 addi r7,r7,VCPU_SLB_SIZE
1485 /* Finally clear out the SLB */
1490 3: stw r5,VCPU_SLB_MAX(r9)
1492 /* load host SLB entries */
1493 BEGIN_MMU_FTR_SECTION
1495 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
1496 ld r8,PACA_SLBSHADOWPTR(r13)
1498 .rept SLB_NUM_BOLTED
1499 li r3, SLBSHADOW_SAVEAREA
1503 andis. r7,r5,SLB_ESID_V@h
1511 stw r12, STACK_SLOT_TRAP(r1)
1514 /* Do this before kvmhv_commence_exit so we know TB is guest TB */
1515 ld r3, HSTATE_KVM_VCORE(r13)
1518 /* On P9, if the guest has large decr enabled, don't sign extend */
1520 ld r4, VCORE_LPCR(r3)
1521 andis. r4, r4, LPCR_LD@h
1523 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1526 /* r5 is a guest timebase value here, convert to host TB */
1527 ld r4,VCORE_TB_OFFSET_APPL(r3)
1529 std r5,VCPU_DEC_EXPIRES(r9)
1531 /* Increment exit count, poke other threads to exit */
1533 bl kvmhv_commence_exit
1535 ld r9, HSTATE_KVM_VCPU(r13)
1537 /* Stop others sending VCPU interrupts to this physical CPU */
1539 stw r0, VCPU_CPU(r9)
1540 stw r0, VCPU_THREAD_CPU(r9)
1542 /* Save guest CTRL register, set runlatch to 1 */
1544 stw r6,VCPU_CTRL(r9)
1551 * Save the guest PURR/SPURR
1556 ld r8,VCPU_SPURR(r9)
1557 std r5,VCPU_PURR(r9)
1558 std r6,VCPU_SPURR(r9)
1563 * Restore host PURR/SPURR and add guest times
1564 * so that the time in the guest gets accounted.
1566 ld r3,HSTATE_PURR(r13)
1567 ld r4,HSTATE_SPURR(r13)
1575 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1576 /* Save POWER8-specific registers */
1580 std r5, VCPU_IAMR(r9)
1581 stw r6, VCPU_PSPB(r9)
1582 std r7, VCPU_FSCR(r9)
1586 std r7, VCPU_TAR(r9)
1587 mfspr r8, SPRN_EBBHR
1588 std r8, VCPU_EBBHR(r9)
1589 mfspr r5, SPRN_EBBRR
1590 mfspr r6, SPRN_BESCR
1593 std r5, VCPU_EBBRR(r9)
1594 std r6, VCPU_BESCR(r9)
1595 stw r7, VCPU_GUEST_PID(r9)
1596 std r8, VCPU_WORT(r9)
1598 mfspr r5, SPRN_TCSCR
1600 mfspr r7, SPRN_CSIGR
1602 std r5, VCPU_TCSCR(r9)
1603 std r6, VCPU_ACOP(r9)
1604 std r7, VCPU_CSIGR(r9)
1605 std r8, VCPU_TACR(r9)
1608 mfspr r6, SPRN_PSSCR
1609 std r5, VCPU_TID(r9)
1610 rldicl r6, r6, 4, 50 /* r6 &= PSSCR_GUEST_VIS */
1612 std r6, VCPU_PSSCR(r9)
1613 /* Restore host HFSCR value */
1614 ld r7, STACK_SLOT_HFSCR(r1)
1615 mtspr SPRN_HFSCR, r7
1616 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
1618 * Restore various registers to 0, where non-zero values
1619 * set by the guest could disrupt the host.
1625 mtspr SPRN_TCSCR, r0
1626 /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
1629 mtspr SPRN_MMCRS, r0
1630 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1632 /* Save and restore AMR, IAMR and UAMOR before turning on the MMU */
1633 ld r8, STACK_SLOT_IAMR(r1)
1636 8: /* Power7 jumps back in here */
1640 std r6,VCPU_UAMOR(r9)
1641 ld r5,STACK_SLOT_AMR(r1)
1642 ld r6,STACK_SLOT_UAMOR(r1)
1644 mtspr SPRN_UAMOR, r6
1646 /* Switch DSCR back to host value */
1648 ld r7, HSTATE_DSCR(r13)
1649 std r8, VCPU_DSCR(r9)
1652 /* Save non-volatile GPRs */
1653 std r14, VCPU_GPR(R14)(r9)
1654 std r15, VCPU_GPR(R15)(r9)
1655 std r16, VCPU_GPR(R16)(r9)
1656 std r17, VCPU_GPR(R17)(r9)
1657 std r18, VCPU_GPR(R18)(r9)
1658 std r19, VCPU_GPR(R19)(r9)
1659 std r20, VCPU_GPR(R20)(r9)
1660 std r21, VCPU_GPR(R21)(r9)
1661 std r22, VCPU_GPR(R22)(r9)
1662 std r23, VCPU_GPR(R23)(r9)
1663 std r24, VCPU_GPR(R24)(r9)
1664 std r25, VCPU_GPR(R25)(r9)
1665 std r26, VCPU_GPR(R26)(r9)
1666 std r27, VCPU_GPR(R27)(r9)
1667 std r28, VCPU_GPR(R28)(r9)
1668 std r29, VCPU_GPR(R29)(r9)
1669 std r30, VCPU_GPR(R30)(r9)
1670 std r31, VCPU_GPR(R31)(r9)
1673 mfspr r3, SPRN_SPRG0
1674 mfspr r4, SPRN_SPRG1
1675 mfspr r5, SPRN_SPRG2
1676 mfspr r6, SPRN_SPRG3
1677 std r3, VCPU_SPRG0(r9)
1678 std r4, VCPU_SPRG1(r9)
1679 std r5, VCPU_SPRG2(r9)
1680 std r6, VCPU_SPRG3(r9)
1686 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1688 * Branch around the call if both CPU_FTR_TM and
1689 * CPU_FTR_P9_TM_HV_ASSIST are off.
1693 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
1695 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
1699 li r5, 0 /* don't preserve non-vol regs */
1700 bl kvmppc_save_tm_hv
1702 ld r9, HSTATE_KVM_VCPU(r13)
1706 /* Increment yield count if they have a VPA */
1707 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1710 li r4, LPPACA_YIELDCOUNT
1715 stb r3, VCPU_VPA_DIRTY(r9)
1717 /* Save PMU registers if requested */
1718 /* r8 and cr0.eq are live here */
1721 beq 21f /* if no VPA, save PMU stuff anyway */
1722 lbz r4, LPPACA_PMCINUSE(r8)
1723 21: bl kvmhv_save_guest_pmu
1724 ld r9, HSTATE_KVM_VCPU(r13)
1726 /* Restore host values of some registers */
1728 ld r5, STACK_SLOT_CIABR(r1)
1729 ld r6, STACK_SLOT_DAWR(r1)
1730 ld r7, STACK_SLOT_DAWRX(r1)
1731 mtspr SPRN_CIABR, r5
1733 * If the DAWR doesn't work, it's ok to write these here as
1734 * this value should always be zero
1737 mtspr SPRN_DAWRX, r7
1738 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1740 ld r5, STACK_SLOT_TID(r1)
1741 ld r6, STACK_SLOT_PSSCR(r1)
1742 ld r7, STACK_SLOT_PID(r1)
1744 mtspr SPRN_PSSCR, r6
1746 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1748 #ifdef CONFIG_PPC_RADIX_MMU
1750 * Are we running hash or radix ?
1753 lbz r0, KVM_RADIX(r5)
1758 * Radix: do eieio; tlbsync; ptesync sequence in case we
1759 * interrupted the guest between a tlbie and a ptesync.
1765 /* Radix: Handle the case where the guest used an illegal PID */
1766 LOAD_REG_ADDR(r4, mmu_base_pid)
1767 lwz r3, VCPU_GUEST_PID(r9)
1773 * Illegal PID, the HW might have prefetched and cached in the TLB
1774 * some translations for the LPID 0 / guest PID combination which
1775 * Linux doesn't know about, so we need to flush that PID out of
1776 * the TLB. First we need to set LPIDR to 0 so tlbiel applies to
1777 * the right context.
1783 /* Then do a congruence class local flush */
1785 lwz r0,KVM_TLB_SETS(r6)
1787 li r7,0x400 /* IS field = 0b01 */
1789 sldi r0,r3,32 /* RS has PID */
1790 1: PPC_TLBIEL(7,0,2,1,1) /* RIC=2, PRS=1, R=1 */
1796 #endif /* CONFIG_PPC_RADIX_MMU */
1799 * POWER7/POWER8 guest -> host partition switch code.
1800 * We don't have to lock against tlbies but we do
1801 * have to coordinate the hardware threads.
1802 * Here STACK_SLOT_TRAP(r1) contains the trap number.
1804 kvmhv_switch_to_host:
1805 /* Secondary threads wait for primary to do partition switch */
1806 ld r5,HSTATE_KVM_VCORE(r13)
1807 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1808 lbz r3,HSTATE_PTID(r13)
1812 13: lbz r3,VCORE_IN_GUEST(r5)
1818 /* Primary thread waits for all the secondaries to exit guest */
1819 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1820 rlwinm r0,r3,32-8,0xff
1826 /* Did we actually switch to the guest at all? */
1827 lbz r6, VCORE_IN_GUEST(r5)
1831 /* Primary thread switches back to host partition */
1832 lwz r7,KVM_HOST_LPID(r4)
1834 ld r6,KVM_HOST_SDR1(r4)
1835 li r8,LPID_RSVD /* switch to reserved LPID */
1838 mtspr SPRN_SDR1,r6 /* switch to host page table */
1839 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1844 /* DPDES and VTB are shared between threads */
1845 mfspr r7, SPRN_DPDES
1847 std r7, VCORE_DPDES(r5)
1848 std r8, VCORE_VTB(r5)
1849 /* clear DPDES so we don't get guest doorbells in the host */
1851 mtspr SPRN_DPDES, r8
1852 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1854 /* Subtract timebase offset from timebase */
1855 ld r8, VCORE_TB_OFFSET_APPL(r5)
1859 std r0, VCORE_TB_OFFSET_APPL(r5)
1860 mftb r6 /* current guest timebase */
1862 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1863 mftb r7 /* check if lower 24 bits overflowed */
1868 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1873 * If this is an HMI, we called kvmppc_realmode_hmi_handler
1874 * above, which may or may not have already called
1875 * kvmppc_subcore_exit_guest. Fortunately, all that
1876 * kvmppc_subcore_exit_guest does is clear a flag, so calling
1877 * it again here is benign even if kvmppc_realmode_hmi_handler
1878 * has already called it.
1880 bl kvmppc_subcore_exit_guest
1882 30: ld r5,HSTATE_KVM_VCORE(r13)
1883 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1886 ld r0, VCORE_PCR(r5)
1892 /* Signal secondary CPUs to continue */
1893 stb r0,VCORE_IN_GUEST(r5)
1894 19: lis r8,0x7fff /* MAX_INT@h */
1899 /* On POWER9 with HPT-on-radix we need to wait for all other threads */
1900 ld r3, HSTATE_SPLIT_MODE(r13)
1903 lwz r8, KVM_SPLIT_DO_RESTORE(r3)
1906 bl kvmhv_p9_restore_lpcr
1910 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1911 ld r8,KVM_HOST_LPCR(r4)
1915 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1916 /* Finish timing, if we have a vcpu */
1917 ld r4, HSTATE_KVM_VCPU(r13)
1921 bl kvmhv_accumulate_time
1924 /* Unset guest mode */
1925 li r0, KVM_GUEST_MODE_NONE
1926 stb r0, HSTATE_IN_GUEST(r13)
1928 lwz r12, STACK_SLOT_TRAP(r1) /* return trap # in r12 */
1929 ld r0, SFS+PPC_LR_STKOFF(r1)
1934 kvmppc_guest_external:
1935 /* External interrupt, first check for host_ipi. If this is
1936 * set, we know the host wants us out so let's do it now
1941 * Restore the active volatile registers after returning from
1944 ld r9, HSTATE_KVM_VCPU(r13)
1945 li r12, BOOK3S_INTERRUPT_EXTERNAL
1948 * kvmppc_read_intr return codes:
1950 * Exit to host (r3 > 0)
1951 * 1 An interrupt is pending that needs to be handled by the host
1952 * Exit guest and return to host by branching to guest_exit_cont
1954 * 2 Passthrough that needs completion in the host
1955 * Exit guest and return to host by branching to guest_exit_cont
1956 * However, we also set r12 to BOOK3S_INTERRUPT_HV_RM_HARD
1957 * to indicate to the host to complete handling the interrupt
1959 * Before returning to guest, we check if any CPU is heading out
1960 * to the host and if so, we head out also. If no CPUs are heading
1961 * check return values <= 0.
1963 * Return to guest (r3 <= 0)
1964 * 0 No external interrupt is pending
1965 * -1 A guest wakeup IPI (which has now been cleared)
1966 * In either case, we return to guest to deliver any pending
1969 * -2 A PCI passthrough external interrupt was handled
1970 * (interrupt was delivered directly to guest)
1971 * Return to guest to deliver any pending guest interrupts.
1977 /* Return code = 2 */
1978 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
1979 stw r12, VCPU_TRAP(r9)
1982 1: /* Return code <= 1 */
1986 /* Return code <= 0 */
1987 maybe_reenter_guest:
1988 ld r5, HSTATE_KVM_VCORE(r13)
1989 lwz r0, VCORE_ENTRY_EXIT(r5)
1992 blt deliver_guest_interrupt
1995 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1997 * Softpatch interrupt for transactional memory emulation cases
1998 * on POWER9 DD2.2. This is early in the guest exit path - we
1999 * haven't saved registers or done a treclaim yet.
2002 /* Save instruction image in HEIR */
2004 stw r3, VCPU_HEIR(r9)
2007 * The cases we want to handle here are those where the guest
2008 * is in real suspend mode and is trying to transition to
2009 * transactional mode.
2011 lbz r0, HSTATE_FAKE_SUSPEND(r13)
2012 cmpwi r0, 0 /* keep exiting guest if in fake suspend */
2014 rldicl r3, r11, 64 - MSR_TS_S_LG, 62
2015 cmpwi r3, 1 /* or if not in suspend state */
2018 /* Call C code to do the emulation */
2020 bl kvmhv_p9_tm_emulation_early
2022 ld r9, HSTATE_KVM_VCPU(r13)
2023 li r12, BOOK3S_INTERRUPT_HV_SOFTPATCH
2025 beq guest_exit_cont /* continue exiting if not handled */
2027 ld r11, VCPU_MSR(r9)
2028 b fast_interrupt_c_return /* go back to guest if handled */
2029 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2032 * Check whether an HDSI is an HPTE not found fault or something else.
2033 * If it is an HPTE not found fault that is due to the guest accessing
2034 * a page that they have mapped but which we have paged out, then
2035 * we continue on with the guest exit path. In all other cases,
2036 * reflect the HDSI to the guest as a DSI.
2040 lbz r0, KVM_RADIX(r3)
2042 mfspr r6, SPRN_HDSISR
2044 /* Look for DSISR canary. If we find it, retry instruction */
2047 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2049 bne .Lradix_hdsi /* on radix, just save DAR/DSISR/ASDR */
2050 /* HPTE not found fault or protection fault? */
2051 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
2052 beq 1f /* if not, send it to the guest */
2053 andi. r0, r11, MSR_DR /* data relocation enabled? */
2056 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
2058 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2060 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
2061 li r0, BOOK3S_INTERRUPT_DATA_SEGMENT
2062 bne 7f /* if no SLB entry found */
2063 4: std r4, VCPU_FAULT_DAR(r9)
2064 stw r6, VCPU_FAULT_DSISR(r9)
2066 /* Search the hash table. */
2067 mr r3, r9 /* vcpu pointer */
2068 li r7, 1 /* data fault */
2069 bl kvmppc_hpte_hv_fault
2070 ld r9, HSTATE_KVM_VCPU(r13)
2072 ld r11, VCPU_MSR(r9)
2073 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
2074 cmpdi r3, 0 /* retry the instruction */
2076 cmpdi r3, -1 /* handle in kernel mode */
2078 cmpdi r3, -2 /* MMIO emulation; need instr word */
2081 /* Synthesize a DSI (or DSegI) for the guest */
2082 ld r4, VCPU_FAULT_DAR(r9)
2084 1: li r0, BOOK3S_INTERRUPT_DATA_STORAGE
2085 mtspr SPRN_DSISR, r6
2086 7: mtspr SPRN_DAR, r4
2087 mtspr SPRN_SRR0, r10
2088 mtspr SPRN_SRR1, r11
2090 bl kvmppc_msr_interrupt
2091 fast_interrupt_c_return:
2092 6: ld r7, VCPU_CTR(r9)
2099 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
2100 ld r5, KVM_VRMA_SLB_V(r5)
2103 /* If this is for emulated MMIO, load the instruction word */
2104 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
2106 /* Set guest mode to 'jump over instruction' so if lwz faults
2107 * we'll just continue at the next IP. */
2108 li r0, KVM_GUEST_MODE_SKIP
2109 stb r0, HSTATE_IN_GUEST(r13)
2111 /* Do the access with MSR:DR enabled */
2113 ori r4, r3, MSR_DR /* Enable paging for data */
2118 /* Store the result */
2119 stw r8, VCPU_LAST_INST(r9)
2121 /* Unset guest mode. */
2122 li r0, KVM_GUEST_MODE_HOST_HV
2123 stb r0, HSTATE_IN_GUEST(r13)
2127 std r4, VCPU_FAULT_DAR(r9)
2128 stw r6, VCPU_FAULT_DSISR(r9)
2131 std r5, VCPU_FAULT_GPA(r9)
2135 * Similarly for an HISI, reflect it to the guest as an ISI unless
2136 * it is an HPTE not found fault for a page that we have paged out.
2140 lbz r0, KVM_RADIX(r3)
2142 bne .Lradix_hisi /* for radix, just save ASDR */
2143 andis. r0, r11, SRR1_ISI_NOPT@h
2145 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
2148 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
2150 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2152 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
2153 li r0, BOOK3S_INTERRUPT_INST_SEGMENT
2154 bne 7f /* if no SLB entry found */
2156 /* Search the hash table. */
2157 mr r3, r9 /* vcpu pointer */
2160 li r7, 0 /* instruction fault */
2161 bl kvmppc_hpte_hv_fault
2162 ld r9, HSTATE_KVM_VCPU(r13)
2164 ld r11, VCPU_MSR(r9)
2165 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
2166 cmpdi r3, 0 /* retry the instruction */
2167 beq fast_interrupt_c_return
2168 cmpdi r3, -1 /* handle in kernel mode */
2171 /* Synthesize an ISI (or ISegI) for the guest */
2173 1: li r0, BOOK3S_INTERRUPT_INST_STORAGE
2174 7: mtspr SPRN_SRR0, r10
2175 mtspr SPRN_SRR1, r11
2177 bl kvmppc_msr_interrupt
2178 b fast_interrupt_c_return
2180 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
2181 ld r5, KVM_VRMA_SLB_V(r6)
2185 * Try to handle an hcall in real mode.
2186 * Returns to the guest if we handle it, or continues on up to
2187 * the kernel if we can't (i.e. if we don't have a handler for
2188 * it, or if the handler returns H_TOO_HARD).
2190 * r5 - r8 contain hcall args,
2191 * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca
2193 hcall_try_real_mode:
2194 ld r3,VCPU_GPR(R3)(r9)
2196 /* sc 1 from userspace - reflect to guest syscall */
2197 bne sc_1_fast_return
2198 /* sc 1 from nested guest - give it to L1 to handle */
2199 ld r0, VCPU_NESTED(r9)
2203 cmpldi r3,hcall_real_table_end - hcall_real_table
2205 /* See if this hcall is enabled for in-kernel handling */
2207 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
2208 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
2210 ld r0, KVM_ENABLED_HCALLS(r4)
2211 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
2215 /* Get pointer to handler, if any, and call it */
2216 LOAD_REG_ADDR(r4, hcall_real_table)
2222 mr r3,r9 /* get vcpu pointer */
2223 ld r4,VCPU_GPR(R4)(r9)
2226 beq hcall_real_fallback
2227 ld r4,HSTATE_KVM_VCPU(r13)
2228 std r3,VCPU_GPR(R3)(r4)
2236 li r10, BOOK3S_INTERRUPT_SYSCALL
2237 bl kvmppc_msr_interrupt
2241 /* We've attempted a real mode hcall, but it's punted it back
2242 * to userspace. We need to restore some clobbered volatiles
2243 * before resuming the pass-it-to-qemu path */
2244 hcall_real_fallback:
2245 li r12,BOOK3S_INTERRUPT_SYSCALL
2246 ld r9, HSTATE_KVM_VCPU(r13)
2250 .globl hcall_real_table
2252 .long 0 /* 0 - unused */
2253 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
2254 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
2255 .long DOTSYM(kvmppc_h_read) - hcall_real_table
2256 .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table
2257 .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table
2258 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
2259 #ifdef CONFIG_SPAPR_TCE_IOMMU
2260 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
2261 .long DOTSYM(kvmppc_rm_h_put_tce) - hcall_real_table
2266 .long 0 /* 0x24 - H_SET_SPRG0 */
2267 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
2268 .long DOTSYM(kvmppc_rm_h_page_init) - hcall_real_table
2282 #ifdef CONFIG_KVM_XICS
2283 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
2284 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
2285 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
2286 .long DOTSYM(kvmppc_rm_h_ipoll) - hcall_real_table
2287 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
2289 .long 0 /* 0x64 - H_EOI */
2290 .long 0 /* 0x68 - H_CPPR */
2291 .long 0 /* 0x6c - H_IPI */
2292 .long 0 /* 0x70 - H_IPOLL */
2293 .long 0 /* 0x74 - H_XIRR */
2321 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
2322 .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table
2338 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
2342 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
2343 #ifdef CONFIG_SPAPR_TCE_IOMMU
2344 .long DOTSYM(kvmppc_rm_h_stuff_tce) - hcall_real_table
2345 .long DOTSYM(kvmppc_rm_h_put_tce_indirect) - hcall_real_table
2461 #ifdef CONFIG_KVM_XICS
2462 .long DOTSYM(kvmppc_rm_h_xirr_x) - hcall_real_table
2464 .long 0 /* 0x2fc - H_XIRR_X*/
2466 .long DOTSYM(kvmppc_h_random) - hcall_real_table
2467 .globl hcall_real_table_end
2468 hcall_real_table_end:
2470 _GLOBAL(kvmppc_h_set_xdabr)
2471 EXPORT_SYMBOL_GPL(kvmppc_h_set_xdabr)
2472 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2474 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2477 6: li r3, H_PARAMETER
2480 _GLOBAL(kvmppc_h_set_dabr)
2481 EXPORT_SYMBOL_GPL(kvmppc_h_set_dabr)
2482 li r5, DABRX_USER | DABRX_KERNEL
2486 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2487 std r4,VCPU_DABR(r3)
2488 stw r5, VCPU_DABRX(r3)
2489 mtspr SPRN_DABRX, r5
2490 /* Work around P7 bug where DABR can get corrupted on mtspr */
2491 1: mtspr SPRN_DABR,r4
2500 LOAD_REG_ADDR(r11, dawr_force_enable)
2507 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2508 rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2509 rlwimi r5, r4, 2, DAWRX_WT
2511 std r4, VCPU_DAWR(r3)
2512 std r5, VCPU_DAWRX(r3)
2514 * If came in through the real mode hcall handler then it is necessary
2515 * to write the registers since the return path won't. Otherwise it is
2516 * sufficient to store then in the vcpu struct as they will be loaded
2517 * next time the vcpu is run.
2520 andi. r6, r6, MSR_DR /* in real mode? */
2523 mtspr SPRN_DAWRX, r5
2527 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
2529 std r11,VCPU_MSR(r3)
2531 stb r0,VCPU_CEDED(r3)
2532 sync /* order setting ceded vs. testing prodded */
2533 lbz r5,VCPU_PRODDED(r3)
2535 bne kvm_cede_prodded
2536 li r12,0 /* set trap to 0 to say hcall is handled */
2537 stw r12,VCPU_TRAP(r3)
2539 std r0,VCPU_GPR(R3)(r3)
2542 * Set our bit in the bitmask of napping threads unless all the
2543 * other threads are already napping, in which case we send this
2546 ld r5,HSTATE_KVM_VCORE(r13)
2547 lbz r6,HSTATE_PTID(r13)
2548 lwz r8,VCORE_ENTRY_EXIT(r5)
2552 addi r6,r5,VCORE_NAPPING_THREADS
2559 /* order napping_threads update vs testing entry_exit_map */
2562 stb r0,HSTATE_NAPPING(r13)
2563 lwz r7,VCORE_ENTRY_EXIT(r5)
2565 bge 33f /* another thread already exiting */
2568 * Although not specifically required by the architecture, POWER7
2569 * preserves the following registers in nap mode, even if an SMT mode
2570 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2571 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2573 /* Save non-volatile GPRs */
2574 std r14, VCPU_GPR(R14)(r3)
2575 std r15, VCPU_GPR(R15)(r3)
2576 std r16, VCPU_GPR(R16)(r3)
2577 std r17, VCPU_GPR(R17)(r3)
2578 std r18, VCPU_GPR(R18)(r3)
2579 std r19, VCPU_GPR(R19)(r3)
2580 std r20, VCPU_GPR(R20)(r3)
2581 std r21, VCPU_GPR(R21)(r3)
2582 std r22, VCPU_GPR(R22)(r3)
2583 std r23, VCPU_GPR(R23)(r3)
2584 std r24, VCPU_GPR(R24)(r3)
2585 std r25, VCPU_GPR(R25)(r3)
2586 std r26, VCPU_GPR(R26)(r3)
2587 std r27, VCPU_GPR(R27)(r3)
2588 std r28, VCPU_GPR(R28)(r3)
2589 std r29, VCPU_GPR(R29)(r3)
2590 std r30, VCPU_GPR(R30)(r3)
2591 std r31, VCPU_GPR(R31)(r3)
2596 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2598 * Branch around the call if both CPU_FTR_TM and
2599 * CPU_FTR_P9_TM_HV_ASSIST are off.
2603 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
2605 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
2607 ld r3, HSTATE_KVM_VCPU(r13)
2609 li r5, 0 /* don't preserve non-vol regs */
2610 bl kvmppc_save_tm_hv
2616 * Set DEC to the smaller of DEC and HDEC, so that we wake
2617 * no later than the end of our timeslice (HDEC interrupts
2618 * don't wake us from nap).
2624 /* On P9 check whether the guest has large decrementer mode enabled */
2625 ld r6, HSTATE_KVM_VCORE(r13)
2626 ld r6, VCORE_LPCR(r6)
2627 andis. r6, r6, LPCR_LD@h
2629 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2636 /* save expiry time of guest decrementer */
2638 ld r4, HSTATE_KVM_VCPU(r13)
2639 ld r5, HSTATE_KVM_VCORE(r13)
2640 ld r6, VCORE_TB_OFFSET_APPL(r5)
2641 subf r3, r6, r3 /* convert to host TB value */
2642 std r3, VCPU_DEC_EXPIRES(r4)
2644 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2645 ld r4, HSTATE_KVM_VCPU(r13)
2646 addi r3, r4, VCPU_TB_CEDE
2647 bl kvmhv_accumulate_time
2650 lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
2652 /* Go back to host stack */
2653 ld r1, HSTATE_HOST_R1(r13)
2656 * Take a nap until a decrementer or external or doobell interrupt
2657 * occurs, with PECE1 and PECE0 set in LPCR.
2658 * On POWER8, set PECEDH, and if we are ceding, also set PECEDP.
2659 * Also clear the runlatch bit before napping.
2662 mfspr r0, SPRN_CTRLF
2664 mtspr SPRN_CTRLT, r0
2667 stb r0,HSTATE_HWTHREAD_REQ(r13)
2669 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2671 ori r5, r5, LPCR_PECEDH
2672 rlwimi r5, r3, 0, LPCR_PECEDP
2673 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2675 kvm_nap_sequence: /* desired LPCR value in r5 */
2678 * PSSCR bits: exit criterion = 1 (wakeup based on LPCR at sreset)
2679 * enable state loss = 1 (allow SMT mode switch)
2680 * requested level = 0 (just stop dispatching)
2682 lis r3, (PSSCR_EC | PSSCR_ESL)@h
2683 /* Set LPCR_PECE_HVEE bit to enable wakeup by HV interrupts */
2684 li r4, LPCR_PECE_HVEE@higher
2688 li r3, PNV_THREAD_NAP
2689 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
2694 bl isa300_idle_stop_mayloss
2696 bl isa206_idle_insn_mayloss
2697 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
2699 mfspr r0, SPRN_CTRLF
2701 mtspr SPRN_CTRLT, r0
2706 stb r0, PACA_FTRACE_ENABLED(r13)
2708 li r0, KVM_HWTHREAD_IN_KVM
2709 stb r0, HSTATE_HWTHREAD_STATE(r13)
2711 lbz r0, HSTATE_NAPPING(r13)
2712 cmpwi r0, NAPPING_CEDE
2714 cmpwi r0, NAPPING_NOVCPU
2715 beq kvm_novcpu_wakeup
2716 cmpwi r0, NAPPING_UNSPLIT
2717 beq kvm_unsplit_wakeup
2718 twi 31,0,0 /* Nap state must not be zero */
2726 /* Woken by external or decrementer interrupt */
2728 /* get vcpu pointer */
2729 ld r4, HSTATE_KVM_VCPU(r13)
2731 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2732 addi r3, r4, VCPU_TB_RMINTR
2733 bl kvmhv_accumulate_time
2736 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2738 * Branch around the call if both CPU_FTR_TM and
2739 * CPU_FTR_P9_TM_HV_ASSIST are off.
2743 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
2745 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
2749 li r5, 0 /* don't preserve non-vol regs */
2750 bl kvmppc_restore_tm_hv
2752 ld r4, HSTATE_KVM_VCPU(r13)
2756 /* load up FP state */
2759 /* Restore guest decrementer */
2760 ld r3, VCPU_DEC_EXPIRES(r4)
2761 ld r5, HSTATE_KVM_VCORE(r13)
2762 ld r6, VCORE_TB_OFFSET_APPL(r5)
2763 add r3, r3, r6 /* convert host TB to guest TB value */
2769 ld r14, VCPU_GPR(R14)(r4)
2770 ld r15, VCPU_GPR(R15)(r4)
2771 ld r16, VCPU_GPR(R16)(r4)
2772 ld r17, VCPU_GPR(R17)(r4)
2773 ld r18, VCPU_GPR(R18)(r4)
2774 ld r19, VCPU_GPR(R19)(r4)
2775 ld r20, VCPU_GPR(R20)(r4)
2776 ld r21, VCPU_GPR(R21)(r4)
2777 ld r22, VCPU_GPR(R22)(r4)
2778 ld r23, VCPU_GPR(R23)(r4)
2779 ld r24, VCPU_GPR(R24)(r4)
2780 ld r25, VCPU_GPR(R25)(r4)
2781 ld r26, VCPU_GPR(R26)(r4)
2782 ld r27, VCPU_GPR(R27)(r4)
2783 ld r28, VCPU_GPR(R28)(r4)
2784 ld r29, VCPU_GPR(R29)(r4)
2785 ld r30, VCPU_GPR(R30)(r4)
2786 ld r31, VCPU_GPR(R31)(r4)
2788 /* Check the wake reason in SRR1 to see why we got here */
2789 bl kvmppc_check_wake_reason
2792 * Restore volatile registers since we could have called a
2793 * C routine in kvmppc_check_wake_reason
2795 * r3 tells us whether we need to return to host or not
2796 * WARNING: it gets checked further down:
2797 * should not modify r3 until this check is done.
2799 ld r4, HSTATE_KVM_VCPU(r13)
2801 /* clear our bit in vcore->napping_threads */
2802 34: ld r5,HSTATE_KVM_VCORE(r13)
2803 lbz r7,HSTATE_PTID(r13)
2806 addi r6,r5,VCORE_NAPPING_THREADS
2812 stb r0,HSTATE_NAPPING(r13)
2814 /* See if the wake reason saved in r3 means we need to exit */
2815 stw r12, VCPU_TRAP(r4)
2819 b maybe_reenter_guest
2821 /* cede when already previously prodded case */
2824 stb r0,VCPU_PRODDED(r3)
2825 sync /* order testing prodded vs. clearing ceded */
2826 stb r0,VCPU_CEDED(r3)
2830 /* we've ceded but we want to give control to the host */
2832 ld r9, HSTATE_KVM_VCPU(r13)
2833 #ifdef CONFIG_KVM_XICS
2834 /* are we using XIVE with single escalation? */
2835 ld r10, VCPU_XIVE_ESC_VADDR(r9)
2838 li r6, XIVE_ESB_SET_PQ_00
2840 * If we still have a pending escalation, abort the cede,
2841 * and we must set PQ to 10 rather than 00 so that we don't
2842 * potentially end up with two entries for the escalation
2843 * interrupt in the XIVE interrupt queue. In that case
2844 * we also don't want to set xive_esc_on to 1 here in
2845 * case we race with xive_esc_irq().
2847 lbz r5, VCPU_XIVE_ESC_ON(r9)
2851 stb r0, VCPU_CEDED(r9)
2852 li r6, XIVE_ESB_SET_PQ_10
2855 stb r0, VCPU_XIVE_ESC_ON(r9)
2856 /* make sure store to xive_esc_on is seen before xive_esc_irq runs */
2858 5: /* Enable XIVE escalation */
2860 andi. r0, r0, MSR_DR /* in real mode? */
2864 1: ld r10, VCPU_XIVE_ESC_RADDR(r9)
2867 #endif /* CONFIG_KVM_XICS */
2868 3: b guest_exit_cont
2870 /* Try to do machine check recovery in real mode */
2871 machine_check_realmode:
2872 mr r3, r9 /* get vcpu pointer */
2873 bl kvmppc_realmode_machine_check
2875 /* all machine checks go to virtual mode for further handling */
2876 ld r9, HSTATE_KVM_VCPU(r13)
2877 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2881 * Call C code to handle a HMI in real mode.
2882 * Only the primary thread does the call, secondary threads are handled
2883 * by calling hmi_exception_realmode() after kvmppc_hv_entry returns.
2884 * r9 points to the vcpu on entry
2887 lbz r0, HSTATE_PTID(r13)
2890 bl kvmppc_realmode_hmi_handler
2891 ld r9, HSTATE_KVM_VCPU(r13)
2892 li r12, BOOK3S_INTERRUPT_HMI
2896 * Check the reason we woke from nap, and take appropriate action.
2898 * 0 if nothing needs to be done
2899 * 1 if something happened that needs to be handled by the host
2900 * -1 if there was a guest wakeup (IPI or msgsnd)
2901 * -2 if we handled a PCI passthrough interrupt (returned by
2902 * kvmppc_read_intr only)
2904 * Also sets r12 to the interrupt vector for any interrupt that needs
2905 * to be handled now by the host (0x500 for external interrupt), or zero.
2906 * Modifies all volatile registers (since it may call a C function).
2907 * This routine calls kvmppc_read_intr, a C function, if an external
2908 * interrupt is pending.
2910 kvmppc_check_wake_reason:
2913 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2915 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2916 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2917 cmpwi r6, 8 /* was it an external interrupt? */
2918 beq 7f /* if so, see what it was */
2921 cmpwi r6, 6 /* was it the decrementer? */
2924 cmpwi r6, 5 /* privileged doorbell? */
2926 cmpwi r6, 3 /* hypervisor doorbell? */
2928 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2929 cmpwi r6, 0xa /* Hypervisor maintenance ? */
2931 li r3, 1 /* anything else, return 1 */
2934 /* hypervisor doorbell */
2935 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2938 * Clear the doorbell as we will invoke the handler
2939 * explicitly in the guest exit path.
2941 lis r6, (PPC_DBELL_SERVER << (63-36))@h
2943 /* see if it's a host IPI */
2948 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2949 lbz r0, HSTATE_HOST_IPI(r13)
2952 /* if not, return -1 */
2956 /* Woken up due to Hypervisor maintenance interrupt */
2957 4: li r12, BOOK3S_INTERRUPT_HMI
2961 /* external interrupt - create a stack frame so we can call C */
2963 std r0, PPC_LR_STKOFF(r1)
2964 stdu r1, -PPC_MIN_STKFRM(r1)
2967 li r12, BOOK3S_INTERRUPT_EXTERNAL
2972 * Return code of 2 means PCI passthrough interrupt, but
2973 * we need to return back to host to complete handling the
2974 * interrupt. Trap reason is expected in r12 by guest
2977 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
2979 ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1)
2980 addi r1, r1, PPC_MIN_STKFRM
2985 * Save away FP, VMX and VSX registers.
2987 * N.B. r30 and r31 are volatile across this function,
2988 * thus it is not callable from C.
2995 #ifdef CONFIG_ALTIVEC
2997 oris r8,r8,MSR_VEC@h
2998 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3002 oris r8,r8,MSR_VSX@h
3003 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
3006 addi r3,r3,VCPU_FPRS
3008 #ifdef CONFIG_ALTIVEC
3010 addi r3,r31,VCPU_VRS
3012 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3014 mfspr r6,SPRN_VRSAVE
3015 stw r6,VCPU_VRSAVE(r31)
3020 * Load up FP, VMX and VSX registers
3022 * N.B. r30 and r31 are volatile across this function,
3023 * thus it is not callable from C.
3030 #ifdef CONFIG_ALTIVEC
3032 oris r8,r8,MSR_VEC@h
3033 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3037 oris r8,r8,MSR_VSX@h
3038 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
3041 addi r3,r4,VCPU_FPRS
3043 #ifdef CONFIG_ALTIVEC
3045 addi r3,r31,VCPU_VRS
3047 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3049 lwz r7,VCPU_VRSAVE(r31)
3050 mtspr SPRN_VRSAVE,r7
3055 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
3057 * Save transactional state and TM-related registers.
3058 * Called with r3 pointing to the vcpu struct and r4 containing
3059 * the guest MSR value.
3060 * r5 is non-zero iff non-volatile register state needs to be maintained.
3061 * If r5 == 0, this can modify all checkpointed registers, but
3062 * restores r1 and r2 before exit.
3064 _GLOBAL_TOC(kvmppc_save_tm_hv)
3065 EXPORT_SYMBOL_GPL(kvmppc_save_tm_hv)
3066 /* See if we need to handle fake suspend mode */
3069 END_FTR_SECTION_IFCLR(CPU_FTR_P9_TM_HV_ASSIST)
3071 lbz r0, HSTATE_FAKE_SUSPEND(r13) /* Were we fake suspended? */
3073 beq __kvmppc_save_tm
3075 /* The following code handles the fake_suspend = 1 case */
3077 std r0, PPC_LR_STKOFF(r1)
3078 stdu r1, -PPC_MIN_STKFRM(r1)
3083 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
3086 rldicl. r8, r8, 64 - MSR_TS_S_LG, 62 /* Did we actually hrfid? */
3089 bl pnv_power9_force_smt4_catch
3090 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
3093 /* We have to treclaim here because that's the only way to do S->N */
3094 li r3, TM_CAUSE_KVM_RESCHED
3098 * We were in fake suspend, so we are not going to save the
3099 * register state as the guest checkpointed state (since
3100 * we already have it), therefore we can now use any volatile GPR.
3101 * In fact treclaim in fake suspend state doesn't modify
3106 bl pnv_power9_force_smt4_release
3107 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
3111 mfspr r3, SPRN_PSSCR
3112 /* PSSCR_FAKE_SUSPEND is a write-only bit, but clear it anyway */
3113 li r0, PSSCR_FAKE_SUSPEND
3115 mtspr SPRN_PSSCR, r3
3117 /* Don't save TEXASR, use value from last exit in real suspend state */
3118 ld r9, HSTATE_KVM_VCPU(r13)
3119 mfspr r5, SPRN_TFHAR
3120 mfspr r6, SPRN_TFIAR
3121 std r5, VCPU_TFHAR(r9)
3122 std r6, VCPU_TFIAR(r9)
3124 addi r1, r1, PPC_MIN_STKFRM
3125 ld r0, PPC_LR_STKOFF(r1)
3130 * Restore transactional state and TM-related registers.
3131 * Called with r3 pointing to the vcpu struct
3132 * and r4 containing the guest MSR value.
3133 * r5 is non-zero iff non-volatile register state needs to be maintained.
3134 * This potentially modifies all checkpointed registers.
3135 * It restores r1 and r2 from the PACA.
3137 _GLOBAL_TOC(kvmppc_restore_tm_hv)
3138 EXPORT_SYMBOL_GPL(kvmppc_restore_tm_hv)
3140 * If we are doing TM emulation for the guest on a POWER9 DD2,
3141 * then we don't actually do a trechkpt -- we either set up
3142 * fake-suspend mode, or emulate a TM rollback.
3145 b __kvmppc_restore_tm
3146 END_FTR_SECTION_IFCLR(CPU_FTR_P9_TM_HV_ASSIST)
3148 std r0, PPC_LR_STKOFF(r1)
3151 stb r0, HSTATE_FAKE_SUSPEND(r13)
3153 /* Turn on TM so we can restore TM SPRs */
3156 rldimi r5, r0, MSR_TM_LG, 63-MSR_TM_LG
3160 * The user may change these outside of a transaction, so they must
3161 * always be context switched.
3163 ld r5, VCPU_TFHAR(r3)
3164 ld r6, VCPU_TFIAR(r3)
3165 ld r7, VCPU_TEXASR(r3)
3166 mtspr SPRN_TFHAR, r5
3167 mtspr SPRN_TFIAR, r6
3168 mtspr SPRN_TEXASR, r7
3170 rldicl. r5, r4, 64 - MSR_TS_S_LG, 62
3171 beqlr /* TM not active in guest */
3173 /* Make sure the failure summary is set */
3174 oris r7, r7, (TEXASR_FS)@h
3175 mtspr SPRN_TEXASR, r7
3177 cmpwi r5, 1 /* check for suspended state */
3179 stb r5, HSTATE_FAKE_SUSPEND(r13)
3180 b 9f /* and return */
3181 10: stdu r1, -PPC_MIN_STKFRM(r1)
3182 /* guest is in transactional state, so simulate rollback */
3183 bl kvmhv_emulate_tm_rollback
3185 addi r1, r1, PPC_MIN_STKFRM
3186 9: ld r0, PPC_LR_STKOFF(r1)
3189 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
3192 * We come here if we get any exception or interrupt while we are
3193 * executing host real mode code while in guest MMU context.
3194 * r12 is (CR << 32) | vector
3195 * r13 points to our PACA
3196 * r12 is saved in HSTATE_SCRATCH0(r13)
3197 * ctr is saved in HSTATE_SCRATCH1(r13) if RELOCATABLE
3198 * r9 is saved in HSTATE_SCRATCH2(r13)
3199 * r13 is saved in HSPRG1
3200 * cfar is saved in HSTATE_CFAR(r13)
3201 * ppr is saved in HSTATE_PPR(r13)
3203 kvmppc_bad_host_intr:
3205 * Switch to the emergency stack, but start half-way down in
3206 * case we were already on it.
3210 ld r1, PACAEMERGSP(r13)
3211 subi r1, r1, THREAD_SIZE/2 + INT_FRAME_SIZE
3224 mfspr r3, SPRN_HSRR0
3225 mfspr r4, SPRN_HSRR1
3227 mfspr r6, SPRN_HDSISR
3229 1: mfspr r3, SPRN_SRR0
3232 mfspr r6, SPRN_DSISR
3237 ld r9, HSTATE_SCRATCH2(r13)
3238 ld r12, HSTATE_SCRATCH0(r13)
3243 ld r5, HSTATE_CFAR(r13)
3244 std r5, ORIG_GPR3(r1)
3246 #ifdef CONFIG_RELOCATABLE
3247 ld r4, HSTATE_SCRATCH1(r13)
3252 lbz r6, PACAIRQSOFTMASK(r13)
3258 LOAD_REG_IMMEDIATE(3, 0x7265677368657265)
3259 std r3, STACK_FRAME_OVERHEAD-16(r1)
3262 * On POWER9 do a minimal restore of the MMU and call C code,
3263 * which will print a message and panic.
3264 * XXX On POWER7 and POWER8, we just spin here since we don't
3265 * know what the other threads are doing (and we don't want to
3266 * coordinate with them) - but at least we now have register state
3267 * in memory that we might be able to look at from another CPU.
3271 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
3272 ld r9, HSTATE_KVM_VCPU(r13)
3273 ld r10, VCPU_KVM(r9)
3278 mtspr SPRN_CIABR, r0
3279 mtspr SPRN_DAWRX, r0
3281 BEGIN_MMU_FTR_SECTION
3283 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
3288 ld r8, PACA_SLBSHADOWPTR(r13)
3289 .rept SLB_NUM_BOLTED
3290 li r3, SLBSHADOW_SAVEAREA
3294 andis. r7, r5, SLB_ESID_V@h
3300 4: lwz r7, KVM_HOST_LPID(r10)
3303 ld r8, KVM_HOST_LPCR(r10)
3306 li r0, KVM_GUEST_MODE_NONE
3307 stb r0, HSTATE_IN_GUEST(r13)
3310 * Turn on the MMU and jump to C code
3314 addi r3, r3, 9f - 5b
3316 rldimi r3, r4, 62, 0 /* ensure 0xc000000000000000 bits are set */
3317 ld r4, PACAKMSR(r13)
3321 9: addi r3, r1, STACK_FRAME_OVERHEAD
3322 bl kvmppc_bad_interrupt
3326 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
3327 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
3328 * r11 has the guest MSR value (in/out)
3329 * r9 has a vcpu pointer (in)
3330 * r0 is used as a scratch register
3332 kvmppc_msr_interrupt:
3333 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
3334 cmpwi r0, 2 /* Check if we are in transactional state.. */
3335 ld r11, VCPU_INTR_MSR(r9)
3337 /* ... if transactional, change to suspended */
3339 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
3343 * Load up guest PMU state. R3 points to the vcpu struct.
3345 _GLOBAL(kvmhv_load_guest_pmu)
3346 EXPORT_SYMBOL_GPL(kvmhv_load_guest_pmu)
3350 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
3351 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
3354 ld r3, VCPU_MMCR(r4)
3355 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
3356 cmpwi r5, MMCR0_PMAO
3357 beql kvmppc_fix_pmao
3358 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
3359 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
3360 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
3361 lwz r6, VCPU_PMC + 8(r4)
3362 lwz r7, VCPU_PMC + 12(r4)
3363 lwz r8, VCPU_PMC + 16(r4)
3364 lwz r9, VCPU_PMC + 20(r4)
3371 ld r3, VCPU_MMCR(r4)
3372 ld r5, VCPU_MMCR + 8(r4)
3373 ld r6, VCPU_MMCR + 16(r4)
3374 ld r7, VCPU_SIAR(r4)
3375 ld r8, VCPU_SDAR(r4)
3376 mtspr SPRN_MMCR1, r5
3377 mtspr SPRN_MMCRA, r6
3381 ld r5, VCPU_MMCR + 24(r4)
3382 ld r6, VCPU_SIER(r4)
3383 mtspr SPRN_MMCR2, r5
3385 BEGIN_FTR_SECTION_NESTED(96)
3386 lwz r7, VCPU_PMC + 24(r4)
3387 lwz r8, VCPU_PMC + 28(r4)
3388 ld r9, VCPU_MMCR + 32(r4)
3389 mtspr SPRN_SPMC1, r7
3390 mtspr SPRN_SPMC2, r8
3391 mtspr SPRN_MMCRS, r9
3392 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
3393 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3394 mtspr SPRN_MMCR0, r3
3400 * Reload host PMU state saved in the PACA by kvmhv_save_host_pmu.
3402 _GLOBAL(kvmhv_load_host_pmu)
3403 EXPORT_SYMBOL_GPL(kvmhv_load_host_pmu)
3405 lbz r4, PACA_PMCINUSE(r13) /* is the host using the PMU? */
3407 beq 23f /* skip if not */
3409 ld r3, HSTATE_MMCR0(r13)
3410 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
3411 cmpwi r4, MMCR0_PMAO
3412 beql kvmppc_fix_pmao
3413 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
3414 lwz r3, HSTATE_PMC1(r13)
3415 lwz r4, HSTATE_PMC2(r13)
3416 lwz r5, HSTATE_PMC3(r13)
3417 lwz r6, HSTATE_PMC4(r13)
3418 lwz r8, HSTATE_PMC5(r13)
3419 lwz r9, HSTATE_PMC6(r13)
3426 ld r3, HSTATE_MMCR0(r13)
3427 ld r4, HSTATE_MMCR1(r13)
3428 ld r5, HSTATE_MMCRA(r13)
3429 ld r6, HSTATE_SIAR(r13)
3430 ld r7, HSTATE_SDAR(r13)
3431 mtspr SPRN_MMCR1, r4
3432 mtspr SPRN_MMCRA, r5
3436 ld r8, HSTATE_MMCR2(r13)
3437 ld r9, HSTATE_SIER(r13)
3438 mtspr SPRN_MMCR2, r8
3440 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3441 mtspr SPRN_MMCR0, r3
3447 * Save guest PMU state into the vcpu struct.
3448 * r3 = vcpu, r4 = full save flag (PMU in use flag set in VPA)
3450 _GLOBAL(kvmhv_save_guest_pmu)
3451 EXPORT_SYMBOL_GPL(kvmhv_save_guest_pmu)
3456 * POWER8 seems to have a hardware bug where setting
3457 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
3458 * when some counters are already negative doesn't seem
3459 * to cause a performance monitor alert (and hence interrupt).
3460 * The effect of this is that when saving the PMU state,
3461 * if there is no PMU alert pending when we read MMCR0
3462 * before freezing the counters, but one becomes pending
3463 * before we read the counters, we lose it.
3464 * To work around this, we need a way to freeze the counters
3465 * before reading MMCR0. Normally, freezing the counters
3466 * is done by writing MMCR0 (to set MMCR0[FC]) which
3467 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
3468 * we can also freeze the counters using MMCR2, by writing
3469 * 1s to all the counter freeze condition bits (there are
3470 * 9 bits each for 6 counters).
3472 li r3, -1 /* set all freeze bits */
3474 mfspr r10, SPRN_MMCR2
3475 mtspr SPRN_MMCR2, r3
3477 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3479 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
3480 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
3481 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
3482 mfspr r6, SPRN_MMCRA
3483 /* Clear MMCRA in order to disable SDAR updates */
3485 mtspr SPRN_MMCRA, r7
3487 cmpwi r8, 0 /* did they ask for PMU stuff to be saved? */
3489 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
3491 21: mfspr r5, SPRN_MMCR1
3494 std r4, VCPU_MMCR(r9)
3495 std r5, VCPU_MMCR + 8(r9)
3496 std r6, VCPU_MMCR + 16(r9)
3498 std r10, VCPU_MMCR + 24(r9)
3499 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3500 std r7, VCPU_SIAR(r9)
3501 std r8, VCPU_SDAR(r9)
3508 stw r3, VCPU_PMC(r9)
3509 stw r4, VCPU_PMC + 4(r9)
3510 stw r5, VCPU_PMC + 8(r9)
3511 stw r6, VCPU_PMC + 12(r9)
3512 stw r7, VCPU_PMC + 16(r9)
3513 stw r8, VCPU_PMC + 20(r9)
3516 std r5, VCPU_SIER(r9)
3517 BEGIN_FTR_SECTION_NESTED(96)
3518 mfspr r6, SPRN_SPMC1
3519 mfspr r7, SPRN_SPMC2
3520 mfspr r8, SPRN_MMCRS
3521 stw r6, VCPU_PMC + 24(r9)
3522 stw r7, VCPU_PMC + 28(r9)
3523 std r8, VCPU_MMCR + 32(r9)
3525 mtspr SPRN_MMCRS, r4
3526 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
3527 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3531 * This works around a hardware bug on POWER8E processors, where
3532 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
3533 * performance monitor interrupt. Instead, when we need to have
3534 * an interrupt pending, we have to arrange for a counter to overflow.
3538 mtspr SPRN_MMCR2, r3
3539 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
3540 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
3541 mtspr SPRN_MMCR0, r3
3548 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
3550 * Start timing an activity
3551 * r3 = pointer to time accumulation struct, r4 = vcpu
3554 ld r5, HSTATE_KVM_VCORE(r13)
3555 ld r6, VCORE_TB_OFFSET_APPL(r5)
3557 subf r5, r6, r5 /* subtract current timebase offset */
3558 std r3, VCPU_CUR_ACTIVITY(r4)
3559 std r5, VCPU_ACTIVITY_START(r4)
3563 * Accumulate time to one activity and start another.
3564 * r3 = pointer to new time accumulation struct, r4 = vcpu
3566 kvmhv_accumulate_time:
3567 ld r5, HSTATE_KVM_VCORE(r13)
3568 ld r8, VCORE_TB_OFFSET_APPL(r5)
3569 ld r5, VCPU_CUR_ACTIVITY(r4)
3570 ld r6, VCPU_ACTIVITY_START(r4)
3571 std r3, VCPU_CUR_ACTIVITY(r4)
3573 subf r7, r8, r7 /* subtract current timebase offset */
3574 std r7, VCPU_ACTIVITY_START(r4)
3578 ld r8, TAS_SEQCOUNT(r5)
3581 std r8, TAS_SEQCOUNT(r5)
3583 ld r7, TAS_TOTAL(r5)
3585 std r7, TAS_TOTAL(r5)
3591 3: std r3, TAS_MIN(r5)
3597 std r8, TAS_SEQCOUNT(r5)
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