arch/powerpc/lib/sstep.c

   1 /*
   2  * Single-step support.
   3  *
   4  * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/kprobes.h>
  13 #include <linux/ptrace.h>
  14 #include <linux/prefetch.h>
  15 #include <asm/sstep.h>
  16 #include <asm/processor.h>
  17 #include <linux/uaccess.h>
  18 #include <asm/cpu_has_feature.h>
  19 #include <asm/cputable.h>
  20
  21 extern char system_call_common[];
  22
  23 #ifdef CONFIG_PPC64
  24 /* Bits in SRR1 that are copied from MSR */
  25 #define MSR_MASK        0xffffffff87c0ffffUL
  26 #else
  27 #define MSR_MASK        0x87c0ffff
  28 #endif
  29
  30 /* Bits in XER */
  31 #define XER_SO          0x80000000U
  32 #define XER_OV          0x40000000U
  33 #define XER_CA          0x20000000U
  34 #define XER_OV32        0x00080000U
  35 #define XER_CA32        0x00040000U
  36
  37 #ifdef CONFIG_PPC_FPU
  38 /*
  39  * Functions in ldstfp.S
  40  */
  41 extern void get_fpr(int rn, double *p);
  42 extern void put_fpr(int rn, const double *p);
  43 extern void get_vr(int rn, __vector128 *p);
  44 extern void put_vr(int rn, __vector128 *p);
  45 extern void load_vsrn(int vsr, const void *p);
  46 extern void store_vsrn(int vsr, void *p);
  47 extern void conv_sp_to_dp(const float *sp, double *dp);
  48 extern void conv_dp_to_sp(const double *dp, float *sp);
  49 #endif
  50
  51 #ifdef __powerpc64__
  52 /*
  53  * Functions in quad.S
  54  */
  55 extern int do_lq(unsigned long ea, unsigned long *regs);
  56 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
  57 extern int do_lqarx(unsigned long ea, unsigned long *regs);
  58 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
  59                     unsigned int *crp);
  60 #endif
  61
  62 #ifdef __LITTLE_ENDIAN__
  63 #define IS_LE   1
  64 #define IS_BE   0
  65 #else
  66 #define IS_LE   0
  67 #define IS_BE   1
  68 #endif
  69
  70 /*
  71  * Emulate the truncation of 64 bit values in 32-bit mode.
  72  */
  73 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr,
  74                                                         unsigned long val)
  75 {
  76 #ifdef __powerpc64__
  77         if ((msr & MSR_64BIT) == 0)
  78                 val &= 0xffffffffUL;
  79 #endif
  80         return val;
  81 }
  82
  83 /*
  84  * Determine whether a conditional branch instruction would branch.
  85  */
  86 static nokprobe_inline int branch_taken(unsigned int instr,
  87                                         const struct pt_regs *regs,
  88                                         struct instruction_op *op)
  89 {
  90         unsigned int bo = (instr >> 21) & 0x1f;
  91         unsigned int bi;
  92
  93         if ((bo & 4) == 0) {
  94                 /* decrement counter */
  95                 op->type |= DECCTR;
  96                 if (((bo >> 1) & 1) ^ (regs->ctr == 1))
  97                         return 0;
  98         }
  99         if ((bo & 0x10) == 0) {
 100                 /* check bit from CR */
 101                 bi = (instr >> 16) & 0x1f;
 102                 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
 103                         return 0;
 104         }
 105         return 1;
 106 }
 107
 108 static nokprobe_inline long address_ok(struct pt_regs *regs,
 109                                        unsigned long ea, int nb)
 110 {
 111         if (!user_mode(regs))
 112                 return 1;
 113         if (__access_ok(ea, nb, USER_DS))
 114                 return 1;
 115         if (__access_ok(ea, 1, USER_DS))
 116                 /* Access overlaps the end of the user region */
 117                 regs->dar = USER_DS.seg;
 118         else
 119                 regs->dar = ea;
 120         return 0;
 121 }
 122
 123 /*
 124  * Calculate effective address for a D-form instruction
 125  */
 126 static nokprobe_inline unsigned long dform_ea(unsigned int instr,
 127                                               const struct pt_regs *regs)
 128 {
 129         int ra;
 130         unsigned long ea;
 131
 132         ra = (instr >> 16) & 0x1f;
 133         ea = (signed short) instr;              /* sign-extend */
 134         if (ra)
 135                 ea += regs->gpr[ra];
 136
 137         return ea;
 138 }
 139
 140 #ifdef __powerpc64__
 141 /*
 142  * Calculate effective address for a DS-form instruction
 143  */
 144 static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
 145                                                const struct pt_regs *regs)
 146 {
 147         int ra;
 148         unsigned long ea;
 149
 150         ra = (instr >> 16) & 0x1f;
 151         ea = (signed short) (instr & ~3);       /* sign-extend */
 152         if (ra)
 153                 ea += regs->gpr[ra];
 154
 155         return ea;
 156 }
 157
 158 /*
 159  * Calculate effective address for a DQ-form instruction
 160  */
 161 static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
 162                                                const struct pt_regs *regs)
 163 {
 164         int ra;
 165         unsigned long ea;
 166
 167         ra = (instr >> 16) & 0x1f;
 168         ea = (signed short) (instr & ~0xf);     /* sign-extend */
 169         if (ra)
 170                 ea += regs->gpr[ra];
 171
 172         return ea;
 173 }
 174 #endif /* __powerpc64 */
 175
 176 /*
 177  * Calculate effective address for an X-form instruction
 178  */
 179 static nokprobe_inline unsigned long xform_ea(unsigned int instr,
 180                                               const struct pt_regs *regs)
 181 {
 182         int ra, rb;
 183         unsigned long ea;
 184
 185         ra = (instr >> 16) & 0x1f;
 186         rb = (instr >> 11) & 0x1f;
 187         ea = regs->gpr[rb];
 188         if (ra)
 189                 ea += regs->gpr[ra];
 190
 191         return ea;
 192 }
 193
 194 /*
 195  * Return the largest power of 2, not greater than sizeof(unsigned long),
 196  * such that x is a multiple of it.
 197  */
 198 static nokprobe_inline unsigned long max_align(unsigned long x)
 199 {
 200         x |= sizeof(unsigned long);
 201         return x & -x;          /* isolates rightmost bit */
 202 }
 203
 204 static nokprobe_inline unsigned long byterev_2(unsigned long x)
 205 {
 206         return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
 207 }
 208
 209 static nokprobe_inline unsigned long byterev_4(unsigned long x)
 210 {
 211         return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
 212                 ((x & 0xff00) << 8) | ((x & 0xff) << 24);
 213 }
 214
 215 #ifdef __powerpc64__
 216 static nokprobe_inline unsigned long byterev_8(unsigned long x)
 217 {
 218         return (byterev_4(x) << 32) | byterev_4(x >> 32);
 219 }
 220 #endif
 221
 222 static nokprobe_inline void do_byte_reverse(void *ptr, int nb)
 223 {
 224         switch (nb) {
 225         case 2:
 226                 *(u16 *)ptr = byterev_2(*(u16 *)ptr);
 227                 break;
 228         case 4:
 229                 *(u32 *)ptr = byterev_4(*(u32 *)ptr);
 230                 break;
 231 #ifdef __powerpc64__
 232         case 8:
 233                 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr);
 234                 break;
 235         case 16: {
 236                 unsigned long *up = (unsigned long *)ptr;
 237                 unsigned long tmp;
 238                 tmp = byterev_8(up[0]);
 239                 up[0] = byterev_8(up[1]);
 240                 up[1] = tmp;
 241                 break;
 242         }
 243 #endif
 244         default:
 245                 WARN_ON_ONCE(1);
 246         }
 247 }
 248
 249 static nokprobe_inline int read_mem_aligned(unsigned long *dest,
 250                                             unsigned long ea, int nb,
 251                                             struct pt_regs *regs)
 252 {
 253         int err = 0;
 254         unsigned long x = 0;
 255
 256         switch (nb) {
 257         case 1:
 258                 err = __get_user(x, (unsigned char __user *) ea);
 259                 break;
 260         case 2:
 261                 err = __get_user(x, (unsigned short __user *) ea);
 262                 break;
 263         case 4:
 264                 err = __get_user(x, (unsigned int __user *) ea);
 265                 break;
 266 #ifdef __powerpc64__
 267         case 8:
 268                 err = __get_user(x, (unsigned long __user *) ea);
 269                 break;
 270 #endif
 271         }
 272         if (!err)
 273                 *dest = x;
 274         else
 275                 regs->dar = ea;
 276         return err;
 277 }
 278
 279 /*
 280  * Copy from userspace to a buffer, using the largest possible
 281  * aligned accesses, up to sizeof(long).
 282  */
 283 static nokprobe_inline int copy_mem_in(u8 *dest, unsigned long ea, int nb,
 284                                        struct pt_regs *regs)
 285 {
 286         int err = 0;
 287         int c;
 288
 289         for (; nb > 0; nb -= c) {
 290                 c = max_align(ea);
 291                 if (c > nb)
 292                         c = max_align(nb);
 293                 switch (c) {
 294                 case 1:
 295                         err = __get_user(*dest, (unsigned char __user *) ea);
 296                         break;
 297                 case 2:
 298                         err = __get_user(*(u16 *)dest,
 299                                          (unsigned short __user *) ea);
 300                         break;
 301                 case 4:
 302                         err = __get_user(*(u32 *)dest,
 303                                          (unsigned int __user *) ea);
 304                         break;
 305 #ifdef __powerpc64__
 306                 case 8:
 307                         err = __get_user(*(unsigned long *)dest,
 308                                          (unsigned long __user *) ea);
 309                         break;
 310 #endif
 311                 }
 312                 if (err) {
 313                         regs->dar = ea;
 314                         return err;
 315                 }
 316                 dest += c;
 317                 ea += c;
 318         }
 319         return 0;
 320 }
 321
 322 static nokprobe_inline int read_mem_unaligned(unsigned long *dest,
 323                                               unsigned long ea, int nb,
 324                                               struct pt_regs *regs)
 325 {
 326         union {
 327                 unsigned long ul;
 328                 u8 b[sizeof(unsigned long)];
 329         } u;
 330         int i;
 331         int err;
 332
 333         u.ul = 0;
 334         i = IS_BE ? sizeof(unsigned long) - nb : 0;
 335         err = copy_mem_in(&u.b[i], ea, nb, regs);
 336         if (!err)
 337                 *dest = u.ul;
 338         return err;
 339 }
 340
 341 /*
 342  * Read memory at address ea for nb bytes, return 0 for success
 343  * or -EFAULT if an error occurred.  N.B. nb must be 1, 2, 4 or 8.
 344  * If nb < sizeof(long), the result is right-justified on BE systems.
 345  */
 346 static int read_mem(unsigned long *dest, unsigned long ea, int nb,
 347                               struct pt_regs *regs)
 348 {
 349         if (!address_ok(regs, ea, nb))
 350                 return -EFAULT;
 351         if ((ea & (nb - 1)) == 0)
 352                 return read_mem_aligned(dest, ea, nb, regs);
 353         return read_mem_unaligned(dest, ea, nb, regs);
 354 }
 355 NOKPROBE_SYMBOL(read_mem);
 356
 357 static nokprobe_inline int write_mem_aligned(unsigned long val,
 358                                              unsigned long ea, int nb,
 359                                              struct pt_regs *regs)
 360 {
 361         int err = 0;
 362
 363         switch (nb) {
 364         case 1:
 365                 err = __put_user(val, (unsigned char __user *) ea);
 366                 break;
 367         case 2:
 368                 err = __put_user(val, (unsigned short __user *) ea);
 369                 break;
 370         case 4:
 371                 err = __put_user(val, (unsigned int __user *) ea);
 372                 break;
 373 #ifdef __powerpc64__
 374         case 8:
 375                 err = __put_user(val, (unsigned long __user *) ea);
 376                 break;
 377 #endif
 378         }
 379         if (err)
 380                 regs->dar = ea;
 381         return err;
 382 }
 383
 384 /*
 385  * Copy from a buffer to userspace, using the largest possible
 386  * aligned accesses, up to sizeof(long).
 387  */
 388 static nokprobe_inline int copy_mem_out(u8 *dest, unsigned long ea, int nb,
 389                                         struct pt_regs *regs)
 390 {
 391         int err = 0;
 392         int c;
 393
 394         for (; nb > 0; nb -= c) {
 395                 c = max_align(ea);
 396                 if (c > nb)
 397                         c = max_align(nb);
 398                 switch (c) {
 399                 case 1:
 400                         err = __put_user(*dest, (unsigned char __user *) ea);
 401                         break;
 402                 case 2:
 403                         err = __put_user(*(u16 *)dest,
 404                                          (unsigned short __user *) ea);
 405                         break;
 406                 case 4:
 407                         err = __put_user(*(u32 *)dest,
 408                                          (unsigned int __user *) ea);
 409                         break;
 410 #ifdef __powerpc64__
 411                 case 8:
 412                         err = __put_user(*(unsigned long *)dest,
 413                                          (unsigned long __user *) ea);
 414                         break;
 415 #endif
 416                 }
 417                 if (err) {
 418                         regs->dar = ea;
 419                         return err;
 420                 }
 421                 dest += c;
 422                 ea += c;
 423         }
 424         return 0;
 425 }
 426
 427 static nokprobe_inline int write_mem_unaligned(unsigned long val,
 428                                                unsigned long ea, int nb,
 429                                                struct pt_regs *regs)
 430 {
 431         union {
 432                 unsigned long ul;
 433                 u8 b[sizeof(unsigned long)];
 434         } u;
 435         int i;
 436
 437         u.ul = val;
 438         i = IS_BE ? sizeof(unsigned long) - nb : 0;
 439         return copy_mem_out(&u.b[i], ea, nb, regs);
 440 }
 441
 442 /*
 443  * Write memory at address ea for nb bytes, return 0 for success
 444  * or -EFAULT if an error occurred.  N.B. nb must be 1, 2, 4 or 8.
 445  */
 446 static int write_mem(unsigned long val, unsigned long ea, int nb,
 447                                struct pt_regs *regs)
 448 {
 449         if (!address_ok(regs, ea, nb))
 450                 return -EFAULT;
 451         if ((ea & (nb - 1)) == 0)
 452                 return write_mem_aligned(val, ea, nb, regs);
 453         return write_mem_unaligned(val, ea, nb, regs);
 454 }
 455 NOKPROBE_SYMBOL(write_mem);
 456
 457 #ifdef CONFIG_PPC_FPU
 458 /*
 459  * These access either the real FP register or the image in the
 460  * thread_struct, depending on regs->msr & MSR_FP.
 461  */
 462 static int do_fp_load(struct instruction_op *op, unsigned long ea,
 463                       struct pt_regs *regs, bool cross_endian)
 464 {
 465         int err, rn, nb;
 466         union {
 467                 int i;
 468                 unsigned int u;
 469                 float f;
 470                 double d[2];
 471                 unsigned long l[2];
 472                 u8 b[2 * sizeof(double)];
 473         } u;
 474
 475         nb = GETSIZE(op->type);
 476         if (!address_ok(regs, ea, nb))
 477                 return -EFAULT;
 478         rn = op->reg;
 479         err = copy_mem_in(u.b, ea, nb, regs);
 480         if (err)
 481                 return err;
 482         if (unlikely(cross_endian)) {
 483                 do_byte_reverse(u.b, min(nb, 8));
 484                 if (nb == 16)
 485                         do_byte_reverse(&u.b[8], 8);
 486         }
 487         preempt_disable();
 488         if (nb == 4) {
 489                 if (op->type & FPCONV)
 490                         conv_sp_to_dp(&u.f, &u.d[0]);
 491                 else if (op->type & SIGNEXT)
 492                         u.l[0] = u.i;
 493                 else
 494                         u.l[0] = u.u;
 495         }
 496         if (regs->msr & MSR_FP)
 497                 put_fpr(rn, &u.d[0]);
 498         else
 499                 current->thread.TS_FPR(rn) = u.l[0];
 500         if (nb == 16) {
 501                 /* lfdp */
 502                 rn |= 1;
 503                 if (regs->msr & MSR_FP)
 504                         put_fpr(rn, &u.d[1]);
 505                 else
 506                         current->thread.TS_FPR(rn) = u.l[1];
 507         }
 508         preempt_enable();
 509         return 0;
 510 }
 511 NOKPROBE_SYMBOL(do_fp_load);
 512
 513 static int do_fp_store(struct instruction_op *op, unsigned long ea,
 514                        struct pt_regs *regs, bool cross_endian)
 515 {
 516         int rn, nb;
 517         union {
 518                 unsigned int u;
 519                 float f;
 520                 double d[2];
 521                 unsigned long l[2];
 522                 u8 b[2 * sizeof(double)];
 523         } u;
 524
 525         nb = GETSIZE(op->type);
 526         if (!address_ok(regs, ea, nb))
 527                 return -EFAULT;
 528         rn = op->reg;
 529         preempt_disable();
 530         if (regs->msr & MSR_FP)
 531                 get_fpr(rn, &u.d[0]);
 532         else
 533                 u.l[0] = current->thread.TS_FPR(rn);
 534         if (nb == 4) {
 535                 if (op->type & FPCONV)
 536                         conv_dp_to_sp(&u.d[0], &u.f);
 537                 else
 538                         u.u = u.l[0];
 539         }
 540         if (nb == 16) {
 541                 rn |= 1;
 542                 if (regs->msr & MSR_FP)
 543                         get_fpr(rn, &u.d[1]);
 544                 else
 545                         u.l[1] = current->thread.TS_FPR(rn);
 546         }
 547         preempt_enable();
 548         if (unlikely(cross_endian)) {
 549                 do_byte_reverse(u.b, min(nb, 8));
 550                 if (nb == 16)
 551                         do_byte_reverse(&u.b[8], 8);
 552         }
 553         return copy_mem_out(u.b, ea, nb, regs);
 554 }
 555 NOKPROBE_SYMBOL(do_fp_store);
 556 #endif
 557
 558 #ifdef CONFIG_ALTIVEC
 559 /* For Altivec/VMX, no need to worry about alignment */
 560 static nokprobe_inline int do_vec_load(int rn, unsigned long ea,
 561                                        int size, struct pt_regs *regs,
 562                                        bool cross_endian)
 563 {
 564         int err;
 565         union {
 566                 __vector128 v;
 567                 u8 b[sizeof(__vector128)];
 568         } u = {};
 569
 570         if (!address_ok(regs, ea & ~0xfUL, 16))
 571                 return -EFAULT;
 572         /* align to multiple of size */
 573         ea &= ~(size - 1);
 574         err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs);
 575         if (err)
 576                 return err;
 577         if (unlikely(cross_endian))
 578                 do_byte_reverse(&u.b[ea & 0xf], size);
 579         preempt_disable();
 580         if (regs->msr & MSR_VEC)
 581                 put_vr(rn, &u.v);
 582         else
 583                 current->thread.vr_state.vr[rn] = u.v;
 584         preempt_enable();
 585         return 0;
 586 }
 587
 588 static nokprobe_inline int do_vec_store(int rn, unsigned long ea,
 589                                         int size, struct pt_regs *regs,
 590                                         bool cross_endian)
 591 {
 592         union {
 593                 __vector128 v;
 594                 u8 b[sizeof(__vector128)];
 595         } u;
 596
 597         if (!address_ok(regs, ea & ~0xfUL, 16))
 598                 return -EFAULT;
 599         /* align to multiple of size */
 600         ea &= ~(size - 1);
 601
 602         preempt_disable();
 603         if (regs->msr & MSR_VEC)
 604                 get_vr(rn, &u.v);
 605         else
 606                 u.v = current->thread.vr_state.vr[rn];
 607         preempt_enable();
 608         if (unlikely(cross_endian))
 609                 do_byte_reverse(&u.b[ea & 0xf], size);
 610         return copy_mem_out(&u.b[ea & 0xf], ea, size, regs);
 611 }
 612 #endif /* CONFIG_ALTIVEC */
 613
 614 #ifdef __powerpc64__
 615 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,
 616                                       int reg, bool cross_endian)
 617 {
 618         int err;
 619
 620         if (!address_ok(regs, ea, 16))
 621                 return -EFAULT;
 622         /* if aligned, should be atomic */
 623         if ((ea & 0xf) == 0) {
 624                 err = do_lq(ea, &regs->gpr[reg]);
 625         } else {
 626                 err = read_mem(&regs->gpr[reg + IS_LE], ea, 8, regs);
 627                 if (!err)
 628                         err = read_mem(&regs->gpr[reg + IS_BE], ea + 8, 8, regs);
 629         }
 630         if (!err && unlikely(cross_endian))
 631                 do_byte_reverse(&regs->gpr[reg], 16);
 632         return err;
 633 }
 634
 635 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,
 636                                        int reg, bool cross_endian)
 637 {
 638         int err;
 639         unsigned long vals[2];
 640
 641         if (!address_ok(regs, ea, 16))
 642                 return -EFAULT;
 643         vals[0] = regs->gpr[reg];
 644         vals[1] = regs->gpr[reg + 1];
 645         if (unlikely(cross_endian))
 646                 do_byte_reverse(vals, 16);
 647
 648         /* if aligned, should be atomic */
 649         if ((ea & 0xf) == 0)
 650                 return do_stq(ea, vals[0], vals[1]);
 651
 652         err = write_mem(vals[IS_LE], ea, 8, regs);
 653         if (!err)
 654                 err = write_mem(vals[IS_BE], ea + 8, 8, regs);
 655         return err;
 656 }
 657 #endif /* __powerpc64 */
 658
 659 #ifdef CONFIG_VSX
 660 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
 661                       const void *mem, bool rev)
 662 {
 663         int size, read_size;
 664         int i, j;
 665         const unsigned int *wp;
 666         const unsigned short *hp;
 667         const unsigned char *bp;
 668
 669         size = GETSIZE(op->type);
 670         reg->d[0] = reg->d[1] = 0;
 671
 672         switch (op->element_size) {
 673         case 16:
 674                 /* whole vector; lxv[x] or lxvl[l] */
 675                 if (size == 0)
 676                         break;
 677                 memcpy(reg, mem, size);
 678                 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
 679                         rev = !rev;
 680                 if (rev)
 681                         do_byte_reverse(reg, 16);
 682                 break;
 683         case 8:
 684                 /* scalar loads, lxvd2x, lxvdsx */
 685                 read_size = (size >= 8) ? 8 : size;
 686                 i = IS_LE ? 8 : 8 - read_size;
 687                 memcpy(&reg->b[i], mem, read_size);
 688                 if (rev)
 689                         do_byte_reverse(&reg->b[i], 8);
 690                 if (size < 8) {
 691                         if (op->type & SIGNEXT) {
 692                                 /* size == 4 is the only case here */
 693                                 reg->d[IS_LE] = (signed int) reg->d[IS_LE];
 694                         } else if (op->vsx_flags & VSX_FPCONV) {
 695                                 preempt_disable();
 696                                 conv_sp_to_dp(&reg->fp[1 + IS_LE],
 697                                               &reg->dp[IS_LE]);
 698                                 preempt_enable();
 699                         }
 700                 } else {
 701                         if (size == 16) {
 702                                 unsigned long v = *(unsigned long *)(mem + 8);
 703                                 reg->d[IS_BE] = !rev ? v : byterev_8(v);
 704                         } else if (op->vsx_flags & VSX_SPLAT)
 705                                 reg->d[IS_BE] = reg->d[IS_LE];
 706                 }
 707                 break;
 708         case 4:
 709                 /* lxvw4x, lxvwsx */
 710                 wp = mem;
 711                 for (j = 0; j < size / 4; ++j) {
 712                         i = IS_LE ? 3 - j : j;
 713                         reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);
 714                 }
 715                 if (op->vsx_flags & VSX_SPLAT) {
 716                         u32 val = reg->w[IS_LE ? 3 : 0];
 717                         for (; j < 4; ++j) {
 718                                 i = IS_LE ? 3 - j : j;
 719                                 reg->w[i] = val;
 720                         }
 721                 }
 722                 break;
 723         case 2:
 724                 /* lxvh8x */
 725                 hp = mem;
 726                 for (j = 0; j < size / 2; ++j) {
 727                         i = IS_LE ? 7 - j : j;
 728                         reg->h[i] = !rev ? *hp++ : byterev_2(*hp++);
 729                 }
 730                 break;
 731         case 1:
 732                 /* lxvb16x */
 733                 bp = mem;
 734                 for (j = 0; j < size; ++j) {
 735                         i = IS_LE ? 15 - j : j;
 736                         reg->b[i] = *bp++;
 737                 }
 738                 break;
 739         }
 740 }
 741 EXPORT_SYMBOL_GPL(emulate_vsx_load);
 742 NOKPROBE_SYMBOL(emulate_vsx_load);
 743
 744 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
 745                        void *mem, bool rev)
 746 {
 747         int size, write_size;
 748         int i, j;
 749         union vsx_reg buf;
 750         unsigned int *wp;
 751         unsigned short *hp;
 752         unsigned char *bp;
 753
 754         size = GETSIZE(op->type);
 755
 756         switch (op->element_size) {
 757         case 16:
 758                 /* stxv, stxvx, stxvl, stxvll */
 759                 if (size == 0)
 760                         break;
 761                 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
 762                         rev = !rev;
 763                 if (rev) {
 764                         /* reverse 16 bytes */
 765                         buf.d[0] = byterev_8(reg->d[1]);
 766                         buf.d[1] = byterev_8(reg->d[0]);
 767                         reg = &buf;
 768                 }
 769                 memcpy(mem, reg, size);
 770                 break;
 771         case 8:
 772                 /* scalar stores, stxvd2x */
 773                 write_size = (size >= 8) ? 8 : size;
 774                 i = IS_LE ? 8 : 8 - write_size;
 775                 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
 776                         buf.d[0] = buf.d[1] = 0;
 777                         preempt_disable();
 778                         conv_dp_to_sp(&reg->dp[IS_LE], &buf.fp[1 + IS_LE]);
 779                         preempt_enable();
 780                         reg = &buf;
 781                 }
 782                 memcpy(mem, &reg->b[i], write_size);
 783                 if (size == 16)
 784                         memcpy(mem + 8, &reg->d[IS_BE], 8);
 785                 if (unlikely(rev)) {
 786                         do_byte_reverse(mem, write_size);
 787                         if (size == 16)
 788                                 do_byte_reverse(mem + 8, 8);
 789                 }
 790                 break;
 791         case 4:
 792                 /* stxvw4x */
 793                 wp = mem;
 794                 for (j = 0; j < size / 4; ++j) {
 795                         i = IS_LE ? 3 - j : j;
 796                         *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);
 797                 }
 798                 break;
 799         case 2:
 800                 /* stxvh8x */
 801                 hp = mem;
 802                 for (j = 0; j < size / 2; ++j) {
 803                         i = IS_LE ? 7 - j : j;
 804                         *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);
 805                 }
 806                 break;
 807         case 1:
 808                 /* stvxb16x */
 809                 bp = mem;
 810                 for (j = 0; j < size; ++j) {
 811                         i = IS_LE ? 15 - j : j;
 812                         *bp++ = reg->b[i];
 813                 }
 814                 break;
 815         }
 816 }
 817 EXPORT_SYMBOL_GPL(emulate_vsx_store);
 818 NOKPROBE_SYMBOL(emulate_vsx_store);
 819
 820 static nokprobe_inline int do_vsx_load(struct instruction_op *op,
 821                                        unsigned long ea, struct pt_regs *regs,
 822                                        bool cross_endian)
 823 {
 824         int reg = op->reg;
 825         u8 mem[16];
 826         union vsx_reg buf;
 827         int size = GETSIZE(op->type);
 828
 829         if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
 830                 return -EFAULT;
 831
 832         emulate_vsx_load(op, &buf, mem, cross_endian);
 833         preempt_disable();
 834         if (reg < 32) {
 835                 /* FP regs + extensions */
 836                 if (regs->msr & MSR_FP) {
 837                         load_vsrn(reg, &buf);
 838                 } else {
 839                         current->thread.fp_state.fpr[reg][0] = buf.d[0];
 840                         current->thread.fp_state.fpr[reg][1] = buf.d[1];
 841                 }
 842         } else {
 843                 if (regs->msr & MSR_VEC)
 844                         load_vsrn(reg, &buf);
 845                 else
 846                         current->thread.vr_state.vr[reg - 32] = buf.v;
 847         }
 848         preempt_enable();
 849         return 0;
 850 }
 851
 852 static nokprobe_inline int do_vsx_store(struct instruction_op *op,
 853                                         unsigned long ea, struct pt_regs *regs,
 854                                         bool cross_endian)
 855 {
 856         int reg = op->reg;
 857         u8 mem[16];
 858         union vsx_reg buf;
 859         int size = GETSIZE(op->type);
 860
 861         if (!address_ok(regs, ea, size))
 862                 return -EFAULT;
 863
 864         preempt_disable();
 865         if (reg < 32) {
 866                 /* FP regs + extensions */
 867                 if (regs->msr & MSR_FP) {
 868                         store_vsrn(reg, &buf);
 869                 } else {
 870                         buf.d[0] = current->thread.fp_state.fpr[reg][0];
 871                         buf.d[1] = current->thread.fp_state.fpr[reg][1];
 872                 }
 873         } else {
 874                 if (regs->msr & MSR_VEC)
 875                         store_vsrn(reg, &buf);
 876                 else
 877                         buf.v = current->thread.vr_state.vr[reg - 32];
 878         }
 879         preempt_enable();
 880         emulate_vsx_store(op, &buf, mem, cross_endian);
 881         return  copy_mem_out(mem, ea, size, regs);
 882 }
 883 #endif /* CONFIG_VSX */
 884
 885 int emulate_dcbz(unsigned long ea, struct pt_regs *regs)
 886 {
 887         int err;
 888         unsigned long i, size;
 889
 890 #ifdef __powerpc64__
 891         size = ppc64_caches.l1d.block_size;
 892         if (!(regs->msr & MSR_64BIT))
 893                 ea &= 0xffffffffUL;
 894 #else
 895         size = L1_CACHE_BYTES;
 896 #endif
 897         ea &= ~(size - 1);
 898         if (!address_ok(regs, ea, size))
 899                 return -EFAULT;
 900         for (i = 0; i < size; i += sizeof(long)) {
 901                 err = __put_user(0, (unsigned long __user *) (ea + i));
 902                 if (err) {
 903                         regs->dar = ea;
 904                         return err;
 905                 }
 906         }
 907         return 0;
 908 }
 909 NOKPROBE_SYMBOL(emulate_dcbz);
 910
 911 #define __put_user_asmx(x, addr, err, op, cr)           \
 912         __asm__ __volatile__(                           \
 913                 "1:     " op " %2,0,%3\n"               \
 914                 "       mfcr    %1\n"                   \
 915                 "2:\n"                                  \
 916                 ".section .fixup,\"ax\"\n"              \
 917                 "3:     li      %0,%4\n"                \
 918                 "       b       2b\n"                   \
 919                 ".previous\n"                           \
 920                 EX_TABLE(1b, 3b)                        \
 921                 : "=r" (err), "=r" (cr)                 \
 922                 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
 923
 924 #define __get_user_asmx(x, addr, err, op)               \
 925         __asm__ __volatile__(                           \
 926                 "1:     "op" %1,0,%2\n"                 \
 927                 "2:\n"                                  \
 928                 ".section .fixup,\"ax\"\n"              \
 929                 "3:     li      %0,%3\n"                \
 930                 "       b       2b\n"                   \
 931                 ".previous\n"                           \
 932                 EX_TABLE(1b, 3b)                        \
 933                 : "=r" (err), "=r" (x)                  \
 934                 : "r" (addr), "i" (-EFAULT), "0" (err))
 935
 936 #define __cacheop_user_asmx(addr, err, op)              \
 937         __asm__ __volatile__(                           \
 938                 "1:     "op" 0,%1\n"                    \
 939                 "2:\n"                                  \
 940                 ".section .fixup,\"ax\"\n"              \
 941                 "3:     li      %0,%3\n"                \
 942                 "       b       2b\n"                   \
 943                 ".previous\n"                           \
 944                 EX_TABLE(1b, 3b)                        \
 945                 : "=r" (err)                            \
 946                 : "r" (addr), "i" (-EFAULT), "0" (err))
 947
 948 static nokprobe_inline void set_cr0(const struct pt_regs *regs,
 949                                     struct instruction_op *op)
 950 {
 951         long val = op->val;
 952
 953         op->type |= SETCC;
 954         op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
 955 #ifdef __powerpc64__
 956         if (!(regs->msr & MSR_64BIT))
 957                 val = (int) val;
 958 #endif
 959         if (val < 0)
 960                 op->ccval |= 0x80000000;
 961         else if (val > 0)
 962                 op->ccval |= 0x40000000;
 963         else
 964                 op->ccval |= 0x20000000;
 965 }
 966
 967 static nokprobe_inline void set_ca32(struct instruction_op *op, bool val)
 968 {
 969         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
 970                 if (val)
 971                         op->xerval |= XER_CA32;
 972                 else
 973                         op->xerval &= ~XER_CA32;
 974         }
 975 }
 976
 977 static nokprobe_inline void add_with_carry(const struct pt_regs *regs,
 978                                      struct instruction_op *op, int rd,
 979                                      unsigned long val1, unsigned long val2,
 980                                      unsigned long carry_in)
 981 {
 982         unsigned long val = val1 + val2;
 983
 984         if (carry_in)
 985                 ++val;
 986         op->type = COMPUTE + SETREG + SETXER;
 987         op->reg = rd;
 988         op->val = val;
 989 #ifdef __powerpc64__
 990         if (!(regs->msr & MSR_64BIT)) {
 991                 val = (unsigned int) val;
 992                 val1 = (unsigned int) val1;
 993         }
 994 #endif
 995         op->xerval = regs->xer;
 996         if (val < val1 || (carry_in && val == val1))
 997                 op->xerval |= XER_CA;
 998         else
 999                 op->xerval &= ~XER_CA;
1000
1001         set_ca32(op, (unsigned int)val < (unsigned int)val1 ||
1002                         (carry_in && (unsigned int)val == (unsigned int)val1));
1003 }
1004
1005 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs,
1006                                           struct instruction_op *op,
1007                                           long v1, long v2, int crfld)
1008 {
1009         unsigned int crval, shift;
1010
1011         op->type = COMPUTE + SETCC;
1012         crval = (regs->xer >> 31) & 1;          /* get SO bit */
1013         if (v1 < v2)
1014                 crval |= 8;
1015         else if (v1 > v2)
1016                 crval |= 4;
1017         else
1018                 crval |= 2;
1019         shift = (7 - crfld) * 4;
1020         op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1021 }
1022
1023 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs,
1024                                             struct instruction_op *op,
1025                                             unsigned long v1,
1026                                             unsigned long v2, int crfld)
1027 {
1028         unsigned int crval, shift;
1029
1030         op->type = COMPUTE + SETCC;
1031         crval = (regs->xer >> 31) & 1;          /* get SO bit */
1032         if (v1 < v2)
1033                 crval |= 8;
1034         else if (v1 > v2)
1035                 crval |= 4;
1036         else
1037                 crval |= 2;
1038         shift = (7 - crfld) * 4;
1039         op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1040 }
1041
1042 static nokprobe_inline void do_cmpb(const struct pt_regs *regs,
1043                                     struct instruction_op *op,
1044                                     unsigned long v1, unsigned long v2)
1045 {
1046         unsigned long long out_val, mask;
1047         int i;
1048
1049         out_val = 0;
1050         for (i = 0; i < 8; i++) {
1051                 mask = 0xffUL << (i * 8);
1052                 if ((v1 & mask) == (v2 & mask))
1053                         out_val |= mask;
1054         }
1055         op->val = out_val;
1056 }
1057
1058 /*
1059  * The size parameter is used to adjust the equivalent popcnt instruction.
1060  * popcntb = 8, popcntw = 32, popcntd = 64
1061  */
1062 static nokprobe_inline void do_popcnt(const struct pt_regs *regs,
1063                                       struct instruction_op *op,
1064                                       unsigned long v1, int size)
1065 {
1066         unsigned long long out = v1;
1067
1068         out -= (out >> 1) & 0x5555555555555555ULL;
1069         out = (0x3333333333333333ULL & out) +
1070               (0x3333333333333333ULL & (out >> 2));
1071         out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1072
1073         if (size == 8) {        /* popcntb */
1074                 op->val = out;
1075                 return;
1076         }
1077         out += out >> 8;
1078         out += out >> 16;
1079         if (size == 32) {       /* popcntw */
1080                 op->val = out & 0x0000003f0000003fULL;
1081                 return;
1082         }
1083
1084         out = (out + (out >> 32)) & 0x7f;
1085         op->val = out;  /* popcntd */
1086 }
1087
1088 #ifdef CONFIG_PPC64
1089 static nokprobe_inline void do_bpermd(const struct pt_regs *regs,
1090                                       struct instruction_op *op,
1091                                       unsigned long v1, unsigned long v2)
1092 {
1093         unsigned char perm, idx;
1094         unsigned int i;
1095
1096         perm = 0;
1097         for (i = 0; i < 8; i++) {
1098                 idx = (v1 >> (i * 8)) & 0xff;
1099                 if (idx < 64)
1100                         if (v2 & PPC_BIT(idx))
1101                                 perm |= 1 << i;
1102         }
1103         op->val = perm;
1104 }
1105 #endif /* CONFIG_PPC64 */
1106 /*
1107  * The size parameter adjusts the equivalent prty instruction.
1108  * prtyw = 32, prtyd = 64
1109  */
1110 static nokprobe_inline void do_prty(const struct pt_regs *regs,
1111                                     struct instruction_op *op,
1112                                     unsigned long v, int size)
1113 {
1114         unsigned long long res = v ^ (v >> 8);
1115
1116         res ^= res >> 16;
1117         if (size == 32) {               /* prtyw */
1118                 op->val = res & 0x0000000100000001ULL;
1119                 return;
1120         }
1121
1122         res ^= res >> 32;
1123         op->val = res & 1;      /*prtyd */
1124 }
1125
1126 static nokprobe_inline int trap_compare(long v1, long v2)
1127 {
1128         int ret = 0;
1129
1130         if (v1 < v2)
1131                 ret |= 0x10;
1132         else if (v1 > v2)
1133                 ret |= 0x08;
1134         else
1135                 ret |= 0x04;
1136         if ((unsigned long)v1 < (unsigned long)v2)
1137                 ret |= 0x02;
1138         else if ((unsigned long)v1 > (unsigned long)v2)
1139                 ret |= 0x01;
1140         return ret;
1141 }
1142
1143 /*
1144  * Elements of 32-bit rotate and mask instructions.
1145  */
1146 #define MASK32(mb, me)  ((0xffffffffUL >> (mb)) + \
1147                          ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
1148 #ifdef __powerpc64__
1149 #define MASK64_L(mb)    (~0UL >> (mb))
1150 #define MASK64_R(me)    ((signed long)-0x8000000000000000L >> (me))
1151 #define MASK64(mb, me)  (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
1152 #define DATA32(x)       (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
1153 #else
1154 #define DATA32(x)       (x)
1155 #endif
1156 #define ROTATE(x, n)    ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
1157
1158 /*
1159  * Decode an instruction, and return information about it in *op
1160  * without changing *regs.
1161  * Integer arithmetic and logical instructions, branches, and barrier
1162  * instructions can be emulated just using the information in *op.
1163  *
1164  * Return value is 1 if the instruction can be emulated just by
1165  * updating *regs with the information in *op, -1 if we need the
1166  * GPRs but *regs doesn't contain the full register set, or 0
1167  * otherwise.
1168  */
1169 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1170                   unsigned int instr)
1171 {
1172         unsigned int opcode, ra, rb, rc, rd, spr, u;
1173         unsigned long int imm;
1174         unsigned long int val, val2;
1175         unsigned int mb, me, sh;
1176         long ival;
1177
1178         op->type = COMPUTE;
1179
1180         opcode = instr >> 26;
1181         switch (opcode) {
1182         case 16:        /* bc */
1183                 op->type = BRANCH;
1184                 imm = (signed short)(instr & 0xfffc);
1185                 if ((instr & 2) == 0)
1186                         imm += regs->nip;
1187                 op->val = truncate_if_32bit(regs->msr, imm);
1188                 if (instr & 1)
1189                         op->type |= SETLK;
1190                 if (branch_taken(instr, regs, op))
1191                         op->type |= BRTAKEN;
1192                 return 1;
1193 #ifdef CONFIG_PPC64
1194         case 17:        /* sc */
1195                 if ((instr & 0xfe2) == 2)
1196                         op->type = SYSCALL;
1197                 else
1198                         op->type = UNKNOWN;
1199                 return 0;
1200 #endif
1201         case 18:        /* b */
1202                 op->type = BRANCH | BRTAKEN;
1203                 imm = instr & 0x03fffffc;
1204                 if (imm & 0x02000000)
1205                         imm -= 0x04000000;
1206                 if ((instr & 2) == 0)
1207                         imm += regs->nip;
1208                 op->val = truncate_if_32bit(regs->msr, imm);
1209                 if (instr & 1)
1210                         op->type |= SETLK;
1211                 return 1;
1212         case 19:
1213                 switch ((instr >> 1) & 0x3ff) {
1214                 case 0:         /* mcrf */
1215                         op->type = COMPUTE + SETCC;
1216                         rd = 7 - ((instr >> 23) & 0x7);
1217                         ra = 7 - ((instr >> 18) & 0x7);
1218                         rd *= 4;
1219                         ra *= 4;
1220                         val = (regs->ccr >> ra) & 0xf;
1221                         op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
1222                         return 1;
1223
1224                 case 16:        /* bclr */
1225                 case 528:       /* bcctr */
1226                         op->type = BRANCH;
1227                         imm = (instr & 0x400)? regs->ctr: regs->link;
1228                         op->val = truncate_if_32bit(regs->msr, imm);
1229                         if (instr & 1)
1230                                 op->type |= SETLK;
1231                         if (branch_taken(instr, regs, op))
1232                                 op->type |= BRTAKEN;
1233                         return 1;
1234
1235                 case 18:        /* rfid, scary */
1236                         if (regs->msr & MSR_PR)
1237                                 goto priv;
1238                         op->type = RFI;
1239                         return 0;
1240
1241                 case 150:       /* isync */
1242                         op->type = BARRIER | BARRIER_ISYNC;
1243                         return 1;
1244
1245                 case 33:        /* crnor */
1246                 case 129:       /* crandc */
1247                 case 193:       /* crxor */
1248                 case 225:       /* crnand */
1249                 case 257:       /* crand */
1250                 case 289:       /* creqv */
1251                 case 417:       /* crorc */
1252                 case 449:       /* cror */
1253                         op->type = COMPUTE + SETCC;
1254                         ra = (instr >> 16) & 0x1f;
1255                         rb = (instr >> 11) & 0x1f;
1256                         rd = (instr >> 21) & 0x1f;
1257                         ra = (regs->ccr >> (31 - ra)) & 1;
1258                         rb = (regs->ccr >> (31 - rb)) & 1;
1259                         val = (instr >> (6 + ra * 2 + rb)) & 1;
1260                         op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
1261                                 (val << (31 - rd));
1262                         return 1;
1263                 }
1264                 break;
1265         case 31:
1266                 switch ((instr >> 1) & 0x3ff) {
1267                 case 598:       /* sync */
1268                         op->type = BARRIER + BARRIER_SYNC;
1269 #ifdef __powerpc64__
1270                         switch ((instr >> 21) & 3) {
1271                         case 1:         /* lwsync */
1272                                 op->type = BARRIER + BARRIER_LWSYNC;
1273                                 break;
1274                         case 2:         /* ptesync */
1275                                 op->type = BARRIER + BARRIER_PTESYNC;
1276                                 break;
1277                         }
1278 #endif
1279                         return 1;
1280
1281                 case 854:       /* eieio */
1282                         op->type = BARRIER + BARRIER_EIEIO;
1283                         return 1;
1284                 }
1285                 break;
1286         }
1287
1288         /* Following cases refer to regs->gpr[], so we need all regs */
1289         if (!FULL_REGS(regs))
1290                 return -1;
1291
1292         rd = (instr >> 21) & 0x1f;
1293         ra = (instr >> 16) & 0x1f;
1294         rb = (instr >> 11) & 0x1f;
1295         rc = (instr >> 6) & 0x1f;
1296
1297         switch (opcode) {
1298 #ifdef __powerpc64__
1299         case 2:         /* tdi */
1300                 if (rd & trap_compare(regs->gpr[ra], (short) instr))
1301                         goto trap;
1302                 return 1;
1303 #endif
1304         case 3:         /* twi */
1305                 if (rd & trap_compare((int)regs->gpr[ra], (short) instr))
1306                         goto trap;
1307                 return 1;
1308
1309 #ifdef __powerpc64__
1310         case 4:
1311                 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1312                         return -1;
1313
1314                 switch (instr & 0x3f) {
1315                 case 48:        /* maddhd */
1316                         asm volatile(PPC_MADDHD(%0, %1, %2, %3) :
1317                                      "=r" (op->val) : "r" (regs->gpr[ra]),
1318                                      "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1319                         goto compute_done;
1320
1321                 case 49:        /* maddhdu */
1322                         asm volatile(PPC_MADDHDU(%0, %1, %2, %3) :
1323                                      "=r" (op->val) : "r" (regs->gpr[ra]),
1324                                      "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1325                         goto compute_done;
1326
1327                 case 51:        /* maddld */
1328                         asm volatile(PPC_MADDLD(%0, %1, %2, %3) :
1329                                      "=r" (op->val) : "r" (regs->gpr[ra]),
1330                                      "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1331                         goto compute_done;
1332                 }
1333
1334                 /*
1335                  * There are other instructions from ISA 3.0 with the same
1336                  * primary opcode which do not have emulation support yet.
1337                  */
1338                 return -1;
1339 #endif
1340
1341         case 7:         /* mulli */
1342                 op->val = regs->gpr[ra] * (short) instr;
1343                 goto compute_done;
1344
1345         case 8:         /* subfic */
1346                 imm = (short) instr;
1347                 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1348                 return 1;
1349
1350         case 10:        /* cmpli */
1351                 imm = (unsigned short) instr;
1352                 val = regs->gpr[ra];
1353 #ifdef __powerpc64__
1354                 if ((rd & 1) == 0)
1355                         val = (unsigned int) val;
1356 #endif
1357                 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1358                 return 1;
1359
1360         case 11:        /* cmpi */
1361                 imm = (short) instr;
1362                 val = regs->gpr[ra];
1363 #ifdef __powerpc64__
1364                 if ((rd & 1) == 0)
1365                         val = (int) val;
1366 #endif
1367                 do_cmp_signed(regs, op, val, imm, rd >> 2);
1368                 return 1;
1369
1370         case 12:        /* addic */
1371                 imm = (short) instr;
1372                 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1373                 return 1;
1374
1375         case 13:        /* addic. */
1376                 imm = (short) instr;
1377                 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1378                 set_cr0(regs, op);
1379                 return 1;
1380
1381         case 14:        /* addi */
1382                 imm = (short) instr;
1383                 if (ra)
1384                         imm += regs->gpr[ra];
1385                 op->val = imm;
1386                 goto compute_done;
1387
1388         case 15:        /* addis */
1389                 imm = ((short) instr) << 16;
1390                 if (ra)
1391                         imm += regs->gpr[ra];
1392                 op->val = imm;
1393                 goto compute_done;
1394
1395         case 19:
1396                 if (((instr >> 1) & 0x1f) == 2) {
1397                         /* addpcis */
1398                         imm = (short) (instr & 0xffc1); /* d0 + d2 fields */
1399                         imm |= (instr >> 15) & 0x3e;    /* d1 field */
1400                         op->val = regs->nip + (imm << 16) + 4;
1401                         goto compute_done;
1402                 }
1403                 op->type = UNKNOWN;
1404                 return 0;
1405
1406         case 20:        /* rlwimi */
1407                 mb = (instr >> 6) & 0x1f;
1408                 me = (instr >> 1) & 0x1f;
1409                 val = DATA32(regs->gpr[rd]);
1410                 imm = MASK32(mb, me);
1411                 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1412                 goto logical_done;
1413
1414         case 21:        /* rlwinm */
1415                 mb = (instr >> 6) & 0x1f;
1416                 me = (instr >> 1) & 0x1f;
1417                 val = DATA32(regs->gpr[rd]);
1418                 op->val = ROTATE(val, rb) & MASK32(mb, me);
1419                 goto logical_done;
1420
1421         case 23:        /* rlwnm */
1422                 mb = (instr >> 6) & 0x1f;
1423                 me = (instr >> 1) & 0x1f;
1424                 rb = regs->gpr[rb] & 0x1f;
1425                 val = DATA32(regs->gpr[rd]);
1426                 op->val = ROTATE(val, rb) & MASK32(mb, me);
1427                 goto logical_done;
1428
1429         case 24:        /* ori */
1430                 op->val = regs->gpr[rd] | (unsigned short) instr;
1431                 goto logical_done_nocc;
1432
1433         case 25:        /* oris */
1434                 imm = (unsigned short) instr;
1435                 op->val = regs->gpr[rd] | (imm << 16);
1436                 goto logical_done_nocc;
1437
1438         case 26:        /* xori */
1439                 op->val = regs->gpr[rd] ^ (unsigned short) instr;
1440                 goto logical_done_nocc;
1441
1442         case 27:        /* xoris */
1443                 imm = (unsigned short) instr;
1444                 op->val = regs->gpr[rd] ^ (imm << 16);
1445                 goto logical_done_nocc;
1446
1447         case 28:        /* andi. */
1448                 op->val = regs->gpr[rd] & (unsigned short) instr;
1449                 set_cr0(regs, op);
1450                 goto logical_done_nocc;
1451
1452         case 29:        /* andis. */
1453                 imm = (unsigned short) instr;
1454                 op->val = regs->gpr[rd] & (imm << 16);
1455                 set_cr0(regs, op);
1456                 goto logical_done_nocc;
1457
1458 #ifdef __powerpc64__
1459         case 30:        /* rld* */
1460                 mb = ((instr >> 6) & 0x1f) | (instr & 0x20);
1461                 val = regs->gpr[rd];
1462                 if ((instr & 0x10) == 0) {
1463                         sh = rb | ((instr & 2) << 4);
1464                         val = ROTATE(val, sh);
1465                         switch ((instr >> 2) & 3) {
1466                         case 0:         /* rldicl */
1467                                 val &= MASK64_L(mb);
1468                                 break;
1469                         case 1:         /* rldicr */
1470                                 val &= MASK64_R(mb);
1471                                 break;
1472                         case 2:         /* rldic */
1473                                 val &= MASK64(mb, 63 - sh);
1474                                 break;
1475                         case 3:         /* rldimi */
1476                                 imm = MASK64(mb, 63 - sh);
1477                                 val = (regs->gpr[ra] & ~imm) |
1478                                         (val & imm);
1479                         }
1480                         op->val = val;
1481                         goto logical_done;
1482                 } else {
1483                         sh = regs->gpr[rb] & 0x3f;
1484                         val = ROTATE(val, sh);
1485                         switch ((instr >> 1) & 7) {
1486                         case 0:         /* rldcl */
1487                                 op->val = val & MASK64_L(mb);
1488                                 goto logical_done;
1489                         case 1:         /* rldcr */
1490                                 op->val = val & MASK64_R(mb);
1491                                 goto logical_done;
1492                         }
1493                 }
1494 #endif
1495                 op->type = UNKNOWN;     /* illegal instruction */
1496                 return 0;
1497
1498         case 31:
1499                 /* isel occupies 32 minor opcodes */
1500                 if (((instr >> 1) & 0x1f) == 15) {
1501                         mb = (instr >> 6) & 0x1f; /* bc field */
1502                         val = (regs->ccr >> (31 - mb)) & 1;
1503                         val2 = (ra) ? regs->gpr[ra] : 0;
1504
1505                         op->val = (val) ? val2 : regs->gpr[rb];
1506                         goto compute_done;
1507                 }
1508
1509                 switch ((instr >> 1) & 0x3ff) {
1510                 case 4:         /* tw */
1511                         if (rd == 0x1f ||
1512                             (rd & trap_compare((int)regs->gpr[ra],
1513                                                (int)regs->gpr[rb])))
1514                                 goto trap;
1515                         return 1;
1516 #ifdef __powerpc64__
1517                 case 68:        /* td */
1518                         if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb]))
1519                                 goto trap;
1520                         return 1;
1521 #endif
1522                 case 83:        /* mfmsr */
1523                         if (regs->msr & MSR_PR)
1524                                 goto priv;
1525                         op->type = MFMSR;
1526                         op->reg = rd;
1527                         return 0;
1528                 case 146:       /* mtmsr */
1529                         if (regs->msr & MSR_PR)
1530                                 goto priv;
1531                         op->type = MTMSR;
1532                         op->reg = rd;
1533                         op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1534                         return 0;
1535 #ifdef CONFIG_PPC64
1536                 case 178:       /* mtmsrd */
1537                         if (regs->msr & MSR_PR)
1538                                 goto priv;
1539                         op->type = MTMSR;
1540                         op->reg = rd;
1541                         /* only MSR_EE and MSR_RI get changed if bit 15 set */
1542                         /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
1543                         imm = (instr & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
1544                         op->val = imm;
1545                         return 0;
1546 #endif
1547
1548                 case 19:        /* mfcr */
1549                         imm = 0xffffffffUL;
1550                         if ((instr >> 20) & 1) {
1551                                 imm = 0xf0000000UL;
1552                                 for (sh = 0; sh < 8; ++sh) {
1553                                         if (instr & (0x80000 >> sh))
1554                                                 break;
1555                                         imm >>= 4;
1556                                 }
1557                         }
1558                         op->val = regs->ccr & imm;
1559                         goto compute_done;
1560
1561                 case 144:       /* mtcrf */
1562                         op->type = COMPUTE + SETCC;
1563                         imm = 0xf0000000UL;
1564                         val = regs->gpr[rd];
1565                         op->ccval = regs->ccr;
1566                         for (sh = 0; sh < 8; ++sh) {
1567                                 if (instr & (0x80000 >> sh))
1568                                         op->ccval = (op->ccval & ~imm) |
1569                                                 (val & imm);
1570                                 imm >>= 4;
1571                         }
1572                         return 1;
1573
1574                 case 339:       /* mfspr */
1575                         spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
1576                         op->type = MFSPR;
1577                         op->reg = rd;
1578                         op->spr = spr;
1579                         if (spr == SPRN_XER || spr == SPRN_LR ||
1580                             spr == SPRN_CTR)
1581                                 return 1;
1582                         return 0;
1583
1584                 case 467:       /* mtspr */
1585                         spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
1586                         op->type = MTSPR;
1587                         op->val = regs->gpr[rd];
1588                         op->spr = spr;
1589                         if (spr == SPRN_XER || spr == SPRN_LR ||
1590                             spr == SPRN_CTR)
1591                                 return 1;
1592                         return 0;
1593
1594 /*
1595  * Compare instructions
1596  */
1597                 case 0: /* cmp */
1598                         val = regs->gpr[ra];
1599                         val2 = regs->gpr[rb];
1600 #ifdef __powerpc64__
1601                         if ((rd & 1) == 0) {
1602                                 /* word (32-bit) compare */
1603                                 val = (int) val;
1604                                 val2 = (int) val2;
1605                         }
1606 #endif
1607                         do_cmp_signed(regs, op, val, val2, rd >> 2);
1608                         return 1;
1609
1610                 case 32:        /* cmpl */
1611                         val = regs->gpr[ra];
1612                         val2 = regs->gpr[rb];
1613 #ifdef __powerpc64__
1614                         if ((rd & 1) == 0) {
1615                                 /* word (32-bit) compare */
1616                                 val = (unsigned int) val;
1617                                 val2 = (unsigned int) val2;
1618                         }
1619 #endif
1620                         do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1621                         return 1;
1622
1623                 case 508: /* cmpb */
1624                         do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1625                         goto logical_done_nocc;
1626
1627 /*
1628  * Arithmetic instructions
1629  */
1630                 case 8: /* subfc */
1631                         add_with_carry(regs, op, rd, ~regs->gpr[ra],
1632                                        regs->gpr[rb], 1);
1633                         goto arith_done;
1634 #ifdef __powerpc64__
1635                 case 9: /* mulhdu */
1636                         asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1637                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1638                         goto arith_done;
1639 #endif
1640                 case 10:        /* addc */
1641                         add_with_carry(regs, op, rd, regs->gpr[ra],
1642                                        regs->gpr[rb], 0);
1643                         goto arith_done;
1644
1645                 case 11:        /* mulhwu */
1646                         asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1647                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1648                         goto arith_done;
1649
1650                 case 40:        /* subf */
1651                         op->val = regs->gpr[rb] - regs->gpr[ra];
1652                         goto arith_done;
1653 #ifdef __powerpc64__
1654                 case 73:        /* mulhd */
1655                         asm("mulhd %0,%1,%2" : "=r" (op->val) :
1656                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1657                         goto arith_done;
1658 #endif
1659                 case 75:        /* mulhw */
1660                         asm("mulhw %0,%1,%2" : "=r" (op->val) :
1661                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1662                         goto arith_done;
1663
1664                 case 104:       /* neg */
1665                         op->val = -regs->gpr[ra];
1666                         goto arith_done;
1667
1668                 case 136:       /* subfe */
1669                         add_with_carry(regs, op, rd, ~regs->gpr[ra],
1670                                        regs->gpr[rb], regs->xer & XER_CA);
1671                         goto arith_done;
1672
1673                 case 138:       /* adde */
1674                         add_with_carry(regs, op, rd, regs->gpr[ra],
1675                                        regs->gpr[rb], regs->xer & XER_CA);
1676                         goto arith_done;
1677
1678                 case 200:       /* subfze */
1679                         add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1680                                        regs->xer & XER_CA);
1681                         goto arith_done;
1682
1683                 case 202:       /* addze */
1684                         add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1685                                        regs->xer & XER_CA);
1686                         goto arith_done;
1687
1688                 case 232:       /* subfme */
1689                         add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1690                                        regs->xer & XER_CA);
1691                         goto arith_done;
1692 #ifdef __powerpc64__
1693                 case 233:       /* mulld */
1694                         op->val = regs->gpr[ra] * regs->gpr[rb];
1695                         goto arith_done;
1696 #endif
1697                 case 234:       /* addme */
1698                         add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1699                                        regs->xer & XER_CA);
1700                         goto arith_done;
1701
1702                 case 235:       /* mullw */
1703                         op->val = (long)(int) regs->gpr[ra] *
1704                                 (int) regs->gpr[rb];
1705
1706                         goto arith_done;
1707
1708                 case 266:       /* add */
1709                         op->val = regs->gpr[ra] + regs->gpr[rb];
1710                         goto arith_done;
1711 #ifdef __powerpc64__
1712                 case 457:       /* divdu */
1713                         op->val = regs->gpr[ra] / regs->gpr[rb];
1714                         goto arith_done;
1715 #endif
1716                 case 459:       /* divwu */
1717                         op->val = (unsigned int) regs->gpr[ra] /
1718                                 (unsigned int) regs->gpr[rb];
1719                         goto arith_done;
1720 #ifdef __powerpc64__
1721                 case 489:       /* divd */
1722                         op->val = (long int) regs->gpr[ra] /
1723                                 (long int) regs->gpr[rb];
1724                         goto arith_done;
1725 #endif
1726                 case 491:       /* divw */
1727                         op->val = (int) regs->gpr[ra] /
1728                                 (int) regs->gpr[rb];
1729                         goto arith_done;
1730
1731                 case 755:       /* darn */
1732                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1733                                 return -1;
1734                         switch (ra & 0x3) {
1735                         case 0:
1736                                 /* 32-bit conditioned */
1737                                 asm volatile(PPC_DARN(%0, 0) : "=r" (op->val));
1738                                 goto compute_done;
1739
1740                         case 1:
1741                                 /* 64-bit conditioned */
1742                                 asm volatile(PPC_DARN(%0, 1) : "=r" (op->val));
1743                                 goto compute_done;
1744
1745                         case 2:
1746                                 /* 64-bit raw */
1747                                 asm volatile(PPC_DARN(%0, 2) : "=r" (op->val));
1748                                 goto compute_done;
1749                         }
1750
1751                         return -1;
1752
1753
1754 /*
1755  * Logical instructions
1756  */
1757                 case 26:        /* cntlzw */
1758                         val = (unsigned int) regs->gpr[rd];
1759                         op->val = ( val ? __builtin_clz(val) : 32 );
1760                         goto logical_done;
1761 #ifdef __powerpc64__
1762                 case 58:        /* cntlzd */
1763                         val = regs->gpr[rd];
1764                         op->val = ( val ? __builtin_clzl(val) : 64 );
1765                         goto logical_done;
1766 #endif
1767                 case 28:        /* and */
1768                         op->val = regs->gpr[rd] & regs->gpr[rb];
1769                         goto logical_done;
1770
1771                 case 60:        /* andc */
1772                         op->val = regs->gpr[rd] & ~regs->gpr[rb];
1773                         goto logical_done;
1774
1775                 case 122:       /* popcntb */
1776                         do_popcnt(regs, op, regs->gpr[rd], 8);
1777                         goto logical_done_nocc;
1778
1779                 case 124:       /* nor */
1780                         op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
1781                         goto logical_done;
1782
1783                 case 154:       /* prtyw */
1784                         do_prty(regs, op, regs->gpr[rd], 32);
1785                         goto logical_done_nocc;
1786
1787                 case 186:       /* prtyd */
1788                         do_prty(regs, op, regs->gpr[rd], 64);
1789                         goto logical_done_nocc;
1790 #ifdef CONFIG_PPC64
1791                 case 252:       /* bpermd */
1792                         do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
1793                         goto logical_done_nocc;
1794 #endif
1795                 case 284:       /* xor */
1796                         op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
1797                         goto logical_done;
1798
1799                 case 316:       /* xor */
1800                         op->val = regs->gpr[rd] ^ regs->gpr[rb];
1801                         goto logical_done;
1802
1803                 case 378:       /* popcntw */
1804                         do_popcnt(regs, op, regs->gpr[rd], 32);
1805                         goto logical_done_nocc;
1806
1807                 case 412:       /* orc */
1808                         op->val = regs->gpr[rd] | ~regs->gpr[rb];
1809                         goto logical_done;
1810
1811                 case 444:       /* or */
1812                         op->val = regs->gpr[rd] | regs->gpr[rb];
1813                         goto logical_done;
1814
1815                 case 476:       /* nand */
1816                         op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
1817                         goto logical_done;
1818 #ifdef CONFIG_PPC64
1819                 case 506:       /* popcntd */
1820                         do_popcnt(regs, op, regs->gpr[rd], 64);
1821                         goto logical_done_nocc;
1822 #endif
1823                 case 538:       /* cnttzw */
1824                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1825                                 return -1;
1826                         val = (unsigned int) regs->gpr[rd];
1827                         op->val = (val ? __builtin_ctz(val) : 32);
1828                         goto logical_done;
1829 #ifdef __powerpc64__
1830                 case 570:       /* cnttzd */
1831                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1832                                 return -1;
1833                         val = regs->gpr[rd];
1834                         op->val = (val ? __builtin_ctzl(val) : 64);
1835                         goto logical_done;
1836 #endif
1837                 case 922:       /* extsh */
1838                         op->val = (signed short) regs->gpr[rd];
1839                         goto logical_done;
1840
1841                 case 954:       /* extsb */
1842                         op->val = (signed char) regs->gpr[rd];
1843                         goto logical_done;
1844 #ifdef __powerpc64__
1845                 case 986:       /* extsw */
1846                         op->val = (signed int) regs->gpr[rd];
1847                         goto logical_done;
1848 #endif
1849
1850 /*
1851  * Shift instructions
1852  */
1853                 case 24:        /* slw */
1854                         sh = regs->gpr[rb] & 0x3f;
1855                         if (sh < 32)
1856                                 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
1857                         else
1858                                 op->val = 0;
1859                         goto logical_done;
1860
1861                 case 536:       /* srw */
1862                         sh = regs->gpr[rb] & 0x3f;
1863                         if (sh < 32)
1864                                 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
1865                         else
1866                                 op->val = 0;
1867                         goto logical_done;
1868
1869                 case 792:       /* sraw */
1870                         op->type = COMPUTE + SETREG + SETXER;
1871                         sh = regs->gpr[rb] & 0x3f;
1872                         ival = (signed int) regs->gpr[rd];
1873                         op->val = ival >> (sh < 32 ? sh : 31);
1874                         op->xerval = regs->xer;
1875                         if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0))
1876                                 op->xerval |= XER_CA;
1877                         else
1878                                 op->xerval &= ~XER_CA;
1879                         set_ca32(op, op->xerval & XER_CA);
1880                         goto logical_done;
1881
1882                 case 824:       /* srawi */
1883                         op->type = COMPUTE + SETREG + SETXER;
1884                         sh = rb;
1885                         ival = (signed int) regs->gpr[rd];
1886                         op->val = ival >> sh;
1887                         op->xerval = regs->xer;
1888                         if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
1889                                 op->xerval |= XER_CA;
1890                         else
1891                                 op->xerval &= ~XER_CA;
1892                         set_ca32(op, op->xerval & XER_CA);
1893                         goto logical_done;
1894
1895 #ifdef __powerpc64__
1896                 case 27:        /* sld */
1897                         sh = regs->gpr[rb] & 0x7f;
1898                         if (sh < 64)
1899                                 op->val = regs->gpr[rd] << sh;
1900                         else
1901                                 op->val = 0;
1902                         goto logical_done;
1903
1904                 case 539:       /* srd */
1905                         sh = regs->gpr[rb] & 0x7f;
1906                         if (sh < 64)
1907                                 op->val = regs->gpr[rd] >> sh;
1908                         else
1909                                 op->val = 0;
1910                         goto logical_done;
1911
1912                 case 794:       /* srad */
1913                         op->type = COMPUTE + SETREG + SETXER;
1914                         sh = regs->gpr[rb] & 0x7f;
1915                         ival = (signed long int) regs->gpr[rd];
1916                         op->val = ival >> (sh < 64 ? sh : 63);
1917                         op->xerval = regs->xer;
1918                         if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0))
1919                                 op->xerval |= XER_CA;
1920                         else
1921                                 op->xerval &= ~XER_CA;
1922                         set_ca32(op, op->xerval & XER_CA);
1923                         goto logical_done;
1924
1925                 case 826:       /* sradi with sh_5 = 0 */
1926                 case 827:       /* sradi with sh_5 = 1 */
1927                         op->type = COMPUTE + SETREG + SETXER;
1928                         sh = rb | ((instr & 2) << 4);
1929                         ival = (signed long int) regs->gpr[rd];
1930                         op->val = ival >> sh;
1931                         op->xerval = regs->xer;
1932                         if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
1933                                 op->xerval |= XER_CA;
1934                         else
1935                                 op->xerval &= ~XER_CA;
1936                         set_ca32(op, op->xerval & XER_CA);
1937                         goto logical_done;
1938 #endif /* __powerpc64__ */
1939
1940 /*
1941  * Cache instructions
1942  */
1943                 case 54:        /* dcbst */
1944                         op->type = MKOP(CACHEOP, DCBST, 0);
1945                         op->ea = xform_ea(instr, regs);
1946                         return 0;
1947
1948                 case 86:        /* dcbf */
1949                         op->type = MKOP(CACHEOP, DCBF, 0);
1950                         op->ea = xform_ea(instr, regs);
1951                         return 0;
1952
1953                 case 246:       /* dcbtst */
1954                         op->type = MKOP(CACHEOP, DCBTST, 0);
1955                         op->ea = xform_ea(instr, regs);
1956                         op->reg = rd;
1957                         return 0;
1958
1959                 case 278:       /* dcbt */
1960                         op->type = MKOP(CACHEOP, DCBTST, 0);
1961                         op->ea = xform_ea(instr, regs);
1962                         op->reg = rd;
1963                         return 0;
1964
1965                 case 982:       /* icbi */
1966                         op->type = MKOP(CACHEOP, ICBI, 0);
1967                         op->ea = xform_ea(instr, regs);
1968                         return 0;
1969
1970                 case 1014:      /* dcbz */
1971                         op->type = MKOP(CACHEOP, DCBZ, 0);
1972                         op->ea = xform_ea(instr, regs);
1973                         return 0;
1974                 }
1975                 break;
1976         }
1977
1978 /*
1979  * Loads and stores.
1980  */
1981         op->type = UNKNOWN;
1982         op->update_reg = ra;
1983         op->reg = rd;
1984         op->val = regs->gpr[rd];
1985         u = (instr >> 20) & UPDATE;
1986         op->vsx_flags = 0;
1987
1988         switch (opcode) {
1989         case 31:
1990                 u = instr & UPDATE;
1991                 op->ea = xform_ea(instr, regs);
1992                 switch ((instr >> 1) & 0x3ff) {
1993                 case 20:        /* lwarx */
1994                         op->type = MKOP(LARX, 0, 4);
1995                         break;
1996
1997                 case 150:       /* stwcx. */
1998                         op->type = MKOP(STCX, 0, 4);
1999                         break;
2000
2001 #ifdef __powerpc64__
2002                 case 84:        /* ldarx */
2003                         op->type = MKOP(LARX, 0, 8);
2004                         break;
2005
2006                 case 214:       /* stdcx. */
2007                         op->type = MKOP(STCX, 0, 8);
2008                         break;
2009
2010                 case 52:        /* lbarx */
2011                         op->type = MKOP(LARX, 0, 1);
2012                         break;
2013
2014                 case 694:       /* stbcx. */
2015                         op->type = MKOP(STCX, 0, 1);
2016                         break;
2017
2018                 case 116:       /* lharx */
2019                         op->type = MKOP(LARX, 0, 2);
2020                         break;
2021
2022                 case 726:       /* sthcx. */
2023                         op->type = MKOP(STCX, 0, 2);
2024                         break;
2025
2026                 case 276:       /* lqarx */
2027                         if (!((rd & 1) || rd == ra || rd == rb))
2028                                 op->type = MKOP(LARX, 0, 16);
2029                         break;
2030
2031                 case 182:       /* stqcx. */
2032                         if (!(rd & 1))
2033                                 op->type = MKOP(STCX, 0, 16);
2034                         break;
2035 #endif
2036
2037                 case 23:        /* lwzx */
2038                 case 55:        /* lwzux */
2039                         op->type = MKOP(LOAD, u, 4);
2040                         break;
2041
2042                 case 87:        /* lbzx */
2043                 case 119:       /* lbzux */
2044                         op->type = MKOP(LOAD, u, 1);
2045                         break;
2046
2047 #ifdef CONFIG_ALTIVEC
2048                 /*
2049                  * Note: for the load/store vector element instructions,
2050                  * bits of the EA say which field of the VMX register to use.
2051                  */
2052                 case 7:         /* lvebx */
2053                         op->type = MKOP(LOAD_VMX, 0, 1);
2054                         op->element_size = 1;
2055                         break;
2056
2057                 case 39:        /* lvehx */
2058                         op->type = MKOP(LOAD_VMX, 0, 2);
2059                         op->element_size = 2;
2060                         break;
2061
2062                 case 71:        /* lvewx */
2063                         op->type = MKOP(LOAD_VMX, 0, 4);
2064                         op->element_size = 4;
2065                         break;
2066
2067                 case 103:       /* lvx */
2068                 case 359:       /* lvxl */
2069                         op->type = MKOP(LOAD_VMX, 0, 16);
2070                         op->element_size = 16;
2071                         break;
2072
2073                 case 135:       /* stvebx */
2074                         op->type = MKOP(STORE_VMX, 0, 1);
2075                         op->element_size = 1;
2076                         break;
2077
2078                 case 167:       /* stvehx */
2079                         op->type = MKOP(STORE_VMX, 0, 2);
2080                         op->element_size = 2;
2081                         break;
2082
2083                 case 199:       /* stvewx */
2084                         op->type = MKOP(STORE_VMX, 0, 4);
2085                         op->element_size = 4;
2086                         break;
2087
2088                 case 231:       /* stvx */
2089                 case 487:       /* stvxl */
2090                         op->type = MKOP(STORE_VMX, 0, 16);
2091                         break;
2092 #endif /* CONFIG_ALTIVEC */
2093
2094 #ifdef __powerpc64__
2095                 case 21:        /* ldx */
2096                 case 53:        /* ldux */
2097                         op->type = MKOP(LOAD, u, 8);
2098                         break;
2099
2100                 case 149:       /* stdx */
2101                 case 181:       /* stdux */
2102                         op->type = MKOP(STORE, u, 8);
2103                         break;
2104 #endif
2105
2106                 case 151:       /* stwx */
2107                 case 183:       /* stwux */
2108                         op->type = MKOP(STORE, u, 4);
2109                         break;
2110
2111                 case 215:       /* stbx */
2112                 case 247:       /* stbux */
2113                         op->type = MKOP(STORE, u, 1);
2114                         break;
2115
2116                 case 279:       /* lhzx */
2117                 case 311:       /* lhzux */
2118                         op->type = MKOP(LOAD, u, 2);
2119                         break;
2120
2121 #ifdef __powerpc64__
2122                 case 341:       /* lwax */
2123                 case 373:       /* lwaux */
2124                         op->type = MKOP(LOAD, SIGNEXT | u, 4);
2125                         break;
2126 #endif
2127
2128                 case 343:       /* lhax */
2129                 case 375:       /* lhaux */
2130                         op->type = MKOP(LOAD, SIGNEXT | u, 2);
2131                         break;
2132
2133                 case 407:       /* sthx */
2134                 case 439:       /* sthux */
2135                         op->type = MKOP(STORE, u, 2);
2136                         break;
2137
2138 #ifdef __powerpc64__
2139                 case 532:       /* ldbrx */
2140                         op->type = MKOP(LOAD, BYTEREV, 8);
2141                         break;
2142
2143 #endif
2144                 case 533:       /* lswx */
2145                         op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
2146                         break;
2147
2148                 case 534:       /* lwbrx */
2149                         op->type = MKOP(LOAD, BYTEREV, 4);
2150                         break;
2151
2152                 case 597:       /* lswi */
2153                         if (rb == 0)
2154                                 rb = 32;        /* # bytes to load */
2155                         op->type = MKOP(LOAD_MULTI, 0, rb);
2156                         op->ea = ra ? regs->gpr[ra] : 0;
2157                         break;
2158
2159 #ifdef CONFIG_PPC_FPU
2160                 case 535:       /* lfsx */
2161                 case 567:       /* lfsux */
2162                         op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2163                         break;
2164
2165                 case 599:       /* lfdx */
2166                 case 631:       /* lfdux */
2167                         op->type = MKOP(LOAD_FP, u, 8);
2168                         break;
2169
2170                 case 663:       /* stfsx */
2171                 case 695:       /* stfsux */
2172                         op->type = MKOP(STORE_FP, u | FPCONV, 4);
2173                         break;
2174
2175                 case 727:       /* stfdx */
2176                 case 759:       /* stfdux */
2177                         op->type = MKOP(STORE_FP, u, 8);
2178                         break;
2179
2180 #ifdef __powerpc64__
2181                 case 791:       /* lfdpx */
2182                         op->type = MKOP(LOAD_FP, 0, 16);
2183                         break;
2184
2185                 case 855:       /* lfiwax */
2186                         op->type = MKOP(LOAD_FP, SIGNEXT, 4);
2187                         break;
2188
2189                 case 887:       /* lfiwzx */
2190                         op->type = MKOP(LOAD_FP, 0, 4);
2191                         break;
2192
2193                 case 919:       /* stfdpx */
2194                         op->type = MKOP(STORE_FP, 0, 16);
2195                         break;
2196
2197                 case 983:       /* stfiwx */
2198                         op->type = MKOP(STORE_FP, 0, 4);
2199                         break;
2200 #endif /* __powerpc64 */
2201 #endif /* CONFIG_PPC_FPU */
2202
2203 #ifdef __powerpc64__
2204                 case 660:       /* stdbrx */
2205                         op->type = MKOP(STORE, BYTEREV, 8);
2206                         op->val = byterev_8(regs->gpr[rd]);
2207                         break;
2208
2209 #endif
2210                 case 661:       /* stswx */
2211                         op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
2212                         break;
2213
2214                 case 662:       /* stwbrx */
2215                         op->type = MKOP(STORE, BYTEREV, 4);
2216                         op->val = byterev_4(regs->gpr[rd]);
2217                         break;
2218
2219                 case 725:       /* stswi */
2220                         if (rb == 0)
2221                                 rb = 32;        /* # bytes to store */
2222                         op->type = MKOP(STORE_MULTI, 0, rb);
2223                         op->ea = ra ? regs->gpr[ra] : 0;
2224                         break;
2225
2226                 case 790:       /* lhbrx */
2227                         op->type = MKOP(LOAD, BYTEREV, 2);
2228                         break;
2229
2230                 case 918:       /* sthbrx */
2231                         op->type = MKOP(STORE, BYTEREV, 2);
2232                         op->val = byterev_2(regs->gpr[rd]);
2233                         break;
2234
2235 #ifdef CONFIG_VSX
2236                 case 12:        /* lxsiwzx */
2237                         op->reg = rd | ((instr & 1) << 5);
2238                         op->type = MKOP(LOAD_VSX, 0, 4);
2239                         op->element_size = 8;
2240                         break;
2241
2242                 case 76:        /* lxsiwax */
2243                         op->reg = rd | ((instr & 1) << 5);
2244                         op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
2245                         op->element_size = 8;
2246                         break;
2247
2248                 case 140:       /* stxsiwx */
2249                         op->reg = rd | ((instr & 1) << 5);
2250                         op->type = MKOP(STORE_VSX, 0, 4);
2251                         op->element_size = 8;
2252                         break;
2253
2254                 case 268:       /* lxvx */
2255                         op->reg = rd | ((instr & 1) << 5);
2256                         op->type = MKOP(LOAD_VSX, 0, 16);
2257                         op->element_size = 16;
2258                         op->vsx_flags = VSX_CHECK_VEC;
2259                         break;
2260
2261                 case 269:       /* lxvl */
2262                 case 301: {     /* lxvll */
2263                         int nb;
2264                         op->reg = rd | ((instr & 1) << 5);
2265                         op->ea = ra ? regs->gpr[ra] : 0;
2266                         nb = regs->gpr[rb] & 0xff;
2267                         if (nb > 16)
2268                                 nb = 16;
2269                         op->type = MKOP(LOAD_VSX, 0, nb);
2270                         op->element_size = 16;
2271                         op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
2272                                 VSX_CHECK_VEC;
2273                         break;
2274                 }
2275                 case 332:       /* lxvdsx */
2276                         op->reg = rd | ((instr & 1) << 5);
2277                         op->type = MKOP(LOAD_VSX, 0, 8);
2278                         op->element_size = 8;
2279                         op->vsx_flags = VSX_SPLAT;
2280                         break;
2281
2282                 case 364:       /* lxvwsx */
2283                         op->reg = rd | ((instr & 1) << 5);
2284                         op->type = MKOP(LOAD_VSX, 0, 4);
2285                         op->element_size = 4;
2286                         op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
2287                         break;
2288
2289                 case 396:       /* stxvx */
2290                         op->reg = rd | ((instr & 1) << 5);
2291                         op->type = MKOP(STORE_VSX, 0, 16);
2292                         op->element_size = 16;
2293                         op->vsx_flags = VSX_CHECK_VEC;
2294                         break;
2295
2296                 case 397:       /* stxvl */
2297                 case 429: {     /* stxvll */
2298                         int nb;
2299                         op->reg = rd | ((instr & 1) << 5);
2300                         op->ea = ra ? regs->gpr[ra] : 0;
2301                         nb = regs->gpr[rb] & 0xff;
2302                         if (nb > 16)
2303                                 nb = 16;
2304                         op->type = MKOP(STORE_VSX, 0, nb);
2305                         op->element_size = 16;
2306                         op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
2307                                 VSX_CHECK_VEC;
2308                         break;
2309                 }
2310                 case 524:       /* lxsspx */
2311                         op->reg = rd | ((instr & 1) << 5);
2312                         op->type = MKOP(LOAD_VSX, 0, 4);
2313                         op->element_size = 8;
2314                         op->vsx_flags = VSX_FPCONV;
2315                         break;
2316
2317                 case 588:       /* lxsdx */
2318                         op->reg = rd | ((instr & 1) << 5);
2319                         op->type = MKOP(LOAD_VSX, 0, 8);
2320                         op->element_size = 8;
2321                         break;
2322
2323                 case 652:       /* stxsspx */
2324                         op->reg = rd | ((instr & 1) << 5);
2325                         op->type = MKOP(STORE_VSX, 0, 4);
2326                         op->element_size = 8;
2327                         op->vsx_flags = VSX_FPCONV;
2328                         break;
2329
2330                 case 716:       /* stxsdx */
2331                         op->reg = rd | ((instr & 1) << 5);
2332                         op->type = MKOP(STORE_VSX, 0, 8);
2333                         op->element_size = 8;
2334                         break;
2335
2336                 case 780:       /* lxvw4x */
2337                         op->reg = rd | ((instr & 1) << 5);
2338                         op->type = MKOP(LOAD_VSX, 0, 16);
2339                         op->element_size = 4;
2340                         break;
2341
2342                 case 781:       /* lxsibzx */
2343                         op->reg = rd | ((instr & 1) << 5);
2344                         op->type = MKOP(LOAD_VSX, 0, 1);
2345                         op->element_size = 8;
2346                         op->vsx_flags = VSX_CHECK_VEC;
2347                         break;
2348
2349                 case 812:       /* lxvh8x */
2350                         op->reg = rd | ((instr & 1) << 5);
2351                         op->type = MKOP(LOAD_VSX, 0, 16);
2352                         op->element_size = 2;
2353                         op->vsx_flags = VSX_CHECK_VEC;
2354                         break;
2355
2356                 case 813:       /* lxsihzx */
2357                         op->reg = rd | ((instr & 1) << 5);
2358                         op->type = MKOP(LOAD_VSX, 0, 2);
2359                         op->element_size = 8;
2360                         op->vsx_flags = VSX_CHECK_VEC;
2361                         break;
2362
2363                 case 844:       /* lxvd2x */
2364                         op->reg = rd | ((instr & 1) << 5);
2365                         op->type = MKOP(LOAD_VSX, 0, 16);
2366                         op->element_size = 8;
2367                         break;
2368
2369                 case 876:       /* lxvb16x */
2370                         op->reg = rd | ((instr & 1) << 5);
2371                         op->type = MKOP(LOAD_VSX, 0, 16);
2372                         op->element_size = 1;
2373                         op->vsx_flags = VSX_CHECK_VEC;
2374                         break;
2375
2376                 case 908:       /* stxvw4x */
2377                         op->reg = rd | ((instr & 1) << 5);
2378                         op->type = MKOP(STORE_VSX, 0, 16);
2379                         op->element_size = 4;
2380                         break;
2381
2382                 case 909:       /* stxsibx */
2383                         op->reg = rd | ((instr & 1) << 5);
2384                         op->type = MKOP(STORE_VSX, 0, 1);
2385                         op->element_size = 8;
2386                         op->vsx_flags = VSX_CHECK_VEC;
2387                         break;
2388
2389                 case 940:       /* stxvh8x */
2390                         op->reg = rd | ((instr & 1) << 5);
2391                         op->type = MKOP(STORE_VSX, 0, 16);
2392                         op->element_size = 2;
2393                         op->vsx_flags = VSX_CHECK_VEC;
2394                         break;
2395
2396                 case 941:       /* stxsihx */
2397                         op->reg = rd | ((instr & 1) << 5);
2398                         op->type = MKOP(STORE_VSX, 0, 2);
2399                         op->element_size = 8;
2400                         op->vsx_flags = VSX_CHECK_VEC;
2401                         break;
2402
2403                 case 972:       /* stxvd2x */
2404                         op->reg = rd | ((instr & 1) << 5);
2405                         op->type = MKOP(STORE_VSX, 0, 16);
2406                         op->element_size = 8;
2407                         break;
2408
2409                 case 1004:      /* stxvb16x */
2410                         op->reg = rd | ((instr & 1) << 5);
2411                         op->type = MKOP(STORE_VSX, 0, 16);
2412                         op->element_size = 1;
2413                         op->vsx_flags = VSX_CHECK_VEC;
2414                         break;
2415
2416 #endif /* CONFIG_VSX */
2417                 }
2418                 break;
2419
2420         case 32:        /* lwz */
2421         case 33:        /* lwzu */
2422                 op->type = MKOP(LOAD, u, 4);
2423                 op->ea = dform_ea(instr, regs);
2424                 break;
2425
2426         case 34:        /* lbz */
2427         case 35:        /* lbzu */
2428                 op->type = MKOP(LOAD, u, 1);
2429                 op->ea = dform_ea(instr, regs);
2430                 break;
2431
2432         case 36:        /* stw */
2433         case 37:        /* stwu */
2434                 op->type = MKOP(STORE, u, 4);
2435                 op->ea = dform_ea(instr, regs);
2436                 break;
2437
2438         case 38:        /* stb */
2439         case 39:        /* stbu */
2440                 op->type = MKOP(STORE, u, 1);
2441                 op->ea = dform_ea(instr, regs);
2442                 break;
2443
2444         case 40:        /* lhz */
2445         case 41:        /* lhzu */
2446                 op->type = MKOP(LOAD, u, 2);
2447                 op->ea = dform_ea(instr, regs);
2448                 break;
2449
2450         case 42:        /* lha */
2451         case 43:        /* lhau */
2452                 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2453                 op->ea = dform_ea(instr, regs);
2454                 break;
2455
2456         case 44:        /* sth */
2457         case 45:        /* sthu */
2458                 op->type = MKOP(STORE, u, 2);
2459                 op->ea = dform_ea(instr, regs);
2460                 break;
2461
2462         case 46:        /* lmw */
2463                 if (ra >= rd)
2464                         break;          /* invalid form, ra in range to load */
2465                 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2466                 op->ea = dform_ea(instr, regs);
2467                 break;
2468
2469         case 47:        /* stmw */
2470                 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2471                 op->ea = dform_ea(instr, regs);
2472                 break;
2473
2474 #ifdef CONFIG_PPC_FPU
2475         case 48:        /* lfs */
2476         case 49:        /* lfsu */
2477                 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2478                 op->ea = dform_ea(instr, regs);
2479                 break;
2480
2481         case 50:        /* lfd */
2482         case 51:        /* lfdu */
2483                 op->type = MKOP(LOAD_FP, u, 8);
2484                 op->ea = dform_ea(instr, regs);
2485                 break;
2486
2487         case 52:        /* stfs */
2488         case 53:        /* stfsu */
2489                 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2490                 op->ea = dform_ea(instr, regs);
2491                 break;
2492
2493         case 54:        /* stfd */
2494         case 55:        /* stfdu */
2495                 op->type = MKOP(STORE_FP, u, 8);
2496                 op->ea = dform_ea(instr, regs);
2497                 break;
2498 #endif
2499
2500 #ifdef __powerpc64__
2501         case 56:        /* lq */
2502                 if (!((rd & 1) || (rd == ra)))
2503                         op->type = MKOP(LOAD, 0, 16);
2504                 op->ea = dqform_ea(instr, regs);
2505                 break;
2506 #endif
2507
2508 #ifdef CONFIG_VSX
2509         case 57:        /* lfdp, lxsd, lxssp */
2510                 op->ea = dsform_ea(instr, regs);
2511                 switch (instr & 3) {
2512                 case 0:         /* lfdp */
2513                         if (rd & 1)
2514                                 break;          /* reg must be even */
2515                         op->type = MKOP(LOAD_FP, 0, 16);
2516                         break;
2517                 case 2:         /* lxsd */
2518                         op->reg = rd + 32;
2519                         op->type = MKOP(LOAD_VSX, 0, 8);
2520                         op->element_size = 8;
2521                         op->vsx_flags = VSX_CHECK_VEC;
2522                         break;
2523                 case 3:         /* lxssp */
2524                         op->reg = rd + 32;
2525                         op->type = MKOP(LOAD_VSX, 0, 4);
2526                         op->element_size = 8;
2527                         op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2528                         break;
2529                 }
2530                 break;
2531 #endif /* CONFIG_VSX */
2532
2533 #ifdef __powerpc64__
2534         case 58:        /* ld[u], lwa */
2535                 op->ea = dsform_ea(instr, regs);
2536                 switch (instr & 3) {
2537                 case 0:         /* ld */
2538                         op->type = MKOP(LOAD, 0, 8);
2539                         break;
2540                 case 1:         /* ldu */
2541                         op->type = MKOP(LOAD, UPDATE, 8);
2542                         break;
2543                 case 2:         /* lwa */
2544                         op->type = MKOP(LOAD, SIGNEXT, 4);
2545                         break;
2546                 }
2547                 break;
2548 #endif
2549
2550 #ifdef CONFIG_VSX
2551         case 61:        /* stfdp, lxv, stxsd, stxssp, stxv */
2552                 switch (instr & 7) {
2553                 case 0:         /* stfdp with LSB of DS field = 0 */
2554                 case 4:         /* stfdp with LSB of DS field = 1 */
2555                         op->ea = dsform_ea(instr, regs);
2556                         op->type = MKOP(STORE_FP, 0, 16);
2557                         break;
2558
2559                 case 1:         /* lxv */
2560                         op->ea = dqform_ea(instr, regs);
2561                         if (instr & 8)
2562                                 op->reg = rd + 32;
2563                         op->type = MKOP(LOAD_VSX, 0, 16);
2564                         op->element_size = 16;
2565                         op->vsx_flags = VSX_CHECK_VEC;
2566                         break;
2567
2568                 case 2:         /* stxsd with LSB of DS field = 0 */
2569                 case 6:         /* stxsd with LSB of DS field = 1 */
2570                         op->ea = dsform_ea(instr, regs);
2571                         op->reg = rd + 32;
2572                         op->type = MKOP(STORE_VSX, 0, 8);
2573                         op->element_size = 8;
2574                         op->vsx_flags = VSX_CHECK_VEC;
2575                         break;
2576
2577                 case 3:         /* stxssp with LSB of DS field = 0 */
2578                 case 7:         /* stxssp with LSB of DS field = 1 */
2579                         op->ea = dsform_ea(instr, regs);
2580                         op->reg = rd + 32;
2581                         op->type = MKOP(STORE_VSX, 0, 4);
2582                         op->element_size = 8;
2583                         op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2584                         break;
2585
2586                 case 5:         /* stxv */
2587                         op->ea = dqform_ea(instr, regs);
2588                         if (instr & 8)
2589                                 op->reg = rd + 32;
2590                         op->type = MKOP(STORE_VSX, 0, 16);
2591                         op->element_size = 16;
2592                         op->vsx_flags = VSX_CHECK_VEC;
2593                         break;
2594                 }
2595                 break;
2596 #endif /* CONFIG_VSX */
2597
2598 #ifdef __powerpc64__
2599         case 62:        /* std[u] */
2600                 op->ea = dsform_ea(instr, regs);
2601                 switch (instr & 3) {
2602                 case 0:         /* std */
2603                         op->type = MKOP(STORE, 0, 8);
2604                         break;
2605                 case 1:         /* stdu */
2606                         op->type = MKOP(STORE, UPDATE, 8);
2607                         break;
2608                 case 2:         /* stq */
2609                         if (!(rd & 1))
2610                                 op->type = MKOP(STORE, 0, 16);
2611                         break;
2612                 }
2613                 break;
2614 #endif /* __powerpc64__ */
2615
2616         }
2617
2618 #ifdef CONFIG_VSX
2619         if ((GETTYPE(op->type) == LOAD_VSX ||
2620              GETTYPE(op->type) == STORE_VSX) &&
2621             !cpu_has_feature(CPU_FTR_VSX)) {
2622                 return -1;
2623         }
2624 #endif /* CONFIG_VSX */
2625
2626         return 0;
2627
2628  logical_done:
2629         if (instr & 1)
2630                 set_cr0(regs, op);
2631  logical_done_nocc:
2632         op->reg = ra;
2633         op->type |= SETREG;
2634         return 1;
2635
2636  arith_done:
2637         if (instr & 1)
2638                 set_cr0(regs, op);
2639  compute_done:
2640         op->reg = rd;
2641         op->type |= SETREG;
2642         return 1;
2643
2644  priv:
2645         op->type = INTERRUPT | 0x700;
2646         op->val = SRR1_PROGPRIV;
2647         return 0;
2648
2649  trap:
2650         op->type = INTERRUPT | 0x700;
2651         op->val = SRR1_PROGTRAP;
2652         return 0;
2653 }
2654 EXPORT_SYMBOL_GPL(analyse_instr);
2655 NOKPROBE_SYMBOL(analyse_instr);
2656
2657 /*
2658  * For PPC32 we always use stwu with r1 to change the stack pointer.
2659  * So this emulated store may corrupt the exception frame, now we
2660  * have to provide the exception frame trampoline, which is pushed
2661  * below the kprobed function stack. So we only update gpr[1] but
2662  * don't emulate the real store operation. We will do real store
2663  * operation safely in exception return code by checking this flag.
2664  */
2665 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs)
2666 {
2667 #ifdef CONFIG_PPC32
2668         /*
2669          * Check if we will touch kernel stack overflow
2670          */
2671         if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) {
2672                 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n");
2673                 return -EINVAL;
2674         }
2675 #endif /* CONFIG_PPC32 */
2676         /*
2677          * Check if we already set since that means we'll
2678          * lose the previous value.
2679          */
2680         WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE));
2681         set_thread_flag(TIF_EMULATE_STACK_STORE);
2682         return 0;
2683 }
2684
2685 static nokprobe_inline void do_signext(unsigned long *valp, int size)
2686 {
2687         switch (size) {
2688         case 2:
2689                 *valp = (signed short) *valp;
2690                 break;
2691         case 4:
2692                 *valp = (signed int) *valp;
2693                 break;
2694         }
2695 }
2696
2697 static nokprobe_inline void do_byterev(unsigned long *valp, int size)
2698 {
2699         switch (size) {
2700         case 2:
2701                 *valp = byterev_2(*valp);
2702                 break;
2703         case 4:
2704                 *valp = byterev_4(*valp);
2705                 break;
2706 #ifdef __powerpc64__
2707         case 8:
2708                 *valp = byterev_8(*valp);
2709                 break;
2710 #endif
2711         }
2712 }
2713
2714 /*
2715  * Emulate an instruction that can be executed just by updating
2716  * fields in *regs.
2717  */
2718 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
2719 {
2720         unsigned long next_pc;
2721
2722         next_pc = truncate_if_32bit(regs->msr, regs->nip + 4);
2723         switch (GETTYPE(op->type)) {
2724         case COMPUTE:
2725                 if (op->type & SETREG)
2726                         regs->gpr[op->reg] = op->val;
2727                 if (op->type & SETCC)
2728                         regs->ccr = op->ccval;
2729                 if (op->type & SETXER)
2730                         regs->xer = op->xerval;
2731                 break;
2732
2733         case BRANCH:
2734                 if (op->type & SETLK)
2735                         regs->link = next_pc;
2736                 if (op->type & BRTAKEN)
2737                         next_pc = op->val;
2738                 if (op->type & DECCTR)
2739                         --regs->ctr;
2740                 break;
2741
2742         case BARRIER:
2743                 switch (op->type & BARRIER_MASK) {
2744                 case BARRIER_SYNC:
2745                         mb();
2746                         break;
2747                 case BARRIER_ISYNC:
2748                         isync();
2749                         break;
2750                 case BARRIER_EIEIO:
2751                         eieio();
2752                         break;
2753                 case BARRIER_LWSYNC:
2754                         asm volatile("lwsync" : : : "memory");
2755                         break;
2756                 case BARRIER_PTESYNC:
2757                         asm volatile("ptesync" : : : "memory");
2758                         break;
2759                 }
2760                 break;
2761
2762         case MFSPR:
2763                 switch (op->spr) {
2764                 case SPRN_XER:
2765                         regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
2766                         break;
2767                 case SPRN_LR:
2768                         regs->gpr[op->reg] = regs->link;
2769                         break;
2770                 case SPRN_CTR:
2771                         regs->gpr[op->reg] = regs->ctr;
2772                         break;
2773                 default:
2774                         WARN_ON_ONCE(1);
2775                 }
2776                 break;
2777
2778         case MTSPR:
2779                 switch (op->spr) {
2780                 case SPRN_XER:
2781                         regs->xer = op->val & 0xffffffffUL;
2782                         break;
2783                 case SPRN_LR:
2784                         regs->link = op->val;
2785                         break;
2786                 case SPRN_CTR:
2787                         regs->ctr = op->val;
2788                         break;
2789                 default:
2790                         WARN_ON_ONCE(1);
2791                 }
2792                 break;
2793
2794         default:
2795                 WARN_ON_ONCE(1);
2796         }
2797         regs->nip = next_pc;
2798 }
2799 NOKPROBE_SYMBOL(emulate_update_regs);
2800
2801 /*
2802  * Emulate a previously-analysed load or store instruction.
2803  * Return values are:
2804  * 0 = instruction emulated successfully
2805  * -EFAULT = address out of range or access faulted (regs->dar
2806  *           contains the faulting address)
2807  * -EACCES = misaligned access, instruction requires alignment
2808  * -EINVAL = unknown operation in *op
2809  */
2810 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
2811 {
2812         int err, size, type;
2813         int i, rd, nb;
2814         unsigned int cr;
2815         unsigned long val;
2816         unsigned long ea;
2817         bool cross_endian;
2818
2819         err = 0;
2820         size = GETSIZE(op->type);
2821         type = GETTYPE(op->type);
2822         cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
2823         ea = truncate_if_32bit(regs->msr, op->ea);
2824
2825         switch (type) {
2826         case LARX:
2827                 if (ea & (size - 1))
2828                         return -EACCES;         /* can't handle misaligned */
2829                 if (!address_ok(regs, ea, size))
2830                         return -EFAULT;
2831                 err = 0;
2832                 val = 0;
2833                 switch (size) {
2834 #ifdef __powerpc64__
2835                 case 1:
2836                         __get_user_asmx(val, ea, err, "lbarx");
2837                         break;
2838                 case 2:
2839                         __get_user_asmx(val, ea, err, "lharx");
2840                         break;
2841 #endif
2842                 case 4:
2843                         __get_user_asmx(val, ea, err, "lwarx");
2844                         break;
2845 #ifdef __powerpc64__
2846                 case 8:
2847                         __get_user_asmx(val, ea, err, "ldarx");
2848                         break;
2849                 case 16:
2850                         err = do_lqarx(ea, &regs->gpr[op->reg]);
2851                         break;
2852 #endif
2853                 default:
2854                         return -EINVAL;
2855                 }
2856                 if (err) {
2857                         regs->dar = ea;
2858                         break;
2859                 }
2860                 if (size < 16)
2861                         regs->gpr[op->reg] = val;
2862                 break;
2863
2864         case STCX:
2865                 if (ea & (size - 1))
2866                         return -EACCES;         /* can't handle misaligned */
2867                 if (!address_ok(regs, ea, size))
2868                         return -EFAULT;
2869                 err = 0;
2870                 switch (size) {
2871 #ifdef __powerpc64__
2872                 case 1:
2873                         __put_user_asmx(op->val, ea, err, "stbcx.", cr);
2874                         break;
2875                 case 2:
2876                         __put_user_asmx(op->val, ea, err, "stbcx.", cr);
2877                         break;
2878 #endif
2879                 case 4:
2880                         __put_user_asmx(op->val, ea, err, "stwcx.", cr);
2881                         break;
2882 #ifdef __powerpc64__
2883                 case 8:
2884                         __put_user_asmx(op->val, ea, err, "stdcx.", cr);
2885                         break;
2886                 case 16:
2887                         err = do_stqcx(ea, regs->gpr[op->reg],
2888                                        regs->gpr[op->reg + 1], &cr);
2889                         break;
2890 #endif
2891                 default:
2892                         return -EINVAL;
2893                 }
2894                 if (!err)
2895                         regs->ccr = (regs->ccr & 0x0fffffff) |
2896                                 (cr & 0xe0000000) |
2897                                 ((regs->xer >> 3) & 0x10000000);
2898                 else
2899                         regs->dar = ea;
2900                 break;
2901
2902         case LOAD:
2903 #ifdef __powerpc64__
2904                 if (size == 16) {
2905                         err = emulate_lq(regs, ea, op->reg, cross_endian);
2906                         break;
2907                 }
2908 #endif
2909                 err = read_mem(&regs->gpr[op->reg], ea, size, regs);
2910                 if (!err) {
2911                         if (op->type & SIGNEXT)
2912                                 do_signext(&regs->gpr[op->reg], size);
2913                         if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
2914                                 do_byterev(&regs->gpr[op->reg], size);
2915                 }
2916                 break;
2917
2918 #ifdef CONFIG_PPC_FPU
2919         case LOAD_FP:
2920                 /*
2921                  * If the instruction is in userspace, we can emulate it even
2922                  * if the VMX state is not live, because we have the state
2923                  * stored in the thread_struct.  If the instruction is in
2924                  * the kernel, we must not touch the state in the thread_struct.
2925                  */
2926                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
2927                         return 0;
2928                 err = do_fp_load(op, ea, regs, cross_endian);
2929                 break;
2930 #endif
2931 #ifdef CONFIG_ALTIVEC
2932         case LOAD_VMX:
2933                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
2934                         return 0;
2935                 err = do_vec_load(op->reg, ea, size, regs, cross_endian);
2936                 break;
2937 #endif
2938 #ifdef CONFIG_VSX
2939         case LOAD_VSX: {
2940                 unsigned long msrbit = MSR_VSX;
2941
2942                 /*
2943                  * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
2944                  * when the target of the instruction is a vector register.
2945                  */
2946                 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
2947                         msrbit = MSR_VEC;
2948                 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
2949                         return 0;
2950                 err = do_vsx_load(op, ea, regs, cross_endian);
2951                 break;
2952         }
2953 #endif
2954         case LOAD_MULTI:
2955                 if (!address_ok(regs, ea, size))
2956                         return -EFAULT;
2957                 rd = op->reg;
2958                 for (i = 0; i < size; i += 4) {
2959                         unsigned int v32 = 0;
2960
2961                         nb = size - i;
2962                         if (nb > 4)
2963                                 nb = 4;
2964                         err = copy_mem_in((u8 *) &v32, ea, nb, regs);
2965                         if (err)
2966                                 break;
2967                         if (unlikely(cross_endian))
2968                                 v32 = byterev_4(v32);
2969                         regs->gpr[rd] = v32;
2970                         ea += 4;
2971                         /* reg number wraps from 31 to 0 for lsw[ix] */
2972                         rd = (rd + 1) & 0x1f;
2973                 }
2974                 break;
2975
2976         case STORE:
2977 #ifdef __powerpc64__
2978                 if (size == 16) {
2979                         err = emulate_stq(regs, ea, op->reg, cross_endian);
2980                         break;
2981                 }
2982 #endif
2983                 if ((op->type & UPDATE) && size == sizeof(long) &&
2984                     op->reg == 1 && op->update_reg == 1 &&
2985                     !(regs->msr & MSR_PR) &&
2986                     ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
2987                         err = handle_stack_update(ea, regs);
2988                         break;
2989                 }
2990                 if (unlikely(cross_endian))
2991                         do_byterev(&op->val, size);
2992                 err = write_mem(op->val, ea, size, regs);
2993                 break;
2994
2995 #ifdef CONFIG_PPC_FPU
2996         case STORE_FP:
2997                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
2998                         return 0;
2999                 err = do_fp_store(op, ea, regs, cross_endian);
3000                 break;
3001 #endif
3002 #ifdef CONFIG_ALTIVEC
3003         case STORE_VMX:
3004                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3005                         return 0;
3006                 err = do_vec_store(op->reg, ea, size, regs, cross_endian);
3007                 break;
3008 #endif
3009 #ifdef CONFIG_VSX
3010         case STORE_VSX: {
3011                 unsigned long msrbit = MSR_VSX;
3012
3013                 /*
3014                  * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3015                  * when the target of the instruction is a vector register.
3016                  */
3017                 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3018                         msrbit = MSR_VEC;
3019                 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3020                         return 0;
3021                 err = do_vsx_store(op, ea, regs, cross_endian);
3022                 break;
3023         }
3024 #endif
3025         case STORE_MULTI:
3026                 if (!address_ok(regs, ea, size))
3027                         return -EFAULT;
3028                 rd = op->reg;
3029                 for (i = 0; i < size; i += 4) {
3030                         unsigned int v32 = regs->gpr[rd];
3031
3032                         nb = size - i;
3033                         if (nb > 4)
3034                                 nb = 4;
3035                         if (unlikely(cross_endian))
3036                                 v32 = byterev_4(v32);
3037                         err = copy_mem_out((u8 *) &v32, ea, nb, regs);
3038                         if (err)
3039                                 break;
3040                         ea += 4;
3041                         /* reg number wraps from 31 to 0 for stsw[ix] */
3042                         rd = (rd + 1) & 0x1f;
3043                 }
3044                 break;
3045
3046         default:
3047                 return -EINVAL;
3048         }
3049
3050         if (err)
3051                 return err;
3052
3053         if (op->type & UPDATE)
3054                 regs->gpr[op->update_reg] = op->ea;
3055
3056         return 0;
3057 }
3058 NOKPROBE_SYMBOL(emulate_loadstore);
3059
3060 /*
3061  * Emulate instructions that cause a transfer of control,
3062  * loads and stores, and a few other instructions.
3063  * Returns 1 if the step was emulated, 0 if not,
3064  * or -1 if the instruction is one that should not be stepped,
3065  * such as an rfid, or a mtmsrd that would clear MSR_RI.
3066  */
3067 int emulate_step(struct pt_regs *regs, unsigned int instr)
3068 {
3069         struct instruction_op op;
3070         int r, err, type;
3071         unsigned long val;
3072         unsigned long ea;
3073
3074         r = analyse_instr(&op, regs, instr);
3075         if (r < 0)
3076                 return r;
3077         if (r > 0) {
3078                 emulate_update_regs(regs, &op);
3079                 return 1;
3080         }
3081
3082         err = 0;
3083         type = GETTYPE(op.type);
3084
3085         if (OP_IS_LOAD_STORE(type)) {
3086                 err = emulate_loadstore(regs, &op);
3087                 if (err)
3088                         return 0;
3089                 goto instr_done;
3090         }
3091
3092         switch (type) {
3093         case CACHEOP:
3094                 ea = truncate_if_32bit(regs->msr, op.ea);
3095                 if (!address_ok(regs, ea, 8))
3096                         return 0;
3097                 switch (op.type & CACHEOP_MASK) {
3098                 case DCBST:
3099                         __cacheop_user_asmx(ea, err, "dcbst");
3100                         break;
3101                 case DCBF:
3102                         __cacheop_user_asmx(ea, err, "dcbf");
3103                         break;
3104                 case DCBTST:
3105                         if (op.reg == 0)
3106                                 prefetchw((void *) ea);
3107                         break;
3108                 case DCBT:
3109                         if (op.reg == 0)
3110                                 prefetch((void *) ea);
3111                         break;
3112                 case ICBI:
3113                         __cacheop_user_asmx(ea, err, "icbi");
3114                         break;
3115                 case DCBZ:
3116                         err = emulate_dcbz(ea, regs);
3117                         break;
3118                 }
3119                 if (err) {
3120                         regs->dar = ea;
3121                         return 0;
3122                 }
3123                 goto instr_done;
3124
3125         case MFMSR:
3126                 regs->gpr[op.reg] = regs->msr & MSR_MASK;
3127                 goto instr_done;
3128
3129         case MTMSR:
3130                 val = regs->gpr[op.reg];
3131                 if ((val & MSR_RI) == 0)
3132                         /* can't step mtmsr[d] that would clear MSR_RI */
3133                         return -1;
3134                 /* here op.val is the mask of bits to change */
3135                 regs->msr = (regs->msr & ~op.val) | (val & op.val);
3136                 goto instr_done;
3137
3138 #ifdef CONFIG_PPC64
3139         case SYSCALL:   /* sc */
3140                 /*
3141                  * N.B. this uses knowledge about how the syscall
3142                  * entry code works.  If that is changed, this will
3143                  * need to be changed also.
3144                  */
3145                 if (regs->gpr[0] == 0x1ebe &&
3146                     cpu_has_feature(CPU_FTR_REAL_LE)) {
3147                         regs->msr ^= MSR_LE;
3148                         goto instr_done;
3149                 }
3150                 regs->gpr[9] = regs->gpr[13];
3151                 regs->gpr[10] = MSR_KERNEL;
3152                 regs->gpr[11] = regs->nip + 4;
3153                 regs->gpr[12] = regs->msr & MSR_MASK;
3154                 regs->gpr[13] = (unsigned long) get_paca();
3155                 regs->nip = (unsigned long) &system_call_common;
3156                 regs->msr = MSR_KERNEL;
3157                 return 1;
3158
3159         case RFI:
3160                 return -1;
3161 #endif
3162         }
3163         return 0;
3164
3165  instr_done:
3166         regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4);
3167         return 1;
3168 }
3169 NOKPROBE_SYMBOL(emulate_step);