1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
4 * {mikejc|engebret}@us.ibm.com
6 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
8 * SMP scalability work:
9 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
14 * PowerPC Hashed Page Table functions
20 #define pr_fmt(fmt) "hash-mmu: " fmt
21 #include <linux/spinlock.h>
22 #include <linux/errno.h>
23 #include <linux/sched/mm.h>
24 #include <linux/proc_fs.h>
25 #include <linux/stat.h>
26 #include <linux/sysctl.h>
27 #include <linux/export.h>
28 #include <linux/ctype.h>
29 #include <linux/cache.h>
30 #include <linux/init.h>
31 #include <linux/signal.h>
32 #include <linux/memblock.h>
33 #include <linux/context_tracking.h>
34 #include <linux/libfdt.h>
35 #include <linux/pkeys.h>
36 #include <linux/hugetlb.h>
38 #include <asm/debugfs.h>
39 #include <asm/processor.h>
40 #include <asm/pgtable.h>
42 #include <asm/mmu_context.h>
44 #include <asm/types.h>
45 #include <linux/uaccess.h>
46 #include <asm/machdep.h>
51 #include <asm/cacheflush.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
54 #include <asm/copro.h>
56 #include <asm/code-patching.h>
57 #include <asm/fadump.h>
58 #include <asm/firmware.h>
60 #include <asm/trace.h>
62 #include <asm/pte-walk.h>
63 #include <asm/asm-prototypes.h>
65 #include <mm/mmu_decl.h>
68 #define DBG(fmt...) udbg_printf(fmt)
74 #define DBG_LOW(fmt...) udbg_printf(fmt)
76 #define DBG_LOW(fmt...)
84 * Note: pte --> Linux PTE
85 * HPTE --> PowerPC Hashed Page Table Entry
88 * htab_initialize is called with the MMU off (of course), but
89 * the kernel has been copied down to zero so it can directly
90 * reference global data. At this point it is very difficult
91 * to print debug info.
95 static unsigned long _SDR1;
96 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
97 EXPORT_SYMBOL_GPL(mmu_psize_defs);
99 u8 hpte_page_sizes[1 << LP_BITS];
100 EXPORT_SYMBOL_GPL(hpte_page_sizes);
102 struct hash_pte *htab_address;
103 unsigned long htab_size_bytes;
104 unsigned long htab_hash_mask;
105 EXPORT_SYMBOL_GPL(htab_hash_mask);
106 int mmu_linear_psize = MMU_PAGE_4K;
107 EXPORT_SYMBOL_GPL(mmu_linear_psize);
108 int mmu_virtual_psize = MMU_PAGE_4K;
109 int mmu_vmalloc_psize = MMU_PAGE_4K;
110 #ifdef CONFIG_SPARSEMEM_VMEMMAP
111 int mmu_vmemmap_psize = MMU_PAGE_4K;
113 int mmu_io_psize = MMU_PAGE_4K;
114 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
115 EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
116 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
117 u16 mmu_slb_size = 64;
118 EXPORT_SYMBOL_GPL(mmu_slb_size);
119 #ifdef CONFIG_PPC_64K_PAGES
120 int mmu_ci_restrictions;
122 #ifdef CONFIG_DEBUG_PAGEALLOC
123 static u8 *linear_map_hash_slots;
124 static unsigned long linear_map_hash_count;
125 static DEFINE_SPINLOCK(linear_map_hash_lock);
126 #endif /* CONFIG_DEBUG_PAGEALLOC */
127 struct mmu_hash_ops mmu_hash_ops;
128 EXPORT_SYMBOL(mmu_hash_ops);
131 * These are definitions of page sizes arrays to be used when none
132 * is provided by the firmware.
136 * Fallback (4k pages only)
138 static struct mmu_psize_def mmu_psize_defaults[] = {
142 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
149 * POWER4, GPUL, POWER5
151 * Support for 16Mb large pages
153 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
157 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
164 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
165 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
172 * 'R' and 'C' update notes:
173 * - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
174 * create writeable HPTEs without C set, because the hcall H_PROTECT
175 * that we use in that case will not update C
176 * - The above is however not a problem, because we also don't do that
177 * fancy "no flush" variant of eviction and we use H_REMOVE which will
178 * do the right thing and thus we don't have the race I described earlier
180 * - Under bare metal, we do have the race, so we need R and C set
181 * - We make sure R is always set and never lost
182 * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
184 unsigned long htab_convert_pte_flags(unsigned long pteflags)
186 unsigned long rflags = 0;
188 /* _PAGE_EXEC -> NOEXEC */
189 if ((pteflags & _PAGE_EXEC) == 0)
193 * Linux uses slb key 0 for kernel and 1 for user.
194 * kernel RW areas are mapped with PPP=0b000
195 * User area is mapped with PPP=0b010 for read/write
196 * or PPP=0b011 for read-only (including writeable but clean pages).
198 if (pteflags & _PAGE_PRIVILEGED) {
200 * Kernel read only mapped with ppp bits 0b110
202 if (!(pteflags & _PAGE_WRITE)) {
203 if (mmu_has_feature(MMU_FTR_KERNEL_RO))
204 rflags |= (HPTE_R_PP0 | 0x2);
209 if (pteflags & _PAGE_RWX)
211 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
215 * We can't allow hardware to update hpte bits. Hence always
216 * set 'R' bit and set 'C' if it is a write fault
220 if (pteflags & _PAGE_DIRTY)
226 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
228 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
229 rflags |= (HPTE_R_I | HPTE_R_G);
230 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
231 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
234 * Add memory coherence if cache inhibited is not set
238 rflags |= pte_to_hpte_pkey_bits(pteflags);
242 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
243 unsigned long pstart, unsigned long prot,
244 int psize, int ssize)
246 unsigned long vaddr, paddr;
247 unsigned int step, shift;
250 shift = mmu_psize_defs[psize].shift;
253 prot = htab_convert_pte_flags(prot);
255 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
256 vstart, vend, pstart, prot, psize, ssize);
258 for (vaddr = vstart, paddr = pstart; vaddr < vend;
259 vaddr += step, paddr += step) {
260 unsigned long hash, hpteg;
261 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
262 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
263 unsigned long tprot = prot;
266 * If we hit a bad address return error.
270 /* Make kernel text executable */
271 if (overlaps_kernel_text(vaddr, vaddr + step))
274 /* Make kvm guest trampolines executable */
275 if (overlaps_kvm_tmp(vaddr, vaddr + step))
279 * If relocatable, check if it overlaps interrupt vectors that
280 * are copied down to real 0. For relocatable kernel
281 * (e.g. kdump case) we copy interrupt vectors down to real
282 * address 0. Mark that region as executable. This is
283 * because on p8 system with relocation on exception feature
284 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
285 * in order to execute the interrupt handlers in virtual
286 * mode the vector region need to be marked as executable.
288 if ((PHYSICAL_START > MEMORY_START) &&
289 overlaps_interrupt_vector_text(vaddr, vaddr + step))
292 hash = hpt_hash(vpn, shift, ssize);
293 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
295 BUG_ON(!mmu_hash_ops.hpte_insert);
296 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
297 HPTE_V_BOLTED, psize, psize,
303 #ifdef CONFIG_DEBUG_PAGEALLOC
304 if (debug_pagealloc_enabled() &&
305 (paddr >> PAGE_SHIFT) < linear_map_hash_count)
306 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
307 #endif /* CONFIG_DEBUG_PAGEALLOC */
309 return ret < 0 ? ret : 0;
312 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
313 int psize, int ssize)
316 unsigned int step, shift;
320 shift = mmu_psize_defs[psize].shift;
323 if (!mmu_hash_ops.hpte_removebolted)
326 for (vaddr = vstart; vaddr < vend; vaddr += step) {
327 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
339 static bool disable_1tb_segments = false;
341 static int __init parse_disable_1tb_segments(char *p)
343 disable_1tb_segments = true;
346 early_param("disable_1tb_segments", parse_disable_1tb_segments);
348 static int __init htab_dt_scan_seg_sizes(unsigned long node,
349 const char *uname, int depth,
352 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
356 /* We are scanning "cpu" nodes only */
357 if (type == NULL || strcmp(type, "cpu") != 0)
360 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
363 for (; size >= 4; size -= 4, ++prop) {
364 if (be32_to_cpu(prop[0]) == 40) {
365 DBG("1T segment support detected\n");
367 if (disable_1tb_segments) {
368 DBG("1T segments disabled by command line\n");
372 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
376 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
380 static int __init get_idx_from_shift(unsigned int shift)
404 static int __init htab_dt_scan_page_sizes(unsigned long node,
405 const char *uname, int depth,
408 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
412 /* We are scanning "cpu" nodes only */
413 if (type == NULL || strcmp(type, "cpu") != 0)
416 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
420 pr_info("Page sizes from device-tree:\n");
422 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
424 unsigned int base_shift = be32_to_cpu(prop[0]);
425 unsigned int slbenc = be32_to_cpu(prop[1]);
426 unsigned int lpnum = be32_to_cpu(prop[2]);
427 struct mmu_psize_def *def;
430 size -= 3; prop += 3;
431 base_idx = get_idx_from_shift(base_shift);
433 /* skip the pte encoding also */
434 prop += lpnum * 2; size -= lpnum * 2;
437 def = &mmu_psize_defs[base_idx];
438 if (base_idx == MMU_PAGE_16M)
439 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
441 def->shift = base_shift;
442 if (base_shift <= 23)
445 def->avpnm = (1 << (base_shift - 23)) - 1;
448 * We don't know for sure what's up with tlbiel, so
449 * for now we only set it for 4K and 64K pages
451 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
456 while (size > 0 && lpnum) {
457 unsigned int shift = be32_to_cpu(prop[0]);
458 int penc = be32_to_cpu(prop[1]);
460 prop += 2; size -= 2;
463 idx = get_idx_from_shift(shift);
468 pr_err("Invalid penc for base_shift=%d "
469 "shift=%d\n", base_shift, shift);
471 def->penc[idx] = penc;
472 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
473 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
474 base_shift, shift, def->sllp,
475 def->avpnm, def->tlbiel, def->penc[idx]);
482 #ifdef CONFIG_HUGETLB_PAGE
484 * Scan for 16G memory blocks that have been set aside for huge pages
485 * and reserve those blocks for 16G huge pages.
487 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
488 const char *uname, int depth,
490 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
491 const __be64 *addr_prop;
492 const __be32 *page_count_prop;
493 unsigned int expected_pages;
494 long unsigned int phys_addr;
495 long unsigned int block_size;
497 /* We are scanning "memory" nodes only */
498 if (type == NULL || strcmp(type, "memory") != 0)
502 * This property is the log base 2 of the number of virtual pages that
503 * will represent this memory block.
505 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
506 if (page_count_prop == NULL)
508 expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
509 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
510 if (addr_prop == NULL)
512 phys_addr = be64_to_cpu(addr_prop[0]);
513 block_size = be64_to_cpu(addr_prop[1]);
514 if (block_size != (16 * GB))
516 printk(KERN_INFO "Huge page(16GB) memory: "
517 "addr = 0x%lX size = 0x%lX pages = %d\n",
518 phys_addr, block_size, expected_pages);
519 if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) {
520 memblock_reserve(phys_addr, block_size * expected_pages);
521 pseries_add_gpage(phys_addr, block_size, expected_pages);
525 #endif /* CONFIG_HUGETLB_PAGE */
527 static void mmu_psize_set_default_penc(void)
530 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
531 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
532 mmu_psize_defs[bpsize].penc[apsize] = -1;
535 #ifdef CONFIG_PPC_64K_PAGES
537 static bool might_have_hea(void)
540 * The HEA ethernet adapter requires awareness of the
541 * GX bus. Without that awareness we can easily assume
542 * we will never see an HEA ethernet device.
544 #ifdef CONFIG_IBMEBUS
545 return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
546 firmware_has_feature(FW_FEATURE_SPLPAR);
552 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
554 static void __init htab_scan_page_sizes(void)
558 /* se the invalid penc to -1 */
559 mmu_psize_set_default_penc();
561 /* Default to 4K pages only */
562 memcpy(mmu_psize_defs, mmu_psize_defaults,
563 sizeof(mmu_psize_defaults));
566 * Try to find the available page sizes in the device-tree
568 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
569 if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
571 * Nothing in the device-tree, but the CPU supports 16M pages,
572 * so let's fallback on a known size list for 16M capable CPUs.
574 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
575 sizeof(mmu_psize_defaults_gp));
578 #ifdef CONFIG_HUGETLB_PAGE
579 if (!hugetlb_disabled) {
580 /* Reserve 16G huge page memory sections for huge pages */
581 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
583 #endif /* CONFIG_HUGETLB_PAGE */
587 * Fill in the hpte_page_sizes[] array.
588 * We go through the mmu_psize_defs[] array looking for all the
589 * supported base/actual page size combinations. Each combination
590 * has a unique pagesize encoding (penc) value in the low bits of
591 * the LP field of the HPTE. For actual page sizes less than 1MB,
592 * some of the upper LP bits are used for RPN bits, meaning that
593 * we need to fill in several entries in hpte_page_sizes[].
595 * In diagrammatic form, with r = RPN bits and z = page size bits:
596 * PTE LP actual page size
603 * The zzzz bits are implementation-specific but are chosen so that
604 * no encoding for a larger page size uses the same value in its
605 * low-order N bits as the encoding for the 2^(12+N) byte page size
608 static void init_hpte_page_sizes(void)
611 long int shift, penc;
613 for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) {
614 if (!mmu_psize_defs[bp].shift)
615 continue; /* not a supported page size */
616 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) {
617 penc = mmu_psize_defs[bp].penc[ap];
618 if (penc == -1 || !mmu_psize_defs[ap].shift)
620 shift = mmu_psize_defs[ap].shift - LP_SHIFT;
622 continue; /* should never happen */
624 * For page sizes less than 1MB, this loop
625 * replicates the entry for all possible values
628 while (penc < (1 << LP_BITS)) {
629 hpte_page_sizes[penc] = (ap << 4) | bp;
636 static void __init htab_init_page_sizes(void)
638 init_hpte_page_sizes();
640 if (!debug_pagealloc_enabled()) {
642 * Pick a size for the linear mapping. Currently, we only
643 * support 16M, 1M and 4K which is the default
645 if (mmu_psize_defs[MMU_PAGE_16M].shift)
646 mmu_linear_psize = MMU_PAGE_16M;
647 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
648 mmu_linear_psize = MMU_PAGE_1M;
651 #ifdef CONFIG_PPC_64K_PAGES
653 * Pick a size for the ordinary pages. Default is 4K, we support
654 * 64K for user mappings and vmalloc if supported by the processor.
655 * We only use 64k for ioremap if the processor
656 * (and firmware) support cache-inhibited large pages.
657 * If not, we use 4k and set mmu_ci_restrictions so that
658 * hash_page knows to switch processes that use cache-inhibited
659 * mappings to 4k pages.
661 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
662 mmu_virtual_psize = MMU_PAGE_64K;
663 mmu_vmalloc_psize = MMU_PAGE_64K;
664 if (mmu_linear_psize == MMU_PAGE_4K)
665 mmu_linear_psize = MMU_PAGE_64K;
666 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
668 * When running on pSeries using 64k pages for ioremap
669 * would stop us accessing the HEA ethernet. So if we
670 * have the chance of ever seeing one, stay at 4k.
672 if (!might_have_hea())
673 mmu_io_psize = MMU_PAGE_64K;
675 mmu_ci_restrictions = 1;
677 #endif /* CONFIG_PPC_64K_PAGES */
679 #ifdef CONFIG_SPARSEMEM_VMEMMAP
681 * We try to use 16M pages for vmemmap if that is supported
682 * and we have at least 1G of RAM at boot
684 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
685 memblock_phys_mem_size() >= 0x40000000)
686 mmu_vmemmap_psize = MMU_PAGE_16M;
688 mmu_vmemmap_psize = mmu_virtual_psize;
689 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
691 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
692 "virtual = %d, io = %d"
693 #ifdef CONFIG_SPARSEMEM_VMEMMAP
697 mmu_psize_defs[mmu_linear_psize].shift,
698 mmu_psize_defs[mmu_virtual_psize].shift,
699 mmu_psize_defs[mmu_io_psize].shift
700 #ifdef CONFIG_SPARSEMEM_VMEMMAP
701 ,mmu_psize_defs[mmu_vmemmap_psize].shift
706 static int __init htab_dt_scan_pftsize(unsigned long node,
707 const char *uname, int depth,
710 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
713 /* We are scanning "cpu" nodes only */
714 if (type == NULL || strcmp(type, "cpu") != 0)
717 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
719 /* pft_size[0] is the NUMA CEC cookie */
720 ppc64_pft_size = be32_to_cpu(prop[1]);
726 unsigned htab_shift_for_mem_size(unsigned long mem_size)
728 unsigned memshift = __ilog2(mem_size);
729 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
732 /* round mem_size up to next power of 2 */
733 if ((1UL << memshift) < mem_size)
736 /* aim for 2 pages / pteg */
737 pteg_shift = memshift - (pshift + 1);
740 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
741 * size permitted by the architecture.
743 return max(pteg_shift + 7, 18U);
746 static unsigned long __init htab_get_table_size(void)
749 * If hash size isn't already provided by the platform, we try to
750 * retrieve it from the device-tree. If it's not there neither, we
751 * calculate it now based on the total RAM size
753 if (ppc64_pft_size == 0)
754 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
756 return 1UL << ppc64_pft_size;
758 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
761 #ifdef CONFIG_MEMORY_HOTPLUG
762 int resize_hpt_for_hotplug(unsigned long new_mem_size)
764 unsigned target_hpt_shift;
766 if (!mmu_hash_ops.resize_hpt)
769 target_hpt_shift = htab_shift_for_mem_size(new_mem_size);
772 * To avoid lots of HPT resizes if memory size is fluctuating
773 * across a boundary, we deliberately have some hysterisis
774 * here: we immediately increase the HPT size if the target
775 * shift exceeds the current shift, but we won't attempt to
776 * reduce unless the target shift is at least 2 below the
779 if (target_hpt_shift > ppc64_pft_size ||
780 target_hpt_shift < ppc64_pft_size - 1)
781 return mmu_hash_ops.resize_hpt(target_hpt_shift);
786 int hash__create_section_mapping(unsigned long start, unsigned long end, int nid)
790 if (end >= H_VMALLOC_START) {
791 pr_warn("Outside the supported range\n");
795 rc = htab_bolt_mapping(start, end, __pa(start),
796 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
800 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
802 BUG_ON(rc2 && (rc2 != -ENOENT));
807 int hash__remove_section_mapping(unsigned long start, unsigned long end)
809 int rc = htab_remove_mapping(start, end, mmu_linear_psize,
814 #endif /* CONFIG_MEMORY_HOTPLUG */
816 static void __init hash_init_partition_table(phys_addr_t hash_table,
817 unsigned long htab_size)
819 mmu_partition_table_init();
822 * PS field (VRMA page size) is not used for LPID 0, hence set to 0.
823 * For now, UPRT is 0 and we have no segment table.
825 htab_size = __ilog2(htab_size) - 18;
826 mmu_partition_table_set_entry(0, hash_table | htab_size, 0);
827 pr_info("Partition table %p\n", partition_tb);
830 static void __init htab_initialize(void)
833 unsigned long pteg_count;
835 unsigned long base = 0, size = 0;
836 struct memblock_region *reg;
838 DBG(" -> htab_initialize()\n");
840 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
841 mmu_kernel_ssize = MMU_SEGSIZE_1T;
842 mmu_highuser_ssize = MMU_SEGSIZE_1T;
843 printk(KERN_INFO "Using 1TB segments\n");
847 * Calculate the required size of the htab. We want the number of
848 * PTEGs to equal one half the number of real pages.
850 htab_size_bytes = htab_get_table_size();
851 pteg_count = htab_size_bytes >> 7;
853 htab_hash_mask = pteg_count - 1;
855 if (firmware_has_feature(FW_FEATURE_LPAR) ||
856 firmware_has_feature(FW_FEATURE_PS3_LV1)) {
857 /* Using a hypervisor which owns the htab */
861 * On POWER9, we need to do a H_REGISTER_PROC_TBL hcall
862 * to inform the hypervisor that we wish to use the HPT.
864 if (cpu_has_feature(CPU_FTR_ARCH_300))
865 register_process_table(0, 0, 0);
866 #ifdef CONFIG_FA_DUMP
868 * If firmware assisted dump is active firmware preserves
869 * the contents of htab along with entire partition memory.
870 * Clear the htab if firmware assisted dump is active so
871 * that we dont end up using old mappings.
873 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
874 mmu_hash_ops.hpte_clear_all();
877 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
879 #ifdef CONFIG_PPC_CELL
881 * Cell may require the hash table down low when using the
882 * Axon IOMMU in order to fit the dynamic region over it, see
883 * comments in cell/iommu.c
885 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
887 pr_info("Hash table forced below 2G for Axon IOMMU\n");
889 #endif /* CONFIG_PPC_CELL */
891 table = memblock_phys_alloc_range(htab_size_bytes,
895 panic("ERROR: Failed to allocate %pa bytes below %pa\n",
896 &htab_size_bytes, &limit);
898 DBG("Hash table allocated at %lx, size: %lx\n", table,
901 htab_address = __va(table);
903 /* htab absolute addr + encoded htabsize */
904 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
906 /* Initialize the HPT with no entries */
907 memset((void *)table, 0, htab_size_bytes);
909 if (!cpu_has_feature(CPU_FTR_ARCH_300))
911 mtspr(SPRN_SDR1, _SDR1);
913 hash_init_partition_table(table, htab_size_bytes);
916 prot = pgprot_val(PAGE_KERNEL);
918 #ifdef CONFIG_DEBUG_PAGEALLOC
919 if (debug_pagealloc_enabled()) {
920 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
921 linear_map_hash_slots = memblock_alloc_try_nid(
922 linear_map_hash_count, 1, MEMBLOCK_LOW_LIMIT,
923 ppc64_rma_size, NUMA_NO_NODE);
924 if (!linear_map_hash_slots)
925 panic("%s: Failed to allocate %lu bytes max_addr=%pa\n",
926 __func__, linear_map_hash_count, &ppc64_rma_size);
928 #endif /* CONFIG_DEBUG_PAGEALLOC */
930 /* create bolted the linear mapping in the hash table */
931 for_each_memblock(memory, reg) {
932 base = (unsigned long)__va(reg->base);
935 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
938 if ((base + size) >= H_VMALLOC_START) {
939 pr_warn("Outside the supported range\n");
943 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
944 prot, mmu_linear_psize, mmu_kernel_ssize));
946 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
949 * If we have a memory_limit and we've allocated TCEs then we need to
950 * explicitly map the TCE area at the top of RAM. We also cope with the
951 * case that the TCEs start below memory_limit.
952 * tce_alloc_start/end are 16MB aligned so the mapping should work
953 * for either 4K or 16MB pages.
955 if (tce_alloc_start) {
956 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
957 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
959 if (base + size >= tce_alloc_start)
960 tce_alloc_start = base + size + 1;
962 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
963 __pa(tce_alloc_start), prot,
964 mmu_linear_psize, mmu_kernel_ssize));
968 DBG(" <- htab_initialize()\n");
973 void __init hash__early_init_devtree(void)
975 /* Initialize segment sizes */
976 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
978 /* Initialize page sizes */
979 htab_scan_page_sizes();
982 static struct hash_mm_context init_hash_mm_context;
983 void __init hash__early_init_mmu(void)
985 #ifndef CONFIG_PPC_64K_PAGES
987 * We have code in __hash_page_4K() and elsewhere, which assumes it can
989 * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX);
991 * Where the slot number is between 0-15, and values of 8-15 indicate
992 * the secondary bucket. For that code to work H_PAGE_F_SECOND and
993 * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and
994 * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here
995 * with a BUILD_BUG_ON().
997 BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3)));
998 #endif /* CONFIG_PPC_64K_PAGES */
1000 htab_init_page_sizes();
1003 * initialize page table size
1005 __pte_frag_nr = H_PTE_FRAG_NR;
1006 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
1007 __pmd_frag_nr = H_PMD_FRAG_NR;
1008 __pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT;
1010 __pte_index_size = H_PTE_INDEX_SIZE;
1011 __pmd_index_size = H_PMD_INDEX_SIZE;
1012 __pud_index_size = H_PUD_INDEX_SIZE;
1013 __pgd_index_size = H_PGD_INDEX_SIZE;
1014 __pud_cache_index = H_PUD_CACHE_INDEX;
1015 __pte_table_size = H_PTE_TABLE_SIZE;
1016 __pmd_table_size = H_PMD_TABLE_SIZE;
1017 __pud_table_size = H_PUD_TABLE_SIZE;
1018 __pgd_table_size = H_PGD_TABLE_SIZE;
1020 * 4k use hugepd format, so for hash set then to
1023 __pmd_val_bits = HASH_PMD_VAL_BITS;
1024 __pud_val_bits = HASH_PUD_VAL_BITS;
1025 __pgd_val_bits = HASH_PGD_VAL_BITS;
1027 __kernel_virt_start = H_KERN_VIRT_START;
1028 __vmalloc_start = H_VMALLOC_START;
1029 __vmalloc_end = H_VMALLOC_END;
1030 __kernel_io_start = H_KERN_IO_START;
1031 __kernel_io_end = H_KERN_IO_END;
1032 vmemmap = (struct page *)H_VMEMMAP_START;
1033 ioremap_bot = IOREMAP_BASE;
1036 pci_io_base = ISA_IO_BASE;
1039 /* Select appropriate backend */
1040 if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1041 ps3_early_mm_init();
1042 else if (firmware_has_feature(FW_FEATURE_LPAR))
1043 hpte_init_pseries();
1044 else if (IS_ENABLED(CONFIG_PPC_NATIVE))
1047 if (!mmu_hash_ops.hpte_insert)
1048 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
1051 * Initialize the MMU Hash table and create the linear mapping
1052 * of memory. Has to be done before SLB initialization as this is
1053 * currently where the page size encoding is obtained.
1057 init_mm.context.hash_context = &init_hash_mm_context;
1058 mm_ctx_set_slb_addr_limit(&init_mm.context, SLB_ADDR_LIMIT_DEFAULT);
1060 pr_info("Initializing hash mmu with SLB\n");
1061 /* Initialize SLB management */
1064 if (cpu_has_feature(CPU_FTR_ARCH_206)
1065 && cpu_has_feature(CPU_FTR_HVMODE))
1070 void hash__early_init_mmu_secondary(void)
1072 /* Initialize hash table for that CPU */
1073 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1075 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1076 mtspr(SPRN_SDR1, _SDR1);
1079 __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
1081 /* Initialize SLB */
1084 if (cpu_has_feature(CPU_FTR_ARCH_206)
1085 && cpu_has_feature(CPU_FTR_HVMODE))
1088 #endif /* CONFIG_SMP */
1091 * Called by asm hashtable.S for doing lazy icache flush
1093 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
1097 if (!pfn_valid(pte_pfn(pte)))
1100 page = pte_page(pte);
1103 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
1104 if (trap == 0x400) {
1105 flush_dcache_icache_page(page);
1106 set_bit(PG_arch_1, &page->flags);
1113 #ifdef CONFIG_PPC_MM_SLICES
1114 static unsigned int get_paca_psize(unsigned long addr)
1116 unsigned char *psizes;
1117 unsigned long index, mask_index;
1119 if (addr < SLICE_LOW_TOP) {
1120 psizes = get_paca()->mm_ctx_low_slices_psize;
1121 index = GET_LOW_SLICE_INDEX(addr);
1123 psizes = get_paca()->mm_ctx_high_slices_psize;
1124 index = GET_HIGH_SLICE_INDEX(addr);
1126 mask_index = index & 0x1;
1127 return (psizes[index >> 1] >> (mask_index * 4)) & 0xF;
1131 unsigned int get_paca_psize(unsigned long addr)
1133 return get_paca()->mm_ctx_user_psize;
1138 * Demote a segment to using 4k pages.
1139 * For now this makes the whole process use 4k pages.
1141 #ifdef CONFIG_PPC_64K_PAGES
1142 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1144 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1146 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1147 copro_flush_all_slbs(mm);
1148 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1150 copy_mm_to_paca(mm);
1151 slb_flush_and_restore_bolted();
1154 #endif /* CONFIG_PPC_64K_PAGES */
1156 #ifdef CONFIG_PPC_SUBPAGE_PROT
1158 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1159 * Userspace sets the subpage permissions using the subpage_prot system call.
1161 * Result is 0: full permissions, _PAGE_RW: read-only,
1162 * _PAGE_RWX: no access.
1164 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1166 struct subpage_prot_table *spt = mm_ctx_subpage_prot(&mm->context);
1173 if (ea >= spt->maxaddr)
1175 if (ea < 0x100000000UL) {
1176 /* addresses below 4GB use spt->low_prot */
1177 sbpm = spt->low_prot;
1179 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1183 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1186 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1188 /* extract 2-bit bitfield for this 4k subpage */
1189 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1192 * 0 -> full premission
1195 * We return the flag that need to be cleared.
1197 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1201 #else /* CONFIG_PPC_SUBPAGE_PROT */
1202 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1208 void hash_failure_debug(unsigned long ea, unsigned long access,
1209 unsigned long vsid, unsigned long trap,
1210 int ssize, int psize, int lpsize, unsigned long pte)
1212 if (!printk_ratelimit())
1214 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1215 ea, access, current->comm);
1216 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1217 trap, vsid, ssize, psize, lpsize, pte);
1220 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1221 int psize, bool user_region)
1224 if (psize != get_paca_psize(ea)) {
1225 copy_mm_to_paca(mm);
1226 slb_flush_and_restore_bolted();
1228 } else if (get_paca()->vmalloc_sllp !=
1229 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1230 get_paca()->vmalloc_sllp =
1231 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1232 slb_vmalloc_update();
1239 * 1 - normal page fault
1240 * -1 - critical hash insertion error
1241 * -2 - access not permitted by subpage protection mechanism
1243 int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1244 unsigned long access, unsigned long trap,
1245 unsigned long flags)
1248 enum ctx_state prev_state = exception_enter();
1253 int rc, user_region = 0;
1256 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1258 trace_hash_fault(ea, access, trap);
1260 /* Get region & vsid */
1261 switch (get_region_id(ea)) {
1262 case USER_REGION_ID:
1265 DBG_LOW(" user region with no mm !\n");
1269 psize = get_slice_psize(mm, ea);
1270 ssize = user_segment_size(ea);
1271 vsid = get_user_vsid(&mm->context, ea, ssize);
1273 case VMALLOC_REGION_ID:
1274 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1275 psize = mmu_vmalloc_psize;
1276 ssize = mmu_kernel_ssize;
1280 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1281 psize = mmu_io_psize;
1282 ssize = mmu_kernel_ssize;
1287 * Send the problem up to do_page_fault()
1292 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1296 DBG_LOW("Bad address!\n");
1302 if (pgdir == NULL) {
1307 /* Check CPU locality */
1308 if (user_region && mm_is_thread_local(mm))
1309 flags |= HPTE_LOCAL_UPDATE;
1311 #ifndef CONFIG_PPC_64K_PAGES
1313 * If we use 4K pages and our psize is not 4K, then we might
1314 * be hitting a special driver mapping, and need to align the
1315 * address before we fetch the PTE.
1317 * It could also be a hugepage mapping, in which case this is
1318 * not necessary, but it's not harmful, either.
1320 if (psize != MMU_PAGE_4K)
1321 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1322 #endif /* CONFIG_PPC_64K_PAGES */
1324 /* Get PTE and page size from page tables */
1325 ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift);
1326 if (ptep == NULL || !pte_present(*ptep)) {
1327 DBG_LOW(" no PTE !\n");
1332 /* Add _PAGE_PRESENT to the required access perm */
1333 access |= _PAGE_PRESENT;
1336 * Pre-check access permissions (will be re-checked atomically
1337 * in __hash_page_XX but this pre-check is a fast path
1339 if (!check_pte_access(access, pte_val(*ptep))) {
1340 DBG_LOW(" no access !\n");
1347 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1348 trap, flags, ssize, psize);
1349 #ifdef CONFIG_HUGETLB_PAGE
1351 rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1352 flags, ssize, hugeshift, psize);
1356 * if we have hugeshift, and is not transhuge with
1357 * hugetlb disabled, something is really wrong.
1363 if (current->mm == mm)
1364 check_paca_psize(ea, mm, psize, user_region);
1369 #ifndef CONFIG_PPC_64K_PAGES
1370 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1372 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1373 pte_val(*(ptep + PTRS_PER_PTE)));
1375 /* Do actual hashing */
1376 #ifdef CONFIG_PPC_64K_PAGES
1377 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1378 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1379 demote_segment_4k(mm, ea);
1380 psize = MMU_PAGE_4K;
1384 * If this PTE is non-cacheable and we have restrictions on
1385 * using non cacheable large pages, then we switch to 4k
1387 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1389 demote_segment_4k(mm, ea);
1390 psize = MMU_PAGE_4K;
1391 } else if (ea < VMALLOC_END) {
1393 * some driver did a non-cacheable mapping
1394 * in vmalloc space, so switch vmalloc
1397 printk(KERN_ALERT "Reducing vmalloc segment "
1398 "to 4kB pages because of "
1399 "non-cacheable mapping\n");
1400 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1401 copro_flush_all_slbs(mm);
1405 #endif /* CONFIG_PPC_64K_PAGES */
1407 if (current->mm == mm)
1408 check_paca_psize(ea, mm, psize, user_region);
1410 #ifdef CONFIG_PPC_64K_PAGES
1411 if (psize == MMU_PAGE_64K)
1412 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1415 #endif /* CONFIG_PPC_64K_PAGES */
1417 int spp = subpage_protection(mm, ea);
1421 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1426 * Dump some info in case of hash insertion failure, they should
1427 * never happen so it is really useful to know if/when they do
1430 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1431 psize, pte_val(*ptep));
1432 #ifndef CONFIG_PPC_64K_PAGES
1433 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1435 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1436 pte_val(*(ptep + PTRS_PER_PTE)));
1438 DBG_LOW(" -> rc=%d\n", rc);
1441 exception_exit(prev_state);
1444 EXPORT_SYMBOL_GPL(hash_page_mm);
1446 int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1447 unsigned long dsisr)
1449 unsigned long flags = 0;
1450 struct mm_struct *mm = current->mm;
1452 if ((get_region_id(ea) == VMALLOC_REGION_ID) ||
1453 (get_region_id(ea) == IO_REGION_ID))
1456 if (dsisr & DSISR_NOHPTE)
1457 flags |= HPTE_NOHPTE_UPDATE;
1459 return hash_page_mm(mm, ea, access, trap, flags);
1461 EXPORT_SYMBOL_GPL(hash_page);
1463 int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap,
1464 unsigned long dsisr)
1466 unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1467 unsigned long flags = 0;
1468 struct mm_struct *mm = current->mm;
1469 unsigned int region_id = get_region_id(ea);
1471 if ((region_id == VMALLOC_REGION_ID) || (region_id == IO_REGION_ID))
1474 if (dsisr & DSISR_NOHPTE)
1475 flags |= HPTE_NOHPTE_UPDATE;
1477 if (dsisr & DSISR_ISSTORE)
1478 access |= _PAGE_WRITE;
1480 * We set _PAGE_PRIVILEGED only when
1481 * kernel mode access kernel space.
1483 * _PAGE_PRIVILEGED is NOT set
1484 * 1) when kernel mode access user space
1485 * 2) user space access kernel space.
1487 access |= _PAGE_PRIVILEGED;
1488 if ((msr & MSR_PR) || (region_id == USER_REGION_ID))
1489 access &= ~_PAGE_PRIVILEGED;
1492 access |= _PAGE_EXEC;
1494 return hash_page_mm(mm, ea, access, trap, flags);
1497 #ifdef CONFIG_PPC_MM_SLICES
1498 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1500 int psize = get_slice_psize(mm, ea);
1502 /* We only prefault standard pages for now */
1503 if (unlikely(psize != mm_ctx_user_psize(&mm->context)))
1507 * Don't prefault if subpage protection is enabled for the EA.
1509 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1515 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1521 void hash_preload(struct mm_struct *mm, unsigned long ea,
1522 bool is_exec, unsigned long trap)
1528 unsigned long flags;
1529 int rc, ssize, update_flags = 0;
1530 unsigned long access = _PAGE_PRESENT | _PAGE_READ | (is_exec ? _PAGE_EXEC : 0);
1532 BUG_ON(get_region_id(ea) != USER_REGION_ID);
1534 if (!should_hash_preload(mm, ea))
1537 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1538 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1540 /* Get Linux PTE if available */
1546 ssize = user_segment_size(ea);
1547 vsid = get_user_vsid(&mm->context, ea, ssize);
1551 * Hash doesn't like irqs. Walking linux page table with irq disabled
1552 * saves us from holding multiple locks.
1554 local_irq_save(flags);
1557 * THP pages use update_mmu_cache_pmd. We don't do
1558 * hash preload there. Hence can ignore THP here
1560 ptep = find_current_mm_pte(pgdir, ea, NULL, &hugepage_shift);
1564 WARN_ON(hugepage_shift);
1565 #ifdef CONFIG_PPC_64K_PAGES
1566 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1567 * a 64K kernel), then we don't preload, hash_page() will take
1568 * care of it once we actually try to access the page.
1569 * That way we don't have to duplicate all of the logic for segment
1570 * page size demotion here
1572 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1574 #endif /* CONFIG_PPC_64K_PAGES */
1576 /* Is that local to this CPU ? */
1577 if (mm_is_thread_local(mm))
1578 update_flags |= HPTE_LOCAL_UPDATE;
1581 #ifdef CONFIG_PPC_64K_PAGES
1582 if (mm_ctx_user_psize(&mm->context) == MMU_PAGE_64K)
1583 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1584 update_flags, ssize);
1586 #endif /* CONFIG_PPC_64K_PAGES */
1587 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1588 ssize, subpage_protection(mm, ea));
1590 /* Dump some info in case of hash insertion failure, they should
1591 * never happen so it is really useful to know if/when they do
1594 hash_failure_debug(ea, access, vsid, trap, ssize,
1595 mm_ctx_user_psize(&mm->context),
1596 mm_ctx_user_psize(&mm->context),
1599 local_irq_restore(flags);
1602 #ifdef CONFIG_PPC_MEM_KEYS
1604 * Return the protection key associated with the given address and the
1607 u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address)
1611 unsigned long flags;
1613 if (!mm || !mm->pgd)
1616 local_irq_save(flags);
1617 ptep = find_linux_pte(mm->pgd, address, NULL, NULL);
1619 pkey = pte_to_pkey_bits(pte_val(READ_ONCE(*ptep)));
1620 local_irq_restore(flags);
1624 #endif /* CONFIG_PPC_MEM_KEYS */
1626 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1627 static inline void tm_flush_hash_page(int local)
1630 * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a
1631 * page back to a block device w/PIO could pick up transactional data
1632 * (bad!) so we force an abort here. Before the sync the page will be
1633 * made read-only, which will flush_hash_page. BIG ISSUE here: if the
1634 * kernel uses a page from userspace without unmapping it first, it may
1635 * see the speculated version.
1637 if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
1638 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1640 tm_abort(TM_CAUSE_TLBI);
1644 static inline void tm_flush_hash_page(int local)
1650 * Return the global hash slot, corresponding to the given PTE, which contains
1653 unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,
1654 int ssize, real_pte_t rpte, unsigned int subpg_index)
1656 unsigned long hash, gslot, hidx;
1658 hash = hpt_hash(vpn, shift, ssize);
1659 hidx = __rpte_to_hidx(rpte, subpg_index);
1660 if (hidx & _PTEIDX_SECONDARY)
1662 gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1663 gslot += hidx & _PTEIDX_GROUP_IX;
1668 * WARNING: This is called from hash_low_64.S, if you change this prototype,
1669 * do not forget to update the assembly call site !
1671 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1672 unsigned long flags)
1674 unsigned long index, shift, gslot;
1675 int local = flags & HPTE_LOCAL_UPDATE;
1677 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1678 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1679 gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index);
1680 DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot);
1682 * We use same base page size and actual psize, because we don't
1683 * use these functions for hugepage
1685 mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize,
1687 } pte_iterate_hashed_end();
1689 tm_flush_hash_page(local);
1692 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1693 void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1694 pmd_t *pmdp, unsigned int psize, int ssize,
1695 unsigned long flags)
1697 int i, max_hpte_count, valid;
1698 unsigned long s_addr;
1699 unsigned char *hpte_slot_array;
1700 unsigned long hidx, shift, vpn, hash, slot;
1701 int local = flags & HPTE_LOCAL_UPDATE;
1703 s_addr = addr & HPAGE_PMD_MASK;
1704 hpte_slot_array = get_hpte_slot_array(pmdp);
1706 * IF we try to do a HUGE PTE update after a withdraw is done.
1707 * we will find the below NULL. This happens when we do
1708 * split_huge_page_pmd
1710 if (!hpte_slot_array)
1713 if (mmu_hash_ops.hugepage_invalidate) {
1714 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1715 psize, ssize, local);
1719 * No bluk hpte removal support, invalidate each entry
1721 shift = mmu_psize_defs[psize].shift;
1722 max_hpte_count = HPAGE_PMD_SIZE >> shift;
1723 for (i = 0; i < max_hpte_count; i++) {
1725 * 8 bits per each hpte entries
1726 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1728 valid = hpte_valid(hpte_slot_array, i);
1731 hidx = hpte_hash_index(hpte_slot_array, i);
1734 addr = s_addr + (i * (1ul << shift));
1735 vpn = hpt_vpn(addr, vsid, ssize);
1736 hash = hpt_hash(vpn, shift, ssize);
1737 if (hidx & _PTEIDX_SECONDARY)
1740 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1741 slot += hidx & _PTEIDX_GROUP_IX;
1742 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1743 MMU_PAGE_16M, ssize, local);
1746 tm_flush_hash_page(local);
1748 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1750 void flush_hash_range(unsigned long number, int local)
1752 if (mmu_hash_ops.flush_hash_range)
1753 mmu_hash_ops.flush_hash_range(number, local);
1756 struct ppc64_tlb_batch *batch =
1757 this_cpu_ptr(&ppc64_tlb_batch);
1759 for (i = 0; i < number; i++)
1760 flush_hash_page(batch->vpn[i], batch->pte[i],
1761 batch->psize, batch->ssize, local);
1766 * low_hash_fault is called when we the low level hash code failed
1767 * to instert a PTE due to an hypervisor error
1769 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1771 enum ctx_state prev_state = exception_enter();
1773 if (user_mode(regs)) {
1774 #ifdef CONFIG_PPC_SUBPAGE_PROT
1776 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1779 _exception(SIGBUS, regs, BUS_ADRERR, address);
1781 bad_page_fault(regs, address, SIGBUS);
1783 exception_exit(prev_state);
1786 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1787 unsigned long pa, unsigned long rflags,
1788 unsigned long vflags, int psize, int ssize)
1790 unsigned long hpte_group;
1794 hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1796 /* Insert into the hash table, primary slot */
1797 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1798 psize, psize, ssize);
1800 /* Primary is full, try the secondary */
1801 if (unlikely(slot == -1)) {
1802 hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP;
1803 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1804 vflags | HPTE_V_SECONDARY,
1805 psize, psize, ssize);
1808 hpte_group = (hash & htab_hash_mask) *
1811 mmu_hash_ops.hpte_remove(hpte_group);
1819 #ifdef CONFIG_DEBUG_PAGEALLOC
1820 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1823 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1824 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1825 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1828 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1830 /* Don't create HPTE entries for bad address */
1834 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1836 mmu_linear_psize, mmu_kernel_ssize);
1839 spin_lock(&linear_map_hash_lock);
1840 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1841 linear_map_hash_slots[lmi] = ret | 0x80;
1842 spin_unlock(&linear_map_hash_lock);
1845 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1847 unsigned long hash, hidx, slot;
1848 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1849 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1851 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1852 spin_lock(&linear_map_hash_lock);
1853 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1854 hidx = linear_map_hash_slots[lmi] & 0x7f;
1855 linear_map_hash_slots[lmi] = 0;
1856 spin_unlock(&linear_map_hash_lock);
1857 if (hidx & _PTEIDX_SECONDARY)
1859 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1860 slot += hidx & _PTEIDX_GROUP_IX;
1861 mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1863 mmu_kernel_ssize, 0);
1866 void __kernel_map_pages(struct page *page, int numpages, int enable)
1868 unsigned long flags, vaddr, lmi;
1871 local_irq_save(flags);
1872 for (i = 0; i < numpages; i++, page++) {
1873 vaddr = (unsigned long)page_address(page);
1874 lmi = __pa(vaddr) >> PAGE_SHIFT;
1875 if (lmi >= linear_map_hash_count)
1878 kernel_map_linear_page(vaddr, lmi);
1880 kernel_unmap_linear_page(vaddr, lmi);
1882 local_irq_restore(flags);
1884 #endif /* CONFIG_DEBUG_PAGEALLOC */
1886 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1887 phys_addr_t first_memblock_size)
1890 * We don't currently support the first MEMBLOCK not mapping 0
1891 * physical on those processors
1893 BUG_ON(first_memblock_base != 0);
1896 * On virtualized systems the first entry is our RMA region aka VRMA,
1897 * non-virtualized 64-bit hash MMU systems don't have a limitation
1898 * on real mode access.
1900 * For guests on platforms before POWER9, we clamp the it limit to 1G
1901 * to avoid some funky things such as RTAS bugs etc...
1903 * On POWER9 we limit to 1TB in case the host erroneously told us that
1904 * the RMA was >1TB. Effective address bits 0:23 are treated as zero
1905 * (meaning the access is aliased to zero i.e. addr = addr % 1TB)
1906 * for virtual real mode addressing and so it doesn't make sense to
1907 * have an area larger than 1TB as it can't be addressed.
1909 if (!early_cpu_has_feature(CPU_FTR_HVMODE)) {
1910 ppc64_rma_size = first_memblock_size;
1911 if (!early_cpu_has_feature(CPU_FTR_ARCH_300))
1912 ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000);
1914 ppc64_rma_size = min_t(u64, ppc64_rma_size,
1915 1UL << SID_SHIFT_1T);
1917 /* Finally limit subsequent allocations */
1918 memblock_set_current_limit(ppc64_rma_size);
1920 ppc64_rma_size = ULONG_MAX;
1924 #ifdef CONFIG_DEBUG_FS
1926 static int hpt_order_get(void *data, u64 *val)
1928 *val = ppc64_pft_size;
1932 static int hpt_order_set(void *data, u64 val)
1934 if (!mmu_hash_ops.resize_hpt)
1937 return mmu_hash_ops.resize_hpt(val);
1940 DEFINE_DEBUGFS_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n");
1942 static int __init hash64_debugfs(void)
1944 if (!debugfs_create_file_unsafe("hpt_order", 0600, powerpc_debugfs_root,
1945 NULL, &fops_hpt_order)) {
1946 pr_err("lpar: unable to create hpt_order debugsfs file\n");
1951 machine_device_initcall(pseries, hash64_debugfs);
1952 #endif /* CONFIG_DEBUG_FS */
1954 void __init print_system_hash_info(void)
1956 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size);
1959 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask);
1960 pr_info("kernel vmalloc start = 0x%lx\n", KERN_VIRT_START);
1961 pr_info("kernel IO start = 0x%lx\n", KERN_IO_START);
1962 pr_info("kernel vmemmap start = 0x%lx\n", (unsigned long)vmemmap);