1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains low-level functions for performing various
4 * types of TLB invalidations on various processors with no hash
7 * This file implements the following functions for all no-hash
8 * processors. Some aren't implemented for some variants. Some
9 * are inline in tlbflush.h
16 * Code mostly moved over from misc_32.S
18 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
20 * Partially rewritten by Cort Dougan (cort@cs.nmt.edu)
21 * Paul Mackerras, Kumar Gala and Benjamin Herrenschmidt.
26 #include <asm/cputable.h>
28 #include <asm/ppc_asm.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/processor.h>
32 #include <asm/asm-compat.h>
33 #include <asm/feature-fixups.h>
35 #if defined(CONFIG_40x)
38 * 40x implementation needs only tlbil_va
41 /* We run the search with interrupts disabled because we have to change
42 * the PID and I don't want to preempt when that happens.
53 /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is
54 * clear. Since 25 is the V bit in the TLB_TAG, loading this value
55 * will invalidate the TLB entry. */
60 #elif defined(CONFIG_PPC_8xx)
63 * Nothing to do for 8xx, everything is inline
66 #elif defined(CONFIG_44x) /* Includes 47x */
69 * 440 implementation uses tlbsx/we for tlbil_va and a full sweep
70 * of the TLB for everything else.
77 * We write 16 bits of STID since 47x supports that much, we
78 * will never be passed out of bounds values on 440 (hopefully)
82 /* We have to run the search with interrupts disabled, otherwise
83 * an interrupt which causes a TLB miss can clobber the MMUCR
84 * between the mtspr and the tlbsx.
86 * Critical and Machine Check interrupts take care of saving
87 * and restoring MMUCR, so only normal interrupts have to be
97 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
98 /* On 440 There are only 64 TLB entries, so r3 < 64, which means bit
99 * 22, is clear. Since 22 is the V bit in the TLB_PAGEID, loading this
100 * value will invalidate the TLB entry.
102 tlbwe r6,r6,PPC44x_TLB_PAGEID
107 #ifdef CONFIG_PPC_47x
108 oris r7,r6,0x8000 /* specify way explicitly */
109 clrrwi r4,r3,12 /* get an EPN for the hashing with V = 0 */
110 ori r4,r4,PPC47x_TLBE_SIZE
111 tlbwe r4,r7,0 /* write it */
115 #else /* CONFIG_PPC_47x */
117 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0;
118 #endif /* !CONFIG_PPC_47x */
122 BEGIN_MMU_FTR_SECTION
124 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
128 /* Load high watermark */
129 lis r4,tlb_44x_hwater@ha
130 lwz r5,tlb_44x_hwater@l(r4)
132 1: tlbwe r3,r3,PPC44x_TLB_PAGEID
140 #ifdef CONFIG_PPC_47x
141 /* 476 variant. There's not simple way to do this, hopefully we'll
142 * try to limit the amount of such full invalidates
144 mfmsr r11 /* Interrupts off */
146 li r3,-1 /* Current set */
147 lis r10,tlb_47x_boltmap@h
148 ori r10,r10,tlb_47x_boltmap@l
149 lis r7,0x8000 /* Specify way explicitly */
151 b 9f /* For each set */
153 1: li r9,4 /* Number of ways */
154 li r4,0 /* Current way */
155 li r6,0 /* Default entry value 0 */
156 andi. r0,r8,1 /* Check if way 0 is bolted */
157 mtctr r9 /* Load way counter */
158 bne- 3f /* Bolted, skip loading it */
160 2: /* For each way */
161 or r5,r3,r4 /* Make way|index for tlbre */
162 rlwimi r5,r5,16,8,15 /* Copy index into position */
163 tlbre r6,r5,0 /* Read entry */
164 3: addis r4,r4,0x2000 /* Next way */
165 andi. r0,r6,PPC47x_TLB0_VALID /* Valid entry ? */
166 beq 4f /* Nope, skip it */
167 rlwimi r7,r5,0,1,2 /* Insert way number */
168 rlwinm r6,r6,0,21,19 /* Clear V */
169 tlbwe r6,r7,0 /* Write it */
170 4: bdnz 2b /* Loop for each way */
171 srwi r8,r8,1 /* Next boltmap bit */
172 9: cmpwi cr1,r3,255 /* Last set done ? */
173 addi r3,r3,1 /* Next set */
174 beq cr1,1f /* End of loop */
175 andi. r0,r3,0x1f /* Need to load a new boltmap word ? */
176 bne 1b /* No, loop */
177 lwz r8,0(r10) /* Load boltmap entry */
178 addi r10,r10,4 /* Next word */
180 1: isync /* Sync shadows */
182 #else /* CONFIG_PPC_47x */
184 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0;
185 #endif /* !CONFIG_PPC_47x */
188 #ifdef CONFIG_PPC_47x
191 * _tlbivax_bcast is only on 47x. We don't bother doing a runtime
192 * check though, it will blow up soon enough if we mistakenly try
193 * to use it on a 440.
195 _GLOBAL(_tlbivax_bcast)
208 END_FTR_SECTION_IFSET(CPU_FTR_476_DD2)
213 * DD2 HW could hang if in instruction fetch happens before msync completes.
214 * Touch enough instruction cache lines to ensure cache hits
220 PPC_ICBT(0,R6,R7) /* touch next cache line */
222 PPC_ICBT(0,R6,R7) /* touch next cache line */
224 PPC_ICBT(0,R6,R7) /* touch next cache line */
237 #endif /* CONFIG_PPC_47x */
239 #elif defined(CONFIG_FSL_BOOKE)
241 * FSL BookE implementations.
243 * Since feature sections are using _SECTION_ELSE we need
244 * to have the larger code path before the _SECTION_ELSE
248 * Flush MMU TLB on the local processor
251 BEGIN_MMU_FTR_SECTION
252 li r3,(MMUCSR0_TLBFI)@l
253 mtspr SPRN_MMUCSR0, r3
255 mfspr r3,SPRN_MMUCSR0
256 andi. r3,r3,MMUCSR0_TLBFI@l
260 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
266 BEGIN_MMU_FTR_SECTION
270 mfspr r4,SPRN_MAS6 /* save MAS6 */
273 mtspr SPRN_MAS6,r4 /* restore MAS6 */
276 li r3,(MMUCSR0_TLBFI)@l
277 mtspr SPRN_MMUCSR0, r3
279 mfspr r3,SPRN_MMUCSR0
280 andi. r3,r3,MMUCSR0_TLBFI@l
282 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBILX)
288 * Flush MMU TLB for a particular address, but only on the local processor
295 ori r4,r4,(MAS6_ISIZE(BOOK3E_PAGESZ_4K))@l
296 mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
297 BEGIN_MMU_FTR_SECTION
299 mfspr r4,SPRN_MAS1 /* check valid */
300 andis. r3,r4,MAS1_VALID@h
307 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
312 #elif defined(CONFIG_PPC_BOOK3E)
314 * New Book3E (>= 2.06) implementation
316 * Note: We may be able to get away without the interrupt masking stuff
317 * if we save/restore MAS6 on exceptions that might modify it
320 slwi r4,r3,MAS6_SPID_SHIFT
330 _GLOBAL(_tlbil_pid_noind)
331 slwi r4,r3,MAS6_SPID_SHIFT
352 slwi r4,r4,MAS6_SPID_SHIFT
353 rlwimi r4,r5,MAS6_ISIZE_SHIFT,MAS6_ISIZE_MASK
355 rlwimi r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
356 1: mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
363 _GLOBAL(_tlbivax_bcast)
367 slwi r4,r4,MAS6_SPID_SHIFT
368 rlwimi r4,r5,MAS6_ISIZE_SHIFT,MAS6_ISIZE_MASK
370 rlwimi r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
371 1: mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
380 #ifdef CONFIG_BDI_SWITCH
381 /* Context switch the PTE pointer for the Abatron BDI2000.
382 * The PGDIR is the second parameter.
384 lis r5, abatron_pteptrs@h
385 ori r5, r5, abatron_pteptrs@l
389 isync /* Force context change */
392 #error Unsupported processor type !
395 #if defined(CONFIG_PPC_FSL_BOOK3E)
397 * extern void loadcam_entry(unsigned int index)
399 * Load TLBCAM[index] entry in to the L2 CAM MMU
400 * Must preserve r7, r8, r9, and r10
402 _GLOBAL(loadcam_entry)
404 LOAD_REG_ADDR_PIC(r4, TLBCAM)
406 mulli r5,r3,TLBCAM_SIZE
408 lwz r4,TLBCAM_MAS0(r3)
410 lwz r4,TLBCAM_MAS1(r3)
412 PPC_LL r4,TLBCAM_MAS2(r3)
414 lwz r4,TLBCAM_MAS3(r3)
416 BEGIN_MMU_FTR_SECTION
417 lwz r4,TLBCAM_MAS7(r3)
419 END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
426 * Load multiple TLB entries at once, using an alternate-space
427 * trampoline so that we don't have to care about whether the same
428 * TLB entry maps us before and after.
430 * r3 = first entry to write
431 * r4 = number of entries to write
432 * r5 = temporary tlb entry
434 _GLOBAL(loadcam_multi)
438 * Set up temporary TLB entry that is the same as what we're
439 * running from, but in AS=1.
448 rlwimi r6,r5,MAS0_ESEL_SHIFT,MAS0_ESEL_MASK
457 ori r6,r6,MSR_IS|MSR_DS
469 /* Return to AS=0 and clear the temporary entry */
471 rlwinm. r6,r6,0,~(MSR_IS|MSR_DS)
477 rlwinm r6,r7,MAS0_ESEL_SHIFT,MAS0_ESEL_MASK
478 oris r6,r6,MAS0_TLBSEL(1)@h