2 * Performance event support - powerpc architecture code
4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/sched.h>
13 #include <linux/perf_event.h>
14 #include <linux/percpu.h>
15 #include <linux/hardirq.h>
16 #include <linux/uaccess.h>
19 #include <asm/machdep.h>
20 #include <asm/firmware.h>
21 #include <asm/ptrace.h>
22 #include <asm/code-patching.h>
24 #define BHRB_MAX_ENTRIES 32
25 #define BHRB_TARGET 0x0000000000000002
26 #define BHRB_PREDICTION 0x0000000000000001
27 #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL
29 struct cpu_hw_events {
36 struct perf_event *event[MAX_HWEVENTS];
37 u64 events[MAX_HWEVENTS];
38 unsigned int flags[MAX_HWEVENTS];
40 * The order of the MMCR array is:
41 * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2
42 * - 32-bit, MMCR0, MMCR1, MMCR2
44 unsigned long mmcr[4];
45 struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS];
46 u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS];
47 u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
48 unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
49 unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
51 unsigned int txn_flags;
55 u64 bhrb_filter; /* BHRB HW branch filter */
56 unsigned int bhrb_users;
58 struct perf_branch_stack bhrb_stack;
59 struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES];
63 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
65 static struct power_pmu *ppmu;
68 * Normally, to ignore kernel events we set the FCS (freeze counters
69 * in supervisor mode) bit in MMCR0, but if the kernel runs with the
70 * hypervisor bit set in the MSR, or if we are running on a processor
71 * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
72 * then we need to use the FCHV bit to ignore kernel events.
74 static unsigned int freeze_events_kernel = MMCR0_FCS;
77 * 32-bit doesn't have MMCRA but does have an MMCR2,
78 * and a few other names are different.
83 #define MMCR0_PMCjCE MMCR0_PMCnCE
89 #define MMCR0_PMCC_U6 0
91 #define SPRN_MMCRA SPRN_MMCR2
92 #define MMCRA_SAMPLE_ENABLE 0
94 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
98 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { }
99 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
103 static inline void perf_read_regs(struct pt_regs *regs)
107 static inline int perf_intr_is_nmi(struct pt_regs *regs)
112 static inline int siar_valid(struct pt_regs *regs)
117 static bool is_ebb_event(struct perf_event *event) { return false; }
118 static int ebb_event_check(struct perf_event *event) { return 0; }
119 static void ebb_event_add(struct perf_event *event) { }
120 static void ebb_switch_out(unsigned long mmcr0) { }
121 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
123 return cpuhw->mmcr[0];
126 static inline void power_pmu_bhrb_enable(struct perf_event *event) {}
127 static inline void power_pmu_bhrb_disable(struct perf_event *event) {}
128 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {}
129 static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {}
130 static void pmao_restore_workaround(bool ebb) { }
131 static bool use_ic(u64 event)
135 #endif /* CONFIG_PPC32 */
137 static bool regs_use_siar(struct pt_regs *regs)
140 * When we take a performance monitor exception the regs are setup
141 * using perf_read_regs() which overloads some fields, in particular
142 * regs->result to tell us whether to use SIAR.
144 * However if the regs are from another exception, eg. a syscall, then
145 * they have not been setup using perf_read_regs() and so regs->result
146 * is something random.
148 return ((TRAP(regs) == 0xf00) && regs->result);
152 * Things that are specific to 64-bit implementations.
156 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
158 unsigned long mmcra = regs->dsisr;
160 if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) {
161 unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
163 return 4 * (slot - 1);
170 * The user wants a data address recorded.
171 * If we're not doing instruction sampling, give them the SDAR
172 * (sampled data address). If we are doing instruction sampling, then
173 * only give them the SDAR if it corresponds to the instruction
174 * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the
175 * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER.
177 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp)
179 unsigned long mmcra = regs->dsisr;
182 if (ppmu->flags & PPMU_HAS_SIER)
183 sdar_valid = regs->dar & SIER_SDAR_VALID;
185 unsigned long sdsync;
187 if (ppmu->flags & PPMU_SIAR_VALID)
188 sdsync = POWER7P_MMCRA_SDAR_VALID;
189 else if (ppmu->flags & PPMU_ALT_SIPR)
190 sdsync = POWER6_MMCRA_SDSYNC;
191 else if (ppmu->flags & PPMU_NO_SIAR)
192 sdsync = MMCRA_SAMPLE_ENABLE;
194 sdsync = MMCRA_SDSYNC;
196 sdar_valid = mmcra & sdsync;
199 if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid)
200 *addrp = mfspr(SPRN_SDAR);
202 if (perf_paranoid_kernel() && !capable(CAP_SYS_ADMIN) &&
203 is_kernel_addr(mfspr(SPRN_SDAR)))
207 static bool regs_sihv(struct pt_regs *regs)
209 unsigned long sihv = MMCRA_SIHV;
211 if (ppmu->flags & PPMU_HAS_SIER)
212 return !!(regs->dar & SIER_SIHV);
214 if (ppmu->flags & PPMU_ALT_SIPR)
215 sihv = POWER6_MMCRA_SIHV;
217 return !!(regs->dsisr & sihv);
220 static bool regs_sipr(struct pt_regs *regs)
222 unsigned long sipr = MMCRA_SIPR;
224 if (ppmu->flags & PPMU_HAS_SIER)
225 return !!(regs->dar & SIER_SIPR);
227 if (ppmu->flags & PPMU_ALT_SIPR)
228 sipr = POWER6_MMCRA_SIPR;
230 return !!(regs->dsisr & sipr);
233 static inline u32 perf_flags_from_msr(struct pt_regs *regs)
235 if (regs->msr & MSR_PR)
236 return PERF_RECORD_MISC_USER;
237 if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV)
238 return PERF_RECORD_MISC_HYPERVISOR;
239 return PERF_RECORD_MISC_KERNEL;
242 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
244 bool use_siar = regs_use_siar(regs);
247 return perf_flags_from_msr(regs);
250 * If we don't have flags in MMCRA, rather than using
251 * the MSR, we intuit the flags from the address in
252 * SIAR which should give slightly more reliable
255 if (ppmu->flags & PPMU_NO_SIPR) {
256 unsigned long siar = mfspr(SPRN_SIAR);
257 if (is_kernel_addr(siar))
258 return PERF_RECORD_MISC_KERNEL;
259 return PERF_RECORD_MISC_USER;
262 /* PR has priority over HV, so order below is important */
264 return PERF_RECORD_MISC_USER;
266 if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV))
267 return PERF_RECORD_MISC_HYPERVISOR;
269 return PERF_RECORD_MISC_KERNEL;
273 * Overload regs->dsisr to store MMCRA so we only need to read it once
275 * Overload regs->dar to store SIER if we have it.
276 * Overload regs->result to specify whether we should use the MSR (result
277 * is zero) or the SIAR (result is non zero).
279 static inline void perf_read_regs(struct pt_regs *regs)
281 unsigned long mmcra = mfspr(SPRN_MMCRA);
282 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
287 if (ppmu->flags & PPMU_HAS_SIER)
288 regs->dar = mfspr(SPRN_SIER);
291 * If this isn't a PMU exception (eg a software event) the SIAR is
292 * not valid. Use pt_regs.
294 * If it is a marked event use the SIAR.
296 * If the PMU doesn't update the SIAR for non marked events use
299 * If the PMU has HV/PR flags then check to see if they
300 * place the exception in userspace. If so, use pt_regs. In
301 * continuous sampling mode the SIAR and the PMU exception are
302 * not synchronised, so they may be many instructions apart.
303 * This can result in confusing backtraces. We still want
304 * hypervisor samples as well as samples in the kernel with
305 * interrupts off hence the userspace check.
307 if (TRAP(regs) != 0xf00)
309 else if ((ppmu->flags & PPMU_NO_SIAR))
313 else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING))
315 else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs))
320 regs->result = use_siar;
324 * If interrupts were soft-disabled when a PMU interrupt occurs, treat
327 static inline int perf_intr_is_nmi(struct pt_regs *regs)
329 return (regs->softe & IRQS_DISABLED);
333 * On processors like P7+ that have the SIAR-Valid bit, marked instructions
334 * must be sampled only if the SIAR-valid bit is set.
336 * For unmarked instructions and for processors that don't have the SIAR-Valid
337 * bit, assume that SIAR is valid.
339 static inline int siar_valid(struct pt_regs *regs)
341 unsigned long mmcra = regs->dsisr;
342 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
345 if (ppmu->flags & PPMU_HAS_SIER)
346 return regs->dar & SIER_SIAR_VALID;
348 if (ppmu->flags & PPMU_SIAR_VALID)
349 return mmcra & POWER7P_MMCRA_SIAR_VALID;
356 /* Reset all possible BHRB entries */
357 static void power_pmu_bhrb_reset(void)
359 asm volatile(PPC_CLRBHRB);
362 static void power_pmu_bhrb_enable(struct perf_event *event)
364 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
369 /* Clear BHRB if we changed task context to avoid data leaks */
370 if (event->ctx->task && cpuhw->bhrb_context != event->ctx) {
371 power_pmu_bhrb_reset();
372 cpuhw->bhrb_context = event->ctx;
375 perf_sched_cb_inc(event->ctx->pmu);
378 static void power_pmu_bhrb_disable(struct perf_event *event)
380 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
385 WARN_ON_ONCE(!cpuhw->bhrb_users);
387 perf_sched_cb_dec(event->ctx->pmu);
389 if (!cpuhw->disabled && !cpuhw->bhrb_users) {
390 /* BHRB cannot be turned off when other
391 * events are active on the PMU.
394 /* avoid stale pointer */
395 cpuhw->bhrb_context = NULL;
399 /* Called from ctxsw to prevent one process's branch entries to
400 * mingle with the other process's entries during context switch.
402 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
408 power_pmu_bhrb_reset();
410 /* Calculate the to address for a branch */
411 static __u64 power_pmu_bhrb_to(u64 addr)
417 if (is_kernel_addr(addr)) {
418 if (probe_kernel_read(&instr, (void *)addr, sizeof(instr)))
421 return branch_target(&instr);
424 /* Userspace: need copy instruction here then translate it */
426 ret = __get_user_inatomic(instr, (unsigned int __user *)addr);
433 target = branch_target(&instr);
434 if ((!target) || (instr & BRANCH_ABSOLUTE))
437 /* Translate relative branch target from kernel to user address */
438 return target - (unsigned long)&instr + addr;
441 /* Processing BHRB entries */
442 static void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw)
446 int r_index, u_index, pred;
450 while (r_index < ppmu->bhrb_nr) {
451 /* Assembly read function */
452 val = read_bhrb(r_index++);
454 /* Terminal marker: End of valid BHRB entries */
457 addr = val & BHRB_EA;
458 pred = val & BHRB_PREDICTION;
465 * BHRB rolling buffer could very much contain the kernel
466 * addresses at this point. Check the privileges before
467 * exporting it to userspace (avoid exposure of regions
468 * where we could have speculative execution)
470 if (perf_paranoid_kernel() && !capable(CAP_SYS_ADMIN) &&
471 is_kernel_addr(addr))
474 /* Branches are read most recent first (ie. mfbhrb 0 is
475 * the most recent branch).
476 * There are two types of valid entries:
477 * 1) a target entry which is the to address of a
478 * computed goto like a blr,bctr,btar. The next
479 * entry read from the bhrb will be branch
480 * corresponding to this target (ie. the actual
481 * blr/bctr/btar instruction).
482 * 2) a from address which is an actual branch. If a
483 * target entry proceeds this, then this is the
484 * matching branch for that target. If this is not
485 * following a target entry, then this is a branch
486 * where the target is given as an immediate field
487 * in the instruction (ie. an i or b form branch).
488 * In this case we need to read the instruction from
489 * memory to determine the target/to address.
492 if (val & BHRB_TARGET) {
493 /* Target branches use two entries
494 * (ie. computed gotos/XL form)
496 cpuhw->bhrb_entries[u_index].to = addr;
497 cpuhw->bhrb_entries[u_index].mispred = pred;
498 cpuhw->bhrb_entries[u_index].predicted = ~pred;
500 /* Get from address in next entry */
501 val = read_bhrb(r_index++);
502 addr = val & BHRB_EA;
503 if (val & BHRB_TARGET) {
504 /* Shouldn't have two targets in a
505 row.. Reset index and try again */
509 cpuhw->bhrb_entries[u_index].from = addr;
511 /* Branches to immediate field
513 cpuhw->bhrb_entries[u_index].from = addr;
514 cpuhw->bhrb_entries[u_index].to =
515 power_pmu_bhrb_to(addr);
516 cpuhw->bhrb_entries[u_index].mispred = pred;
517 cpuhw->bhrb_entries[u_index].predicted = ~pred;
523 cpuhw->bhrb_stack.nr = u_index;
527 static bool is_ebb_event(struct perf_event *event)
530 * This could be a per-PMU callback, but we'd rather avoid the cost. We
531 * check that the PMU supports EBB, meaning those that don't can still
532 * use bit 63 of the event code for something else if they wish.
534 return (ppmu->flags & PPMU_ARCH_207S) &&
535 ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1);
538 static int ebb_event_check(struct perf_event *event)
540 struct perf_event *leader = event->group_leader;
542 /* Event and group leader must agree on EBB */
543 if (is_ebb_event(leader) != is_ebb_event(event))
546 if (is_ebb_event(event)) {
547 if (!(event->attach_state & PERF_ATTACH_TASK))
550 if (!leader->attr.pinned || !leader->attr.exclusive)
553 if (event->attr.freq ||
554 event->attr.inherit ||
555 event->attr.sample_type ||
556 event->attr.sample_period ||
557 event->attr.enable_on_exec)
564 static void ebb_event_add(struct perf_event *event)
566 if (!is_ebb_event(event) || current->thread.used_ebb)
570 * IFF this is the first time we've added an EBB event, set
571 * PMXE in the user MMCR0 so we can detect when it's cleared by
572 * userspace. We need this so that we can context switch while
573 * userspace is in the EBB handler (where PMXE is 0).
575 current->thread.used_ebb = 1;
576 current->thread.mmcr0 |= MMCR0_PMXE;
579 static void ebb_switch_out(unsigned long mmcr0)
581 if (!(mmcr0 & MMCR0_EBE))
584 current->thread.siar = mfspr(SPRN_SIAR);
585 current->thread.sier = mfspr(SPRN_SIER);
586 current->thread.sdar = mfspr(SPRN_SDAR);
587 current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK;
588 current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK;
591 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
593 unsigned long mmcr0 = cpuhw->mmcr[0];
598 /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */
599 mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6;
602 * Add any bits from the user MMCR0, FC or PMAO. This is compatible
603 * with pmao_restore_workaround() because we may add PMAO but we never
606 mmcr0 |= current->thread.mmcr0;
609 * Be careful not to set PMXE if userspace had it cleared. This is also
610 * compatible with pmao_restore_workaround() because it has already
611 * cleared PMXE and we leave PMAO alone.
613 if (!(current->thread.mmcr0 & MMCR0_PMXE))
614 mmcr0 &= ~MMCR0_PMXE;
616 mtspr(SPRN_SIAR, current->thread.siar);
617 mtspr(SPRN_SIER, current->thread.sier);
618 mtspr(SPRN_SDAR, current->thread.sdar);
621 * Merge the kernel & user values of MMCR2. The semantics we implement
622 * are that the user MMCR2 can set bits, ie. cause counters to freeze,
623 * but not clear bits. If a task wants to be able to clear bits, ie.
624 * unfreeze counters, it should not set exclude_xxx in its events and
625 * instead manage the MMCR2 entirely by itself.
627 mtspr(SPRN_MMCR2, cpuhw->mmcr[3] | current->thread.mmcr2);
632 static void pmao_restore_workaround(bool ebb)
636 if (!cpu_has_feature(CPU_FTR_PMAO_BUG))
640 * On POWER8E there is a hardware defect which affects the PMU context
641 * switch logic, ie. power_pmu_disable/enable().
643 * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0
644 * by the hardware. Sometime later the actual PMU exception is
647 * If we context switch, or simply disable/enable, the PMU prior to the
648 * exception arriving, the exception will be lost when we clear PMAO.
650 * When we reenable the PMU, we will write the saved MMCR0 with PMAO
651 * set, and this _should_ generate an exception. However because of the
652 * defect no exception is generated when we write PMAO, and we get
653 * stuck with no counters counting but no exception delivered.
655 * The workaround is to detect this case and tweak the hardware to
656 * create another pending PMU exception.
658 * We do that by setting up PMC6 (cycles) for an imminent overflow and
659 * enabling the PMU. That causes a new exception to be generated in the
660 * chip, but we don't take it yet because we have interrupts hard
661 * disabled. We then write back the PMU state as we want it to be seen
662 * by the exception handler. When we reenable interrupts the exception
663 * handler will be called and see the correct state.
665 * The logic is the same for EBB, except that the exception is gated by
666 * us having interrupts hard disabled as well as the fact that we are
667 * not in userspace. The exception is finally delivered when we return
671 /* Only if PMAO is set and PMAO_SYNC is clear */
672 if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO)
675 /* If we're doing EBB, only if BESCR[GE] is set */
676 if (ebb && !(current->thread.bescr & BESCR_GE))
680 * We are already soft-disabled in power_pmu_enable(). We need to hard
681 * disable to actually prevent the PMU exception from firing.
686 * This is a bit gross, but we know we're on POWER8E and have 6 PMCs.
687 * Using read/write_pmc() in a for loop adds 12 function calls and
688 * almost doubles our code size.
690 pmcs[0] = mfspr(SPRN_PMC1);
691 pmcs[1] = mfspr(SPRN_PMC2);
692 pmcs[2] = mfspr(SPRN_PMC3);
693 pmcs[3] = mfspr(SPRN_PMC4);
694 pmcs[4] = mfspr(SPRN_PMC5);
695 pmcs[5] = mfspr(SPRN_PMC6);
697 /* Ensure all freeze bits are unset */
698 mtspr(SPRN_MMCR2, 0);
700 /* Set up PMC6 to overflow in one cycle */
701 mtspr(SPRN_PMC6, 0x7FFFFFFE);
703 /* Enable exceptions and unfreeze PMC6 */
704 mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO);
706 /* Now we need to refreeze and restore the PMCs */
707 mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO);
709 mtspr(SPRN_PMC1, pmcs[0]);
710 mtspr(SPRN_PMC2, pmcs[1]);
711 mtspr(SPRN_PMC3, pmcs[2]);
712 mtspr(SPRN_PMC4, pmcs[3]);
713 mtspr(SPRN_PMC5, pmcs[4]);
714 mtspr(SPRN_PMC6, pmcs[5]);
717 static bool use_ic(u64 event)
719 if (cpu_has_feature(CPU_FTR_POWER9_DD1) &&
720 (event == 0x200f2 || event == 0x300f2))
725 #endif /* CONFIG_PPC64 */
727 static void perf_event_interrupt(struct pt_regs *regs);
730 * Read one performance monitor counter (PMC).
732 static unsigned long read_pmc(int idx)
738 val = mfspr(SPRN_PMC1);
741 val = mfspr(SPRN_PMC2);
744 val = mfspr(SPRN_PMC3);
747 val = mfspr(SPRN_PMC4);
750 val = mfspr(SPRN_PMC5);
753 val = mfspr(SPRN_PMC6);
757 val = mfspr(SPRN_PMC7);
760 val = mfspr(SPRN_PMC8);
762 #endif /* CONFIG_PPC64 */
764 printk(KERN_ERR "oops trying to read PMC%d\n", idx);
773 static void write_pmc(int idx, unsigned long val)
777 mtspr(SPRN_PMC1, val);
780 mtspr(SPRN_PMC2, val);
783 mtspr(SPRN_PMC3, val);
786 mtspr(SPRN_PMC4, val);
789 mtspr(SPRN_PMC5, val);
792 mtspr(SPRN_PMC6, val);
796 mtspr(SPRN_PMC7, val);
799 mtspr(SPRN_PMC8, val);
801 #endif /* CONFIG_PPC64 */
803 printk(KERN_ERR "oops trying to write PMC%d\n", idx);
807 /* Called from sysrq_handle_showregs() */
808 void perf_event_print_debug(void)
810 unsigned long sdar, sier, flags;
811 u32 pmcs[MAX_HWEVENTS];
815 pr_info("Performance monitor hardware not registered.\n");
819 if (!ppmu->n_counter)
822 local_irq_save(flags);
824 pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d",
825 smp_processor_id(), ppmu->name, ppmu->n_counter);
827 for (i = 0; i < ppmu->n_counter; i++)
828 pmcs[i] = read_pmc(i + 1);
830 for (; i < MAX_HWEVENTS; i++)
831 pmcs[i] = 0xdeadbeef;
833 pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n",
834 pmcs[0], pmcs[1], pmcs[2], pmcs[3]);
836 if (ppmu->n_counter > 4)
837 pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n",
838 pmcs[4], pmcs[5], pmcs[6], pmcs[7]);
840 pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n",
841 mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA));
845 sdar = mfspr(SPRN_SDAR);
847 if (ppmu->flags & PPMU_HAS_SIER)
848 sier = mfspr(SPRN_SIER);
850 if (ppmu->flags & PPMU_ARCH_207S) {
851 pr_info("MMCR2: %016lx EBBHR: %016lx\n",
852 mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR));
853 pr_info("EBBRR: %016lx BESCR: %016lx\n",
854 mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR));
857 pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n",
858 mfspr(SPRN_SIAR), sdar, sier);
860 local_irq_restore(flags);
864 * Check if a set of events can all go on the PMU at once.
865 * If they can't, this will look at alternative codes for the events
866 * and see if any combination of alternative codes is feasible.
867 * The feasible set is returned in event_id[].
869 static int power_check_constraints(struct cpu_hw_events *cpuhw,
870 u64 event_id[], unsigned int cflags[],
873 unsigned long mask, value, nv;
874 unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS];
875 int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS];
877 unsigned long addf = ppmu->add_fields;
878 unsigned long tadd = ppmu->test_adder;
880 if (n_ev > ppmu->n_counter)
883 /* First see if the events will go on as-is */
884 for (i = 0; i < n_ev; ++i) {
885 if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
886 && !ppmu->limited_pmc_event(event_id[i])) {
887 ppmu->get_alternatives(event_id[i], cflags[i],
888 cpuhw->alternatives[i]);
889 event_id[i] = cpuhw->alternatives[i][0];
891 if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0],
892 &cpuhw->avalues[i][0]))
896 for (i = 0; i < n_ev; ++i) {
897 nv = (value | cpuhw->avalues[i][0]) +
898 (value & cpuhw->avalues[i][0] & addf);
899 if ((((nv + tadd) ^ value) & mask) != 0 ||
900 (((nv + tadd) ^ cpuhw->avalues[i][0]) &
901 cpuhw->amasks[i][0]) != 0)
904 mask |= cpuhw->amasks[i][0];
907 return 0; /* all OK */
909 /* doesn't work, gather alternatives... */
910 if (!ppmu->get_alternatives)
912 for (i = 0; i < n_ev; ++i) {
914 n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i],
915 cpuhw->alternatives[i]);
916 for (j = 1; j < n_alt[i]; ++j)
917 ppmu->get_constraint(cpuhw->alternatives[i][j],
918 &cpuhw->amasks[i][j],
919 &cpuhw->avalues[i][j]);
922 /* enumerate all possibilities and see if any will work */
925 value = mask = nv = 0;
928 /* we're backtracking, restore context */
934 * See if any alternative k for event_id i,
935 * where k > j, will satisfy the constraints.
937 while (++j < n_alt[i]) {
938 nv = (value | cpuhw->avalues[i][j]) +
939 (value & cpuhw->avalues[i][j] & addf);
940 if ((((nv + tadd) ^ value) & mask) == 0 &&
941 (((nv + tadd) ^ cpuhw->avalues[i][j])
942 & cpuhw->amasks[i][j]) == 0)
947 * No feasible alternative, backtrack
948 * to event_id i-1 and continue enumerating its
949 * alternatives from where we got up to.
955 * Found a feasible alternative for event_id i,
956 * remember where we got up to with this event_id,
957 * go on to the next event_id, and start with
958 * the first alternative for it.
964 mask |= cpuhw->amasks[i][j];
970 /* OK, we have a feasible combination, tell the caller the solution */
971 for (i = 0; i < n_ev; ++i)
972 event_id[i] = cpuhw->alternatives[i][choice[i]];
977 * Check if newly-added events have consistent settings for
978 * exclude_{user,kernel,hv} with each other and any previously
981 static int check_excludes(struct perf_event **ctrs, unsigned int cflags[],
982 int n_prev, int n_new)
984 int eu = 0, ek = 0, eh = 0;
986 struct perf_event *event;
989 * If the PMU we're on supports per event exclude settings then we
990 * don't need to do any of this logic. NB. This assumes no PMU has both
991 * per event exclude and limited PMCs.
993 if (ppmu->flags & PPMU_ARCH_207S)
1001 for (i = 0; i < n; ++i) {
1002 if (cflags[i] & PPMU_LIMITED_PMC_OK) {
1003 cflags[i] &= ~PPMU_LIMITED_PMC_REQD;
1008 eu = event->attr.exclude_user;
1009 ek = event->attr.exclude_kernel;
1010 eh = event->attr.exclude_hv;
1012 } else if (event->attr.exclude_user != eu ||
1013 event->attr.exclude_kernel != ek ||
1014 event->attr.exclude_hv != eh) {
1020 for (i = 0; i < n; ++i)
1021 if (cflags[i] & PPMU_LIMITED_PMC_OK)
1022 cflags[i] |= PPMU_LIMITED_PMC_REQD;
1027 static u64 check_and_compute_delta(u64 prev, u64 val)
1029 u64 delta = (val - prev) & 0xfffffffful;
1032 * POWER7 can roll back counter values, if the new value is smaller
1033 * than the previous value it will cause the delta and the counter to
1034 * have bogus values unless we rolled a counter over. If a coutner is
1035 * rolled back, it will be smaller, but within 256, which is the maximum
1036 * number of events to rollback at once. If we detect a rollback
1037 * return 0. This can lead to a small lack of precision in the
1040 if (prev > val && (prev - val) < 256)
1046 static void power_pmu_read(struct perf_event *event)
1048 s64 val, delta, prev;
1049 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1051 if (event->hw.state & PERF_HES_STOPPED)
1057 if (is_ebb_event(event)) {
1058 val = read_pmc(event->hw.idx);
1059 if (use_ic(event->attr.config)) {
1060 val = mfspr(SPRN_IC);
1061 if (val > cpuhw->ic_init)
1062 val = val - cpuhw->ic_init;
1064 val = val + (0 - cpuhw->ic_init);
1066 local64_set(&event->hw.prev_count, val);
1071 * Performance monitor interrupts come even when interrupts
1072 * are soft-disabled, as long as interrupts are hard-enabled.
1073 * Therefore we treat them like NMIs.
1076 prev = local64_read(&event->hw.prev_count);
1078 val = read_pmc(event->hw.idx);
1079 if (use_ic(event->attr.config)) {
1080 val = mfspr(SPRN_IC);
1081 if (val > cpuhw->ic_init)
1082 val = val - cpuhw->ic_init;
1084 val = val + (0 - cpuhw->ic_init);
1086 delta = check_and_compute_delta(prev, val);
1089 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
1091 local64_add(delta, &event->count);
1094 * A number of places program the PMC with (0x80000000 - period_left).
1095 * We never want period_left to be less than 1 because we will program
1096 * the PMC with a value >= 0x800000000 and an edge detected PMC will
1097 * roll around to 0 before taking an exception. We have seen this
1100 * To fix this, clamp the minimum value of period_left to 1.
1103 prev = local64_read(&event->hw.period_left);
1107 } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev);
1111 * On some machines, PMC5 and PMC6 can't be written, don't respect
1112 * the freeze conditions, and don't generate interrupts. This tells
1113 * us if `event' is using such a PMC.
1115 static int is_limited_pmc(int pmcnum)
1117 return (ppmu->flags & PPMU_LIMITED_PMC5_6)
1118 && (pmcnum == 5 || pmcnum == 6);
1121 static void freeze_limited_counters(struct cpu_hw_events *cpuhw,
1122 unsigned long pmc5, unsigned long pmc6)
1124 struct perf_event *event;
1125 u64 val, prev, delta;
1128 for (i = 0; i < cpuhw->n_limited; ++i) {
1129 event = cpuhw->limited_counter[i];
1132 val = (event->hw.idx == 5) ? pmc5 : pmc6;
1133 prev = local64_read(&event->hw.prev_count);
1135 delta = check_and_compute_delta(prev, val);
1137 local64_add(delta, &event->count);
1141 static void thaw_limited_counters(struct cpu_hw_events *cpuhw,
1142 unsigned long pmc5, unsigned long pmc6)
1144 struct perf_event *event;
1148 for (i = 0; i < cpuhw->n_limited; ++i) {
1149 event = cpuhw->limited_counter[i];
1150 event->hw.idx = cpuhw->limited_hwidx[i];
1151 val = (event->hw.idx == 5) ? pmc5 : pmc6;
1152 prev = local64_read(&event->hw.prev_count);
1153 if (check_and_compute_delta(prev, val))
1154 local64_set(&event->hw.prev_count, val);
1155 perf_event_update_userpage(event);
1160 * Since limited events don't respect the freeze conditions, we
1161 * have to read them immediately after freezing or unfreezing the
1162 * other events. We try to keep the values from the limited
1163 * events as consistent as possible by keeping the delay (in
1164 * cycles and instructions) between freezing/unfreezing and reading
1165 * the limited events as small and consistent as possible.
1166 * Therefore, if any limited events are in use, we read them
1167 * both, and always in the same order, to minimize variability,
1168 * and do it inside the same asm that writes MMCR0.
1170 static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0)
1172 unsigned long pmc5, pmc6;
1174 if (!cpuhw->n_limited) {
1175 mtspr(SPRN_MMCR0, mmcr0);
1180 * Write MMCR0, then read PMC5 and PMC6 immediately.
1181 * To ensure we don't get a performance monitor interrupt
1182 * between writing MMCR0 and freezing/thawing the limited
1183 * events, we first write MMCR0 with the event overflow
1184 * interrupt enable bits turned off.
1186 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
1187 : "=&r" (pmc5), "=&r" (pmc6)
1188 : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)),
1190 "i" (SPRN_PMC5), "i" (SPRN_PMC6));
1192 if (mmcr0 & MMCR0_FC)
1193 freeze_limited_counters(cpuhw, pmc5, pmc6);
1195 thaw_limited_counters(cpuhw, pmc5, pmc6);
1198 * Write the full MMCR0 including the event overflow interrupt
1199 * enable bits, if necessary.
1201 if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE))
1202 mtspr(SPRN_MMCR0, mmcr0);
1206 * Disable all events to prevent PMU interrupts and to allow
1207 * events to be added or removed.
1209 static void power_pmu_disable(struct pmu *pmu)
1211 struct cpu_hw_events *cpuhw;
1212 unsigned long flags, mmcr0, val;
1216 local_irq_save(flags);
1217 cpuhw = this_cpu_ptr(&cpu_hw_events);
1219 if (!cpuhw->disabled) {
1221 * Check if we ever enabled the PMU on this cpu.
1223 if (!cpuhw->pmcs_enabled) {
1225 cpuhw->pmcs_enabled = 1;
1229 * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56
1231 val = mmcr0 = mfspr(SPRN_MMCR0);
1233 val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO |
1237 * The barrier is to make sure the mtspr has been
1238 * executed and the PMU has frozen the events etc.
1241 write_mmcr0(cpuhw, val);
1246 * Disable instruction sampling if it was enabled
1248 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
1250 cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1255 cpuhw->disabled = 1;
1258 ebb_switch_out(mmcr0);
1262 * These are readable by userspace, may contain kernel
1263 * addresses and are not switched by context switch, so clear
1264 * them now to avoid leaking anything to userspace in general
1265 * including to another process.
1267 if (ppmu->flags & PPMU_ARCH_207S) {
1268 mtspr(SPRN_SDAR, 0);
1269 mtspr(SPRN_SIAR, 0);
1274 local_irq_restore(flags);
1278 * Re-enable all events if disable == 0.
1279 * If we were previously disabled and events were added, then
1280 * put the new config on the PMU.
1282 static void power_pmu_enable(struct pmu *pmu)
1284 struct perf_event *event;
1285 struct cpu_hw_events *cpuhw;
1286 unsigned long flags;
1288 unsigned long val, mmcr0;
1290 unsigned int hwc_index[MAX_HWEVENTS];
1297 local_irq_save(flags);
1299 cpuhw = this_cpu_ptr(&cpu_hw_events);
1300 if (!cpuhw->disabled)
1303 if (cpuhw->n_events == 0) {
1304 ppc_set_pmu_inuse(0);
1308 cpuhw->disabled = 0;
1311 * EBB requires an exclusive group and all events must have the EBB
1312 * flag set, or not set, so we can just check a single event. Also we
1313 * know we have at least one event.
1315 ebb = is_ebb_event(cpuhw->event[0]);
1318 * If we didn't change anything, or only removed events,
1319 * no need to recalculate MMCR* settings and reset the PMCs.
1320 * Just reenable the PMU with the current MMCR* settings
1321 * (possibly updated for removal of events).
1323 if (!cpuhw->n_added) {
1324 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1325 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1330 * Clear all MMCR settings and recompute them for the new set of events.
1332 memset(cpuhw->mmcr, 0, sizeof(cpuhw->mmcr));
1334 if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index,
1335 cpuhw->mmcr, cpuhw->event)) {
1336 /* shouldn't ever get here */
1337 printk(KERN_ERR "oops compute_mmcr failed\n");
1341 if (!(ppmu->flags & PPMU_ARCH_207S)) {
1343 * Add in MMCR0 freeze bits corresponding to the attr.exclude_*
1344 * bits for the first event. We have already checked that all
1345 * events have the same value for these bits as the first event.
1347 event = cpuhw->event[0];
1348 if (event->attr.exclude_user)
1349 cpuhw->mmcr[0] |= MMCR0_FCP;
1350 if (event->attr.exclude_kernel)
1351 cpuhw->mmcr[0] |= freeze_events_kernel;
1352 if (event->attr.exclude_hv)
1353 cpuhw->mmcr[0] |= MMCR0_FCHV;
1357 * Write the new configuration to MMCR* with the freeze
1358 * bit set and set the hardware events to their initial values.
1359 * Then unfreeze the events.
1361 ppc_set_pmu_inuse(1);
1362 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1363 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1364 mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
1366 if (ppmu->flags & PPMU_ARCH_207S)
1367 mtspr(SPRN_MMCR2, cpuhw->mmcr[3]);
1370 * Read off any pre-existing events that need to move
1373 for (i = 0; i < cpuhw->n_events; ++i) {
1374 event = cpuhw->event[i];
1375 if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) {
1376 power_pmu_read(event);
1377 write_pmc(event->hw.idx, 0);
1383 * Initialize the PMCs for all the new and moved events.
1385 cpuhw->n_limited = n_lim = 0;
1386 for (i = 0; i < cpuhw->n_events; ++i) {
1387 event = cpuhw->event[i];
1390 idx = hwc_index[i] + 1;
1391 if (is_limited_pmc(idx)) {
1392 cpuhw->limited_counter[n_lim] = event;
1393 cpuhw->limited_hwidx[n_lim] = idx;
1399 val = local64_read(&event->hw.prev_count);
1402 if (event->hw.sample_period) {
1403 left = local64_read(&event->hw.period_left);
1404 if (left < 0x80000000L)
1405 val = 0x80000000L - left;
1407 local64_set(&event->hw.prev_count, val);
1410 event->hw.idx = idx;
1411 if (event->hw.state & PERF_HES_STOPPED)
1413 write_pmc(idx, val);
1415 perf_event_update_userpage(event);
1417 cpuhw->n_limited = n_lim;
1418 cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
1421 pmao_restore_workaround(ebb);
1423 mmcr0 = ebb_switch_in(ebb, cpuhw);
1426 if (cpuhw->bhrb_users)
1427 ppmu->config_bhrb(cpuhw->bhrb_filter);
1429 write_mmcr0(cpuhw, mmcr0);
1432 * Enable instruction sampling if necessary
1434 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
1436 mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
1441 local_irq_restore(flags);
1444 static int collect_events(struct perf_event *group, int max_count,
1445 struct perf_event *ctrs[], u64 *events,
1446 unsigned int *flags)
1449 struct perf_event *event;
1451 if (group->pmu->task_ctx_nr == perf_hw_context) {
1455 flags[n] = group->hw.event_base;
1456 events[n++] = group->hw.config;
1458 for_each_sibling_event(event, group) {
1459 if (event->pmu->task_ctx_nr == perf_hw_context &&
1460 event->state != PERF_EVENT_STATE_OFF) {
1464 flags[n] = event->hw.event_base;
1465 events[n++] = event->hw.config;
1472 * Add a event to the PMU.
1473 * If all events are not already frozen, then we disable and
1474 * re-enable the PMU in order to get hw_perf_enable to do the
1475 * actual work of reconfiguring the PMU.
1477 static int power_pmu_add(struct perf_event *event, int ef_flags)
1479 struct cpu_hw_events *cpuhw;
1480 unsigned long flags;
1484 local_irq_save(flags);
1485 perf_pmu_disable(event->pmu);
1488 * Add the event to the list (if there is room)
1489 * and check whether the total set is still feasible.
1491 cpuhw = this_cpu_ptr(&cpu_hw_events);
1492 n0 = cpuhw->n_events;
1493 if (n0 >= ppmu->n_counter)
1495 cpuhw->event[n0] = event;
1496 cpuhw->events[n0] = event->hw.config;
1497 cpuhw->flags[n0] = event->hw.event_base;
1500 * This event may have been disabled/stopped in record_and_restart()
1501 * because we exceeded the ->event_limit. If re-starting the event,
1502 * clear the ->hw.state (STOPPED and UPTODATE flags), so the user
1503 * notification is re-enabled.
1505 if (!(ef_flags & PERF_EF_START))
1506 event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
1508 event->hw.state = 0;
1511 * If group events scheduling transaction was started,
1512 * skip the schedulability test here, it will be performed
1513 * at commit time(->commit_txn) as a whole
1515 if (cpuhw->txn_flags & PERF_PMU_TXN_ADD)
1518 if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1))
1520 if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1))
1522 event->hw.config = cpuhw->events[n0];
1525 ebb_event_add(event);
1532 if (has_branch_stack(event)) {
1533 power_pmu_bhrb_enable(event);
1534 cpuhw->bhrb_filter = ppmu->bhrb_filter_map(
1535 event->attr.branch_sample_type);
1539 * Workaround for POWER9 DD1 to use the Instruction Counter
1540 * register value for instruction counting
1542 if (use_ic(event->attr.config))
1543 cpuhw->ic_init = mfspr(SPRN_IC);
1545 perf_pmu_enable(event->pmu);
1546 local_irq_restore(flags);
1551 * Remove a event from the PMU.
1553 static void power_pmu_del(struct perf_event *event, int ef_flags)
1555 struct cpu_hw_events *cpuhw;
1557 unsigned long flags;
1559 local_irq_save(flags);
1560 perf_pmu_disable(event->pmu);
1562 power_pmu_read(event);
1564 cpuhw = this_cpu_ptr(&cpu_hw_events);
1565 for (i = 0; i < cpuhw->n_events; ++i) {
1566 if (event == cpuhw->event[i]) {
1567 while (++i < cpuhw->n_events) {
1568 cpuhw->event[i-1] = cpuhw->event[i];
1569 cpuhw->events[i-1] = cpuhw->events[i];
1570 cpuhw->flags[i-1] = cpuhw->flags[i];
1573 ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr);
1574 if (event->hw.idx) {
1575 write_pmc(event->hw.idx, 0);
1578 perf_event_update_userpage(event);
1582 for (i = 0; i < cpuhw->n_limited; ++i)
1583 if (event == cpuhw->limited_counter[i])
1585 if (i < cpuhw->n_limited) {
1586 while (++i < cpuhw->n_limited) {
1587 cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i];
1588 cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i];
1592 if (cpuhw->n_events == 0) {
1593 /* disable exceptions if no events are running */
1594 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
1597 if (has_branch_stack(event))
1598 power_pmu_bhrb_disable(event);
1600 perf_pmu_enable(event->pmu);
1601 local_irq_restore(flags);
1605 * POWER-PMU does not support disabling individual counters, hence
1606 * program their cycle counter to their max value and ignore the interrupts.
1609 static void power_pmu_start(struct perf_event *event, int ef_flags)
1611 unsigned long flags;
1615 if (!event->hw.idx || !event->hw.sample_period)
1618 if (!(event->hw.state & PERF_HES_STOPPED))
1621 if (ef_flags & PERF_EF_RELOAD)
1622 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1624 local_irq_save(flags);
1625 perf_pmu_disable(event->pmu);
1627 event->hw.state = 0;
1628 left = local64_read(&event->hw.period_left);
1631 if (left < 0x80000000L)
1632 val = 0x80000000L - left;
1634 write_pmc(event->hw.idx, val);
1636 perf_event_update_userpage(event);
1637 perf_pmu_enable(event->pmu);
1638 local_irq_restore(flags);
1641 static void power_pmu_stop(struct perf_event *event, int ef_flags)
1643 unsigned long flags;
1645 if (!event->hw.idx || !event->hw.sample_period)
1648 if (event->hw.state & PERF_HES_STOPPED)
1651 local_irq_save(flags);
1652 perf_pmu_disable(event->pmu);
1654 power_pmu_read(event);
1655 event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
1656 write_pmc(event->hw.idx, 0);
1658 perf_event_update_userpage(event);
1659 perf_pmu_enable(event->pmu);
1660 local_irq_restore(flags);
1664 * Start group events scheduling transaction
1665 * Set the flag to make pmu::enable() not perform the
1666 * schedulability test, it will be performed at commit time
1668 * We only support PERF_PMU_TXN_ADD transactions. Save the
1669 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1672 static void power_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1674 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1676 WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */
1678 cpuhw->txn_flags = txn_flags;
1679 if (txn_flags & ~PERF_PMU_TXN_ADD)
1682 perf_pmu_disable(pmu);
1683 cpuhw->n_txn_start = cpuhw->n_events;
1687 * Stop group events scheduling transaction
1688 * Clear the flag and pmu::enable() will perform the
1689 * schedulability test.
1691 static void power_pmu_cancel_txn(struct pmu *pmu)
1693 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1694 unsigned int txn_flags;
1696 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
1698 txn_flags = cpuhw->txn_flags;
1699 cpuhw->txn_flags = 0;
1700 if (txn_flags & ~PERF_PMU_TXN_ADD)
1703 perf_pmu_enable(pmu);
1707 * Commit group events scheduling transaction
1708 * Perform the group schedulability test as a whole
1709 * Return 0 if success
1711 static int power_pmu_commit_txn(struct pmu *pmu)
1713 struct cpu_hw_events *cpuhw;
1719 cpuhw = this_cpu_ptr(&cpu_hw_events);
1720 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
1722 if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) {
1723 cpuhw->txn_flags = 0;
1727 n = cpuhw->n_events;
1728 if (check_excludes(cpuhw->event, cpuhw->flags, 0, n))
1730 i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n);
1734 for (i = cpuhw->n_txn_start; i < n; ++i)
1735 cpuhw->event[i]->hw.config = cpuhw->events[i];
1737 cpuhw->txn_flags = 0;
1738 perf_pmu_enable(pmu);
1743 * Return 1 if we might be able to put event on a limited PMC,
1745 * A event can only go on a limited PMC if it counts something
1746 * that a limited PMC can count, doesn't require interrupts, and
1747 * doesn't exclude any processor mode.
1749 static int can_go_on_limited_pmc(struct perf_event *event, u64 ev,
1753 u64 alt[MAX_EVENT_ALTERNATIVES];
1755 if (event->attr.exclude_user
1756 || event->attr.exclude_kernel
1757 || event->attr.exclude_hv
1758 || event->attr.sample_period)
1761 if (ppmu->limited_pmc_event(ev))
1765 * The requested event_id isn't on a limited PMC already;
1766 * see if any alternative code goes on a limited PMC.
1768 if (!ppmu->get_alternatives)
1771 flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD;
1772 n = ppmu->get_alternatives(ev, flags, alt);
1778 * Find an alternative event_id that goes on a normal PMC, if possible,
1779 * and return the event_id code, or 0 if there is no such alternative.
1780 * (Note: event_id code 0 is "don't count" on all machines.)
1782 static u64 normal_pmc_alternative(u64 ev, unsigned long flags)
1784 u64 alt[MAX_EVENT_ALTERNATIVES];
1787 flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD);
1788 n = ppmu->get_alternatives(ev, flags, alt);
1794 /* Number of perf_events counting hardware events */
1795 static atomic_t num_events;
1796 /* Used to avoid races in calling reserve/release_pmc_hardware */
1797 static DEFINE_MUTEX(pmc_reserve_mutex);
1800 * Release the PMU if this is the last perf_event.
1802 static void hw_perf_event_destroy(struct perf_event *event)
1804 if (!atomic_add_unless(&num_events, -1, 1)) {
1805 mutex_lock(&pmc_reserve_mutex);
1806 if (atomic_dec_return(&num_events) == 0)
1807 release_pmc_hardware();
1808 mutex_unlock(&pmc_reserve_mutex);
1813 * Translate a generic cache event_id config to a raw event_id code.
1815 static int hw_perf_cache_event(u64 config, u64 *eventp)
1817 unsigned long type, op, result;
1820 if (!ppmu->cache_events)
1824 type = config & 0xff;
1825 op = (config >> 8) & 0xff;
1826 result = (config >> 16) & 0xff;
1828 if (type >= PERF_COUNT_HW_CACHE_MAX ||
1829 op >= PERF_COUNT_HW_CACHE_OP_MAX ||
1830 result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
1833 ev = (*ppmu->cache_events)[type][op][result];
1842 static bool is_event_blacklisted(u64 ev)
1846 for (i=0; i < ppmu->n_blacklist_ev; i++) {
1847 if (ppmu->blacklist_ev[i] == ev)
1854 static int power_pmu_event_init(struct perf_event *event)
1857 unsigned long flags;
1858 struct perf_event *ctrs[MAX_HWEVENTS];
1859 u64 events[MAX_HWEVENTS];
1860 unsigned int cflags[MAX_HWEVENTS];
1863 struct cpu_hw_events *cpuhw;
1868 if (has_branch_stack(event)) {
1869 /* PMU has BHRB enabled */
1870 if (!(ppmu->flags & PPMU_ARCH_207S))
1874 switch (event->attr.type) {
1875 case PERF_TYPE_HARDWARE:
1876 ev = event->attr.config;
1877 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
1880 if (ppmu->blacklist_ev && is_event_blacklisted(ev))
1882 ev = ppmu->generic_events[ev];
1884 case PERF_TYPE_HW_CACHE:
1885 err = hw_perf_cache_event(event->attr.config, &ev);
1889 if (ppmu->blacklist_ev && is_event_blacklisted(ev))
1893 ev = event->attr.config;
1895 if (ppmu->blacklist_ev && is_event_blacklisted(ev))
1902 event->hw.config_base = ev;
1906 * If we are not running on a hypervisor, force the
1907 * exclude_hv bit to 0 so that we don't care what
1908 * the user set it to.
1910 if (!firmware_has_feature(FW_FEATURE_LPAR))
1911 event->attr.exclude_hv = 0;
1914 * If this is a per-task event, then we can use
1915 * PM_RUN_* events interchangeably with their non RUN_*
1916 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
1917 * XXX we should check if the task is an idle task.
1920 if (event->attach_state & PERF_ATTACH_TASK)
1921 flags |= PPMU_ONLY_COUNT_RUN;
1924 * If this machine has limited events, check whether this
1925 * event_id could go on a limited event.
1927 if (ppmu->flags & PPMU_LIMITED_PMC5_6) {
1928 if (can_go_on_limited_pmc(event, ev, flags)) {
1929 flags |= PPMU_LIMITED_PMC_OK;
1930 } else if (ppmu->limited_pmc_event(ev)) {
1932 * The requested event_id is on a limited PMC,
1933 * but we can't use a limited PMC; see if any
1934 * alternative goes on a normal PMC.
1936 ev = normal_pmc_alternative(ev, flags);
1942 /* Extra checks for EBB */
1943 err = ebb_event_check(event);
1948 * If this is in a group, check if it can go on with all the
1949 * other hardware events in the group. We assume the event
1950 * hasn't been linked into its leader's sibling list at this point.
1953 if (event->group_leader != event) {
1954 n = collect_events(event->group_leader, ppmu->n_counter - 1,
1955 ctrs, events, cflags);
1962 if (check_excludes(ctrs, cflags, n, 1))
1965 cpuhw = &get_cpu_var(cpu_hw_events);
1966 err = power_check_constraints(cpuhw, events, cflags, n + 1);
1968 if (has_branch_stack(event)) {
1969 cpuhw->bhrb_filter = ppmu->bhrb_filter_map(
1970 event->attr.branch_sample_type);
1972 if (cpuhw->bhrb_filter == -1) {
1973 put_cpu_var(cpu_hw_events);
1978 put_cpu_var(cpu_hw_events);
1982 event->hw.config = events[n];
1983 event->hw.event_base = cflags[n];
1984 event->hw.last_period = event->hw.sample_period;
1985 local64_set(&event->hw.period_left, event->hw.last_period);
1988 * For EBB events we just context switch the PMC value, we don't do any
1989 * of the sample_period logic. We use hw.prev_count for this.
1991 if (is_ebb_event(event))
1992 local64_set(&event->hw.prev_count, 0);
1995 * See if we need to reserve the PMU.
1996 * If no events are currently in use, then we have to take a
1997 * mutex to ensure that we don't race with another task doing
1998 * reserve_pmc_hardware or release_pmc_hardware.
2001 if (!atomic_inc_not_zero(&num_events)) {
2002 mutex_lock(&pmc_reserve_mutex);
2003 if (atomic_read(&num_events) == 0 &&
2004 reserve_pmc_hardware(perf_event_interrupt))
2007 atomic_inc(&num_events);
2008 mutex_unlock(&pmc_reserve_mutex);
2010 event->destroy = hw_perf_event_destroy;
2015 static int power_pmu_event_idx(struct perf_event *event)
2017 return event->hw.idx;
2020 ssize_t power_events_sysfs_show(struct device *dev,
2021 struct device_attribute *attr, char *page)
2023 struct perf_pmu_events_attr *pmu_attr;
2025 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
2027 return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
2030 static struct pmu power_pmu = {
2031 .pmu_enable = power_pmu_enable,
2032 .pmu_disable = power_pmu_disable,
2033 .event_init = power_pmu_event_init,
2034 .add = power_pmu_add,
2035 .del = power_pmu_del,
2036 .start = power_pmu_start,
2037 .stop = power_pmu_stop,
2038 .read = power_pmu_read,
2039 .start_txn = power_pmu_start_txn,
2040 .cancel_txn = power_pmu_cancel_txn,
2041 .commit_txn = power_pmu_commit_txn,
2042 .event_idx = power_pmu_event_idx,
2043 .sched_task = power_pmu_sched_task,
2047 * A counter has overflowed; update its count and record
2048 * things if requested. Note that interrupts are hard-disabled
2049 * here so there is no possibility of being interrupted.
2051 static void record_and_restart(struct perf_event *event, unsigned long val,
2052 struct pt_regs *regs)
2054 u64 period = event->hw.sample_period;
2055 s64 prev, delta, left;
2058 if (event->hw.state & PERF_HES_STOPPED) {
2059 write_pmc(event->hw.idx, 0);
2063 /* we don't have to worry about interrupts here */
2064 prev = local64_read(&event->hw.prev_count);
2065 delta = check_and_compute_delta(prev, val);
2066 local64_add(delta, &event->count);
2069 * See if the total period for this event has expired,
2070 * and update for the next period.
2073 left = local64_read(&event->hw.period_left) - delta;
2081 record = siar_valid(regs);
2082 event->hw.last_period = event->hw.sample_period;
2084 if (left < 0x80000000LL)
2085 val = 0x80000000LL - left;
2088 write_pmc(event->hw.idx, val);
2089 local64_set(&event->hw.prev_count, val);
2090 local64_set(&event->hw.period_left, left);
2091 perf_event_update_userpage(event);
2094 * Finally record data if requested.
2097 struct perf_sample_data data;
2099 perf_sample_data_init(&data, ~0ULL, event->hw.last_period);
2101 if (event->attr.sample_type &
2102 (PERF_SAMPLE_ADDR | PERF_SAMPLE_PHYS_ADDR))
2103 perf_get_data_addr(regs, &data.addr);
2105 if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) {
2106 struct cpu_hw_events *cpuhw;
2107 cpuhw = this_cpu_ptr(&cpu_hw_events);
2108 power_pmu_bhrb_read(cpuhw);
2109 data.br_stack = &cpuhw->bhrb_stack;
2112 if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC &&
2113 ppmu->get_mem_data_src)
2114 ppmu->get_mem_data_src(&data.data_src, ppmu->flags, regs);
2116 if (event->attr.sample_type & PERF_SAMPLE_WEIGHT &&
2117 ppmu->get_mem_weight)
2118 ppmu->get_mem_weight(&data.weight);
2120 if (perf_event_overflow(event, &data, regs))
2121 power_pmu_stop(event, 0);
2126 * Called from generic code to get the misc flags (i.e. processor mode)
2129 unsigned long perf_misc_flags(struct pt_regs *regs)
2131 u32 flags = perf_get_misc_flags(regs);
2135 return user_mode(regs) ? PERF_RECORD_MISC_USER :
2136 PERF_RECORD_MISC_KERNEL;
2140 * Called from generic code to get the instruction pointer
2143 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2145 bool use_siar = regs_use_siar(regs);
2147 if (use_siar && siar_valid(regs))
2148 return mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
2150 return 0; // no valid instruction pointer
2155 static bool pmc_overflow_power7(unsigned long val)
2158 * Events on POWER7 can roll back if a speculative event doesn't
2159 * eventually complete. Unfortunately in some rare cases they will
2160 * raise a performance monitor exception. We need to catch this to
2161 * ensure we reset the PMC. In all cases the PMC will be 256 or less
2162 * cycles from overflow.
2164 * We only do this if the first pass fails to find any overflowing
2165 * PMCs because a user might set a period of less than 256 and we
2166 * don't want to mistakenly reset them.
2168 if ((0x80000000 - val) <= 256)
2174 static bool pmc_overflow(unsigned long val)
2183 * Performance monitor interrupt stuff
2185 static void perf_event_interrupt(struct pt_regs *regs)
2188 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
2189 struct perf_event *event;
2190 unsigned long val[8];
2194 if (cpuhw->n_limited)
2195 freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5),
2198 perf_read_regs(regs);
2200 nmi = perf_intr_is_nmi(regs);
2206 /* Read all the PMCs since we'll need them a bunch of times */
2207 for (i = 0; i < ppmu->n_counter; ++i)
2208 val[i] = read_pmc(i + 1);
2210 /* Try to find what caused the IRQ */
2212 for (i = 0; i < ppmu->n_counter; ++i) {
2213 if (!pmc_overflow(val[i]))
2215 if (is_limited_pmc(i + 1))
2216 continue; /* these won't generate IRQs */
2218 * We've found one that's overflowed. For active
2219 * counters we need to log this. For inactive
2220 * counters, we need to reset it anyway
2224 for (j = 0; j < cpuhw->n_events; ++j) {
2225 event = cpuhw->event[j];
2226 if (event->hw.idx == (i + 1)) {
2228 record_and_restart(event, val[i], regs);
2233 /* reset non active counters that have overflowed */
2234 write_pmc(i + 1, 0);
2236 if (!found && pvr_version_is(PVR_POWER7)) {
2237 /* check active counters for special buggy p7 overflow */
2238 for (i = 0; i < cpuhw->n_events; ++i) {
2239 event = cpuhw->event[i];
2240 if (!event->hw.idx || is_limited_pmc(event->hw.idx))
2242 if (pmc_overflow_power7(val[event->hw.idx - 1])) {
2243 /* event has overflowed in a buggy way*/
2245 record_and_restart(event,
2246 val[event->hw.idx - 1],
2251 if (!found && !nmi && printk_ratelimit())
2252 printk(KERN_WARNING "Can't find PMC that caused IRQ\n");
2255 * Reset MMCR0 to its normal value. This will set PMXE and
2256 * clear FC (freeze counters) and PMAO (perf mon alert occurred)
2257 * and thus allow interrupts to occur again.
2258 * XXX might want to use MSR.PM to keep the events frozen until
2259 * we get back out of this interrupt.
2261 write_mmcr0(cpuhw, cpuhw->mmcr[0]);
2269 static int power_pmu_prepare_cpu(unsigned int cpu)
2271 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
2274 memset(cpuhw, 0, sizeof(*cpuhw));
2275 cpuhw->mmcr[0] = MMCR0_FC;
2280 int register_power_pmu(struct power_pmu *pmu)
2283 return -EBUSY; /* something's already registered */
2286 pr_info("%s performance monitor hardware support registered\n",
2289 power_pmu.attr_groups = ppmu->attr_groups;
2293 * Use FCHV to ignore kernel events if MSR.HV is set.
2295 if (mfmsr() & MSR_HV)
2296 freeze_events_kernel = MMCR0_FCHV;
2297 #endif /* CONFIG_PPC64 */
2299 perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW);
2300 cpuhp_setup_state(CPUHP_PERF_POWER, "perf/powerpc:prepare",
2301 power_pmu_prepare_cpu, NULL);