1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Performance event support - powerpc architecture code
5 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
9 #include <linux/sched/clock.h>
10 #include <linux/perf_event.h>
11 #include <linux/percpu.h>
12 #include <linux/hardirq.h>
13 #include <linux/uaccess.h>
16 #include <asm/machdep.h>
17 #include <asm/firmware.h>
18 #include <asm/ptrace.h>
19 #include <asm/code-patching.h>
25 #define BHRB_MAX_ENTRIES 32
26 #define BHRB_TARGET 0x0000000000000002
27 #define BHRB_PREDICTION 0x0000000000000001
28 #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL
30 struct cpu_hw_events {
37 struct perf_event *event[MAX_HWEVENTS];
38 u64 events[MAX_HWEVENTS];
39 unsigned int flags[MAX_HWEVENTS];
41 * The order of the MMCR array is:
42 * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2
43 * - 32-bit, MMCR0, MMCR1, MMCR2
45 unsigned long mmcr[4];
46 struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS];
47 u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS];
48 u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
49 unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
50 unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
52 unsigned int txn_flags;
56 u64 bhrb_filter; /* BHRB HW branch filter */
57 unsigned int bhrb_users;
59 struct perf_branch_stack bhrb_stack;
60 struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES];
64 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
66 static struct power_pmu *ppmu;
69 * Normally, to ignore kernel events we set the FCS (freeze counters
70 * in supervisor mode) bit in MMCR0, but if the kernel runs with the
71 * hypervisor bit set in the MSR, or if we are running on a processor
72 * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
73 * then we need to use the FCHV bit to ignore kernel events.
75 static unsigned int freeze_events_kernel = MMCR0_FCS;
78 * 32-bit doesn't have MMCRA but does have an MMCR2,
79 * and a few other names are different.
84 #define MMCR0_PMCjCE MMCR0_PMCnCE
90 #define MMCR0_PMCC_U6 0
92 #define SPRN_MMCRA SPRN_MMCR2
93 #define MMCRA_SAMPLE_ENABLE 0
95 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
99 static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs *regs, u64 *addrp) { }
100 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
104 static inline void perf_read_regs(struct pt_regs *regs)
108 static inline int perf_intr_is_nmi(struct pt_regs *regs)
113 static inline int siar_valid(struct pt_regs *regs)
118 static bool is_ebb_event(struct perf_event *event) { return false; }
119 static int ebb_event_check(struct perf_event *event) { return 0; }
120 static void ebb_event_add(struct perf_event *event) { }
121 static void ebb_switch_out(unsigned long mmcr0) { }
122 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
124 return cpuhw->mmcr[0];
127 static inline void power_pmu_bhrb_enable(struct perf_event *event) {}
128 static inline void power_pmu_bhrb_disable(struct perf_event *event) {}
129 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {}
130 static inline void power_pmu_bhrb_read(struct perf_event *event, struct cpu_hw_events *cpuhw) {}
131 static void pmao_restore_workaround(bool ebb) { }
132 #endif /* CONFIG_PPC32 */
134 bool is_sier_available(void)
136 if (ppmu->flags & PPMU_HAS_SIER)
142 static bool regs_use_siar(struct pt_regs *regs)
145 * When we take a performance monitor exception the regs are setup
146 * using perf_read_regs() which overloads some fields, in particular
147 * regs->result to tell us whether to use SIAR.
149 * However if the regs are from another exception, eg. a syscall, then
150 * they have not been setup using perf_read_regs() and so regs->result
151 * is something random.
153 return ((TRAP(regs) == 0xf00) && regs->result);
157 * Things that are specific to 64-bit implementations.
161 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
163 unsigned long mmcra = regs->dsisr;
165 if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) {
166 unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
168 return 4 * (slot - 1);
175 * The user wants a data address recorded.
176 * If we're not doing instruction sampling, give them the SDAR
177 * (sampled data address). If we are doing instruction sampling, then
178 * only give them the SDAR if it corresponds to the instruction
179 * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the
180 * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER.
182 static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs *regs, u64 *addrp)
184 unsigned long mmcra = regs->dsisr;
187 if (ppmu->flags & PPMU_HAS_SIER)
188 sdar_valid = regs->dar & SIER_SDAR_VALID;
190 unsigned long sdsync;
192 if (ppmu->flags & PPMU_SIAR_VALID)
193 sdsync = POWER7P_MMCRA_SDAR_VALID;
194 else if (ppmu->flags & PPMU_ALT_SIPR)
195 sdsync = POWER6_MMCRA_SDSYNC;
196 else if (ppmu->flags & PPMU_NO_SIAR)
197 sdsync = MMCRA_SAMPLE_ENABLE;
199 sdsync = MMCRA_SDSYNC;
201 sdar_valid = mmcra & sdsync;
204 if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid)
205 *addrp = mfspr(SPRN_SDAR);
207 if (is_kernel_addr(mfspr(SPRN_SDAR)) && perf_allow_kernel(&event->attr) != 0)
211 static bool regs_sihv(struct pt_regs *regs)
213 unsigned long sihv = MMCRA_SIHV;
215 if (ppmu->flags & PPMU_HAS_SIER)
216 return !!(regs->dar & SIER_SIHV);
218 if (ppmu->flags & PPMU_ALT_SIPR)
219 sihv = POWER6_MMCRA_SIHV;
221 return !!(regs->dsisr & sihv);
224 static bool regs_sipr(struct pt_regs *regs)
226 unsigned long sipr = MMCRA_SIPR;
228 if (ppmu->flags & PPMU_HAS_SIER)
229 return !!(regs->dar & SIER_SIPR);
231 if (ppmu->flags & PPMU_ALT_SIPR)
232 sipr = POWER6_MMCRA_SIPR;
234 return !!(regs->dsisr & sipr);
237 static inline u32 perf_flags_from_msr(struct pt_regs *regs)
239 if (regs->msr & MSR_PR)
240 return PERF_RECORD_MISC_USER;
241 if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV)
242 return PERF_RECORD_MISC_HYPERVISOR;
243 return PERF_RECORD_MISC_KERNEL;
246 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
248 bool use_siar = regs_use_siar(regs);
251 return perf_flags_from_msr(regs);
254 * If we don't have flags in MMCRA, rather than using
255 * the MSR, we intuit the flags from the address in
256 * SIAR which should give slightly more reliable
259 if (ppmu->flags & PPMU_NO_SIPR) {
260 unsigned long siar = mfspr(SPRN_SIAR);
261 if (is_kernel_addr(siar))
262 return PERF_RECORD_MISC_KERNEL;
263 return PERF_RECORD_MISC_USER;
266 /* PR has priority over HV, so order below is important */
268 return PERF_RECORD_MISC_USER;
270 if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV))
271 return PERF_RECORD_MISC_HYPERVISOR;
273 return PERF_RECORD_MISC_KERNEL;
277 * Overload regs->dsisr to store MMCRA so we only need to read it once
279 * Overload regs->dar to store SIER if we have it.
280 * Overload regs->result to specify whether we should use the MSR (result
281 * is zero) or the SIAR (result is non zero).
283 static inline void perf_read_regs(struct pt_regs *regs)
285 unsigned long mmcra = mfspr(SPRN_MMCRA);
286 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
291 if (ppmu->flags & PPMU_HAS_SIER)
292 regs->dar = mfspr(SPRN_SIER);
295 * If this isn't a PMU exception (eg a software event) the SIAR is
296 * not valid. Use pt_regs.
298 * If it is a marked event use the SIAR.
300 * If the PMU doesn't update the SIAR for non marked events use
303 * If the PMU has HV/PR flags then check to see if they
304 * place the exception in userspace. If so, use pt_regs. In
305 * continuous sampling mode the SIAR and the PMU exception are
306 * not synchronised, so they may be many instructions apart.
307 * This can result in confusing backtraces. We still want
308 * hypervisor samples as well as samples in the kernel with
309 * interrupts off hence the userspace check.
311 if (TRAP(regs) != 0xf00)
313 else if ((ppmu->flags & PPMU_NO_SIAR))
317 else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING))
319 else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs))
324 regs->result = use_siar;
328 * If interrupts were soft-disabled when a PMU interrupt occurs, treat
331 static inline int perf_intr_is_nmi(struct pt_regs *regs)
333 return (regs->softe & IRQS_DISABLED);
337 * On processors like P7+ that have the SIAR-Valid bit, marked instructions
338 * must be sampled only if the SIAR-valid bit is set.
340 * For unmarked instructions and for processors that don't have the SIAR-Valid
341 * bit, assume that SIAR is valid.
343 static inline int siar_valid(struct pt_regs *regs)
345 unsigned long mmcra = regs->dsisr;
346 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
349 if (ppmu->flags & PPMU_HAS_SIER)
350 return regs->dar & SIER_SIAR_VALID;
352 if (ppmu->flags & PPMU_SIAR_VALID)
353 return mmcra & POWER7P_MMCRA_SIAR_VALID;
360 /* Reset all possible BHRB entries */
361 static void power_pmu_bhrb_reset(void)
363 asm volatile(PPC_CLRBHRB);
366 static void power_pmu_bhrb_enable(struct perf_event *event)
368 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
373 /* Clear BHRB if we changed task context to avoid data leaks */
374 if (event->ctx->task && cpuhw->bhrb_context != event->ctx) {
375 power_pmu_bhrb_reset();
376 cpuhw->bhrb_context = event->ctx;
379 perf_sched_cb_inc(event->ctx->pmu);
382 static void power_pmu_bhrb_disable(struct perf_event *event)
384 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
389 WARN_ON_ONCE(!cpuhw->bhrb_users);
391 perf_sched_cb_dec(event->ctx->pmu);
393 if (!cpuhw->disabled && !cpuhw->bhrb_users) {
394 /* BHRB cannot be turned off when other
395 * events are active on the PMU.
398 /* avoid stale pointer */
399 cpuhw->bhrb_context = NULL;
403 /* Called from ctxsw to prevent one process's branch entries to
404 * mingle with the other process's entries during context switch.
406 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
412 power_pmu_bhrb_reset();
414 /* Calculate the to address for a branch */
415 static __u64 power_pmu_bhrb_to(u64 addr)
420 if (is_kernel_addr(addr)) {
421 if (probe_kernel_read(&instr, (void *)addr, sizeof(instr)))
424 return branch_target(&instr);
427 /* Userspace: need copy instruction here then translate it */
428 if (probe_user_read(&instr, (unsigned int __user *)addr, sizeof(instr)))
431 target = branch_target(&instr);
432 if ((!target) || (instr & BRANCH_ABSOLUTE))
435 /* Translate relative branch target from kernel to user address */
436 return target - (unsigned long)&instr + addr;
439 /* Processing BHRB entries */
440 static void power_pmu_bhrb_read(struct perf_event *event, struct cpu_hw_events *cpuhw)
444 int r_index, u_index, pred;
448 while (r_index < ppmu->bhrb_nr) {
449 /* Assembly read function */
450 val = read_bhrb(r_index++);
452 /* Terminal marker: End of valid BHRB entries */
455 addr = val & BHRB_EA;
456 pred = val & BHRB_PREDICTION;
463 * BHRB rolling buffer could very much contain the kernel
464 * addresses at this point. Check the privileges before
465 * exporting it to userspace (avoid exposure of regions
466 * where we could have speculative execution)
468 if (is_kernel_addr(addr) && perf_allow_kernel(&event->attr) != 0)
471 /* Branches are read most recent first (ie. mfbhrb 0 is
472 * the most recent branch).
473 * There are two types of valid entries:
474 * 1) a target entry which is the to address of a
475 * computed goto like a blr,bctr,btar. The next
476 * entry read from the bhrb will be branch
477 * corresponding to this target (ie. the actual
478 * blr/bctr/btar instruction).
479 * 2) a from address which is an actual branch. If a
480 * target entry proceeds this, then this is the
481 * matching branch for that target. If this is not
482 * following a target entry, then this is a branch
483 * where the target is given as an immediate field
484 * in the instruction (ie. an i or b form branch).
485 * In this case we need to read the instruction from
486 * memory to determine the target/to address.
489 if (val & BHRB_TARGET) {
490 /* Target branches use two entries
491 * (ie. computed gotos/XL form)
493 cpuhw->bhrb_entries[u_index].to = addr;
494 cpuhw->bhrb_entries[u_index].mispred = pred;
495 cpuhw->bhrb_entries[u_index].predicted = ~pred;
497 /* Get from address in next entry */
498 val = read_bhrb(r_index++);
499 addr = val & BHRB_EA;
500 if (val & BHRB_TARGET) {
501 /* Shouldn't have two targets in a
502 row.. Reset index and try again */
506 cpuhw->bhrb_entries[u_index].from = addr;
508 /* Branches to immediate field
510 cpuhw->bhrb_entries[u_index].from = addr;
511 cpuhw->bhrb_entries[u_index].to =
512 power_pmu_bhrb_to(addr);
513 cpuhw->bhrb_entries[u_index].mispred = pred;
514 cpuhw->bhrb_entries[u_index].predicted = ~pred;
520 cpuhw->bhrb_stack.nr = u_index;
524 static bool is_ebb_event(struct perf_event *event)
527 * This could be a per-PMU callback, but we'd rather avoid the cost. We
528 * check that the PMU supports EBB, meaning those that don't can still
529 * use bit 63 of the event code for something else if they wish.
531 return (ppmu->flags & PPMU_ARCH_207S) &&
532 ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1);
535 static int ebb_event_check(struct perf_event *event)
537 struct perf_event *leader = event->group_leader;
539 /* Event and group leader must agree on EBB */
540 if (is_ebb_event(leader) != is_ebb_event(event))
543 if (is_ebb_event(event)) {
544 if (!(event->attach_state & PERF_ATTACH_TASK))
547 if (!leader->attr.pinned || !leader->attr.exclusive)
550 if (event->attr.freq ||
551 event->attr.inherit ||
552 event->attr.sample_type ||
553 event->attr.sample_period ||
554 event->attr.enable_on_exec)
561 static void ebb_event_add(struct perf_event *event)
563 if (!is_ebb_event(event) || current->thread.used_ebb)
567 * IFF this is the first time we've added an EBB event, set
568 * PMXE in the user MMCR0 so we can detect when it's cleared by
569 * userspace. We need this so that we can context switch while
570 * userspace is in the EBB handler (where PMXE is 0).
572 current->thread.used_ebb = 1;
573 current->thread.mmcr0 |= MMCR0_PMXE;
576 static void ebb_switch_out(unsigned long mmcr0)
578 if (!(mmcr0 & MMCR0_EBE))
581 current->thread.siar = mfspr(SPRN_SIAR);
582 current->thread.sier = mfspr(SPRN_SIER);
583 current->thread.sdar = mfspr(SPRN_SDAR);
584 current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK;
585 current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK;
588 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
590 unsigned long mmcr0 = cpuhw->mmcr[0];
595 /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */
596 mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6;
599 * Add any bits from the user MMCR0, FC or PMAO. This is compatible
600 * with pmao_restore_workaround() because we may add PMAO but we never
603 mmcr0 |= current->thread.mmcr0;
606 * Be careful not to set PMXE if userspace had it cleared. This is also
607 * compatible with pmao_restore_workaround() because it has already
608 * cleared PMXE and we leave PMAO alone.
610 if (!(current->thread.mmcr0 & MMCR0_PMXE))
611 mmcr0 &= ~MMCR0_PMXE;
613 mtspr(SPRN_SIAR, current->thread.siar);
614 mtspr(SPRN_SIER, current->thread.sier);
615 mtspr(SPRN_SDAR, current->thread.sdar);
618 * Merge the kernel & user values of MMCR2. The semantics we implement
619 * are that the user MMCR2 can set bits, ie. cause counters to freeze,
620 * but not clear bits. If a task wants to be able to clear bits, ie.
621 * unfreeze counters, it should not set exclude_xxx in its events and
622 * instead manage the MMCR2 entirely by itself.
624 mtspr(SPRN_MMCR2, cpuhw->mmcr[3] | current->thread.mmcr2);
629 static void pmao_restore_workaround(bool ebb)
633 if (!cpu_has_feature(CPU_FTR_PMAO_BUG))
637 * On POWER8E there is a hardware defect which affects the PMU context
638 * switch logic, ie. power_pmu_disable/enable().
640 * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0
641 * by the hardware. Sometime later the actual PMU exception is
644 * If we context switch, or simply disable/enable, the PMU prior to the
645 * exception arriving, the exception will be lost when we clear PMAO.
647 * When we reenable the PMU, we will write the saved MMCR0 with PMAO
648 * set, and this _should_ generate an exception. However because of the
649 * defect no exception is generated when we write PMAO, and we get
650 * stuck with no counters counting but no exception delivered.
652 * The workaround is to detect this case and tweak the hardware to
653 * create another pending PMU exception.
655 * We do that by setting up PMC6 (cycles) for an imminent overflow and
656 * enabling the PMU. That causes a new exception to be generated in the
657 * chip, but we don't take it yet because we have interrupts hard
658 * disabled. We then write back the PMU state as we want it to be seen
659 * by the exception handler. When we reenable interrupts the exception
660 * handler will be called and see the correct state.
662 * The logic is the same for EBB, except that the exception is gated by
663 * us having interrupts hard disabled as well as the fact that we are
664 * not in userspace. The exception is finally delivered when we return
668 /* Only if PMAO is set and PMAO_SYNC is clear */
669 if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO)
672 /* If we're doing EBB, only if BESCR[GE] is set */
673 if (ebb && !(current->thread.bescr & BESCR_GE))
677 * We are already soft-disabled in power_pmu_enable(). We need to hard
678 * disable to actually prevent the PMU exception from firing.
683 * This is a bit gross, but we know we're on POWER8E and have 6 PMCs.
684 * Using read/write_pmc() in a for loop adds 12 function calls and
685 * almost doubles our code size.
687 pmcs[0] = mfspr(SPRN_PMC1);
688 pmcs[1] = mfspr(SPRN_PMC2);
689 pmcs[2] = mfspr(SPRN_PMC3);
690 pmcs[3] = mfspr(SPRN_PMC4);
691 pmcs[4] = mfspr(SPRN_PMC5);
692 pmcs[5] = mfspr(SPRN_PMC6);
694 /* Ensure all freeze bits are unset */
695 mtspr(SPRN_MMCR2, 0);
697 /* Set up PMC6 to overflow in one cycle */
698 mtspr(SPRN_PMC6, 0x7FFFFFFE);
700 /* Enable exceptions and unfreeze PMC6 */
701 mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO);
703 /* Now we need to refreeze and restore the PMCs */
704 mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO);
706 mtspr(SPRN_PMC1, pmcs[0]);
707 mtspr(SPRN_PMC2, pmcs[1]);
708 mtspr(SPRN_PMC3, pmcs[2]);
709 mtspr(SPRN_PMC4, pmcs[3]);
710 mtspr(SPRN_PMC5, pmcs[4]);
711 mtspr(SPRN_PMC6, pmcs[5]);
714 #endif /* CONFIG_PPC64 */
716 static void perf_event_interrupt(struct pt_regs *regs);
719 * Read one performance monitor counter (PMC).
721 static unsigned long read_pmc(int idx)
727 val = mfspr(SPRN_PMC1);
730 val = mfspr(SPRN_PMC2);
733 val = mfspr(SPRN_PMC3);
736 val = mfspr(SPRN_PMC4);
739 val = mfspr(SPRN_PMC5);
742 val = mfspr(SPRN_PMC6);
746 val = mfspr(SPRN_PMC7);
749 val = mfspr(SPRN_PMC8);
751 #endif /* CONFIG_PPC64 */
753 printk(KERN_ERR "oops trying to read PMC%d\n", idx);
762 static void write_pmc(int idx, unsigned long val)
766 mtspr(SPRN_PMC1, val);
769 mtspr(SPRN_PMC2, val);
772 mtspr(SPRN_PMC3, val);
775 mtspr(SPRN_PMC4, val);
778 mtspr(SPRN_PMC5, val);
781 mtspr(SPRN_PMC6, val);
785 mtspr(SPRN_PMC7, val);
788 mtspr(SPRN_PMC8, val);
790 #endif /* CONFIG_PPC64 */
792 printk(KERN_ERR "oops trying to write PMC%d\n", idx);
796 /* Called from sysrq_handle_showregs() */
797 void perf_event_print_debug(void)
799 unsigned long sdar, sier, flags;
800 u32 pmcs[MAX_HWEVENTS];
804 pr_info("Performance monitor hardware not registered.\n");
808 if (!ppmu->n_counter)
811 local_irq_save(flags);
813 pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d",
814 smp_processor_id(), ppmu->name, ppmu->n_counter);
816 for (i = 0; i < ppmu->n_counter; i++)
817 pmcs[i] = read_pmc(i + 1);
819 for (; i < MAX_HWEVENTS; i++)
820 pmcs[i] = 0xdeadbeef;
822 pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n",
823 pmcs[0], pmcs[1], pmcs[2], pmcs[3]);
825 if (ppmu->n_counter > 4)
826 pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n",
827 pmcs[4], pmcs[5], pmcs[6], pmcs[7]);
829 pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n",
830 mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA));
834 sdar = mfspr(SPRN_SDAR);
836 if (ppmu->flags & PPMU_HAS_SIER)
837 sier = mfspr(SPRN_SIER);
839 if (ppmu->flags & PPMU_ARCH_207S) {
840 pr_info("MMCR2: %016lx EBBHR: %016lx\n",
841 mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR));
842 pr_info("EBBRR: %016lx BESCR: %016lx\n",
843 mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR));
846 pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n",
847 mfspr(SPRN_SIAR), sdar, sier);
849 local_irq_restore(flags);
853 * Check if a set of events can all go on the PMU at once.
854 * If they can't, this will look at alternative codes for the events
855 * and see if any combination of alternative codes is feasible.
856 * The feasible set is returned in event_id[].
858 static int power_check_constraints(struct cpu_hw_events *cpuhw,
859 u64 event_id[], unsigned int cflags[],
862 unsigned long mask, value, nv;
863 unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS];
864 int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS];
866 unsigned long addf = ppmu->add_fields;
867 unsigned long tadd = ppmu->test_adder;
868 unsigned long grp_mask = ppmu->group_constraint_mask;
869 unsigned long grp_val = ppmu->group_constraint_val;
871 if (n_ev > ppmu->n_counter)
874 /* First see if the events will go on as-is */
875 for (i = 0; i < n_ev; ++i) {
876 if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
877 && !ppmu->limited_pmc_event(event_id[i])) {
878 ppmu->get_alternatives(event_id[i], cflags[i],
879 cpuhw->alternatives[i]);
880 event_id[i] = cpuhw->alternatives[i][0];
882 if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0],
883 &cpuhw->avalues[i][0]))
887 for (i = 0; i < n_ev; ++i) {
888 nv = (value | cpuhw->avalues[i][0]) +
889 (value & cpuhw->avalues[i][0] & addf);
891 if (((((nv + tadd) ^ value) & mask) & (~grp_mask)) != 0)
894 if (((((nv + tadd) ^ cpuhw->avalues[i][0]) & cpuhw->amasks[i][0])
899 mask |= cpuhw->amasks[i][0];
902 if ((value & mask & grp_mask) != (mask & grp_val))
905 return 0; /* all OK */
908 /* doesn't work, gather alternatives... */
909 if (!ppmu->get_alternatives)
911 for (i = 0; i < n_ev; ++i) {
913 n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i],
914 cpuhw->alternatives[i]);
915 for (j = 1; j < n_alt[i]; ++j)
916 ppmu->get_constraint(cpuhw->alternatives[i][j],
917 &cpuhw->amasks[i][j],
918 &cpuhw->avalues[i][j]);
921 /* enumerate all possibilities and see if any will work */
924 value = mask = nv = 0;
927 /* we're backtracking, restore context */
933 * See if any alternative k for event_id i,
934 * where k > j, will satisfy the constraints.
936 while (++j < n_alt[i]) {
937 nv = (value | cpuhw->avalues[i][j]) +
938 (value & cpuhw->avalues[i][j] & addf);
939 if ((((nv + tadd) ^ value) & mask) == 0 &&
940 (((nv + tadd) ^ cpuhw->avalues[i][j])
941 & cpuhw->amasks[i][j]) == 0)
946 * No feasible alternative, backtrack
947 * to event_id i-1 and continue enumerating its
948 * alternatives from where we got up to.
954 * Found a feasible alternative for event_id i,
955 * remember where we got up to with this event_id,
956 * go on to the next event_id, and start with
957 * the first alternative for it.
963 mask |= cpuhw->amasks[i][j];
969 /* OK, we have a feasible combination, tell the caller the solution */
970 for (i = 0; i < n_ev; ++i)
971 event_id[i] = cpuhw->alternatives[i][choice[i]];
976 * Check if newly-added events have consistent settings for
977 * exclude_{user,kernel,hv} with each other and any previously
980 static int check_excludes(struct perf_event **ctrs, unsigned int cflags[],
981 int n_prev, int n_new)
983 int eu = 0, ek = 0, eh = 0;
985 struct perf_event *event;
988 * If the PMU we're on supports per event exclude settings then we
989 * don't need to do any of this logic. NB. This assumes no PMU has both
990 * per event exclude and limited PMCs.
992 if (ppmu->flags & PPMU_ARCH_207S)
1000 for (i = 0; i < n; ++i) {
1001 if (cflags[i] & PPMU_LIMITED_PMC_OK) {
1002 cflags[i] &= ~PPMU_LIMITED_PMC_REQD;
1007 eu = event->attr.exclude_user;
1008 ek = event->attr.exclude_kernel;
1009 eh = event->attr.exclude_hv;
1011 } else if (event->attr.exclude_user != eu ||
1012 event->attr.exclude_kernel != ek ||
1013 event->attr.exclude_hv != eh) {
1019 for (i = 0; i < n; ++i)
1020 if (cflags[i] & PPMU_LIMITED_PMC_OK)
1021 cflags[i] |= PPMU_LIMITED_PMC_REQD;
1026 static u64 check_and_compute_delta(u64 prev, u64 val)
1028 u64 delta = (val - prev) & 0xfffffffful;
1031 * POWER7 can roll back counter values, if the new value is smaller
1032 * than the previous value it will cause the delta and the counter to
1033 * have bogus values unless we rolled a counter over. If a coutner is
1034 * rolled back, it will be smaller, but within 256, which is the maximum
1035 * number of events to rollback at once. If we detect a rollback
1036 * return 0. This can lead to a small lack of precision in the
1039 if (prev > val && (prev - val) < 256)
1045 static void power_pmu_read(struct perf_event *event)
1047 s64 val, delta, prev;
1049 if (event->hw.state & PERF_HES_STOPPED)
1055 if (is_ebb_event(event)) {
1056 val = read_pmc(event->hw.idx);
1057 local64_set(&event->hw.prev_count, val);
1062 * Performance monitor interrupts come even when interrupts
1063 * are soft-disabled, as long as interrupts are hard-enabled.
1064 * Therefore we treat them like NMIs.
1067 prev = local64_read(&event->hw.prev_count);
1069 val = read_pmc(event->hw.idx);
1070 delta = check_and_compute_delta(prev, val);
1073 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
1075 local64_add(delta, &event->count);
1078 * A number of places program the PMC with (0x80000000 - period_left).
1079 * We never want period_left to be less than 1 because we will program
1080 * the PMC with a value >= 0x800000000 and an edge detected PMC will
1081 * roll around to 0 before taking an exception. We have seen this
1084 * To fix this, clamp the minimum value of period_left to 1.
1087 prev = local64_read(&event->hw.period_left);
1091 } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev);
1095 * On some machines, PMC5 and PMC6 can't be written, don't respect
1096 * the freeze conditions, and don't generate interrupts. This tells
1097 * us if `event' is using such a PMC.
1099 static int is_limited_pmc(int pmcnum)
1101 return (ppmu->flags & PPMU_LIMITED_PMC5_6)
1102 && (pmcnum == 5 || pmcnum == 6);
1105 static void freeze_limited_counters(struct cpu_hw_events *cpuhw,
1106 unsigned long pmc5, unsigned long pmc6)
1108 struct perf_event *event;
1109 u64 val, prev, delta;
1112 for (i = 0; i < cpuhw->n_limited; ++i) {
1113 event = cpuhw->limited_counter[i];
1116 val = (event->hw.idx == 5) ? pmc5 : pmc6;
1117 prev = local64_read(&event->hw.prev_count);
1119 delta = check_and_compute_delta(prev, val);
1121 local64_add(delta, &event->count);
1125 static void thaw_limited_counters(struct cpu_hw_events *cpuhw,
1126 unsigned long pmc5, unsigned long pmc6)
1128 struct perf_event *event;
1132 for (i = 0; i < cpuhw->n_limited; ++i) {
1133 event = cpuhw->limited_counter[i];
1134 event->hw.idx = cpuhw->limited_hwidx[i];
1135 val = (event->hw.idx == 5) ? pmc5 : pmc6;
1136 prev = local64_read(&event->hw.prev_count);
1137 if (check_and_compute_delta(prev, val))
1138 local64_set(&event->hw.prev_count, val);
1139 perf_event_update_userpage(event);
1144 * Since limited events don't respect the freeze conditions, we
1145 * have to read them immediately after freezing or unfreezing the
1146 * other events. We try to keep the values from the limited
1147 * events as consistent as possible by keeping the delay (in
1148 * cycles and instructions) between freezing/unfreezing and reading
1149 * the limited events as small and consistent as possible.
1150 * Therefore, if any limited events are in use, we read them
1151 * both, and always in the same order, to minimize variability,
1152 * and do it inside the same asm that writes MMCR0.
1154 static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0)
1156 unsigned long pmc5, pmc6;
1158 if (!cpuhw->n_limited) {
1159 mtspr(SPRN_MMCR0, mmcr0);
1164 * Write MMCR0, then read PMC5 and PMC6 immediately.
1165 * To ensure we don't get a performance monitor interrupt
1166 * between writing MMCR0 and freezing/thawing the limited
1167 * events, we first write MMCR0 with the event overflow
1168 * interrupt enable bits turned off.
1170 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
1171 : "=&r" (pmc5), "=&r" (pmc6)
1172 : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)),
1174 "i" (SPRN_PMC5), "i" (SPRN_PMC6));
1176 if (mmcr0 & MMCR0_FC)
1177 freeze_limited_counters(cpuhw, pmc5, pmc6);
1179 thaw_limited_counters(cpuhw, pmc5, pmc6);
1182 * Write the full MMCR0 including the event overflow interrupt
1183 * enable bits, if necessary.
1185 if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE))
1186 mtspr(SPRN_MMCR0, mmcr0);
1190 * Disable all events to prevent PMU interrupts and to allow
1191 * events to be added or removed.
1193 static void power_pmu_disable(struct pmu *pmu)
1195 struct cpu_hw_events *cpuhw;
1196 unsigned long flags, mmcr0, val;
1200 local_irq_save(flags);
1201 cpuhw = this_cpu_ptr(&cpu_hw_events);
1203 if (!cpuhw->disabled) {
1205 * Check if we ever enabled the PMU on this cpu.
1207 if (!cpuhw->pmcs_enabled) {
1209 cpuhw->pmcs_enabled = 1;
1213 * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56
1215 val = mmcr0 = mfspr(SPRN_MMCR0);
1217 val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO |
1221 * The barrier is to make sure the mtspr has been
1222 * executed and the PMU has frozen the events etc.
1225 write_mmcr0(cpuhw, val);
1230 * Disable instruction sampling if it was enabled
1232 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
1234 cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1239 cpuhw->disabled = 1;
1242 ebb_switch_out(mmcr0);
1246 * These are readable by userspace, may contain kernel
1247 * addresses and are not switched by context switch, so clear
1248 * them now to avoid leaking anything to userspace in general
1249 * including to another process.
1251 if (ppmu->flags & PPMU_ARCH_207S) {
1252 mtspr(SPRN_SDAR, 0);
1253 mtspr(SPRN_SIAR, 0);
1258 local_irq_restore(flags);
1262 * Re-enable all events if disable == 0.
1263 * If we were previously disabled and events were added, then
1264 * put the new config on the PMU.
1266 static void power_pmu_enable(struct pmu *pmu)
1268 struct perf_event *event;
1269 struct cpu_hw_events *cpuhw;
1270 unsigned long flags;
1272 unsigned long val, mmcr0;
1274 unsigned int hwc_index[MAX_HWEVENTS];
1281 local_irq_save(flags);
1283 cpuhw = this_cpu_ptr(&cpu_hw_events);
1284 if (!cpuhw->disabled)
1287 if (cpuhw->n_events == 0) {
1288 ppc_set_pmu_inuse(0);
1292 cpuhw->disabled = 0;
1295 * EBB requires an exclusive group and all events must have the EBB
1296 * flag set, or not set, so we can just check a single event. Also we
1297 * know we have at least one event.
1299 ebb = is_ebb_event(cpuhw->event[0]);
1302 * If we didn't change anything, or only removed events,
1303 * no need to recalculate MMCR* settings and reset the PMCs.
1304 * Just reenable the PMU with the current MMCR* settings
1305 * (possibly updated for removal of events).
1307 if (!cpuhw->n_added) {
1308 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1309 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1314 * Clear all MMCR settings and recompute them for the new set of events.
1316 memset(cpuhw->mmcr, 0, sizeof(cpuhw->mmcr));
1318 if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index,
1319 cpuhw->mmcr, cpuhw->event)) {
1320 /* shouldn't ever get here */
1321 printk(KERN_ERR "oops compute_mmcr failed\n");
1325 if (!(ppmu->flags & PPMU_ARCH_207S)) {
1327 * Add in MMCR0 freeze bits corresponding to the attr.exclude_*
1328 * bits for the first event. We have already checked that all
1329 * events have the same value for these bits as the first event.
1331 event = cpuhw->event[0];
1332 if (event->attr.exclude_user)
1333 cpuhw->mmcr[0] |= MMCR0_FCP;
1334 if (event->attr.exclude_kernel)
1335 cpuhw->mmcr[0] |= freeze_events_kernel;
1336 if (event->attr.exclude_hv)
1337 cpuhw->mmcr[0] |= MMCR0_FCHV;
1341 * Write the new configuration to MMCR* with the freeze
1342 * bit set and set the hardware events to their initial values.
1343 * Then unfreeze the events.
1345 ppc_set_pmu_inuse(1);
1346 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1347 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1348 mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
1350 if (ppmu->flags & PPMU_ARCH_207S)
1351 mtspr(SPRN_MMCR2, cpuhw->mmcr[3]);
1354 * Read off any pre-existing events that need to move
1357 for (i = 0; i < cpuhw->n_events; ++i) {
1358 event = cpuhw->event[i];
1359 if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) {
1360 power_pmu_read(event);
1361 write_pmc(event->hw.idx, 0);
1367 * Initialize the PMCs for all the new and moved events.
1369 cpuhw->n_limited = n_lim = 0;
1370 for (i = 0; i < cpuhw->n_events; ++i) {
1371 event = cpuhw->event[i];
1374 idx = hwc_index[i] + 1;
1375 if (is_limited_pmc(idx)) {
1376 cpuhw->limited_counter[n_lim] = event;
1377 cpuhw->limited_hwidx[n_lim] = idx;
1383 val = local64_read(&event->hw.prev_count);
1386 if (event->hw.sample_period) {
1387 left = local64_read(&event->hw.period_left);
1388 if (left < 0x80000000L)
1389 val = 0x80000000L - left;
1391 local64_set(&event->hw.prev_count, val);
1394 event->hw.idx = idx;
1395 if (event->hw.state & PERF_HES_STOPPED)
1397 write_pmc(idx, val);
1399 perf_event_update_userpage(event);
1401 cpuhw->n_limited = n_lim;
1402 cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
1405 pmao_restore_workaround(ebb);
1407 mmcr0 = ebb_switch_in(ebb, cpuhw);
1410 if (cpuhw->bhrb_users)
1411 ppmu->config_bhrb(cpuhw->bhrb_filter);
1413 write_mmcr0(cpuhw, mmcr0);
1416 * Enable instruction sampling if necessary
1418 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
1420 mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
1425 local_irq_restore(flags);
1428 static int collect_events(struct perf_event *group, int max_count,
1429 struct perf_event *ctrs[], u64 *events,
1430 unsigned int *flags)
1433 struct perf_event *event;
1435 if (group->pmu->task_ctx_nr == perf_hw_context) {
1439 flags[n] = group->hw.event_base;
1440 events[n++] = group->hw.config;
1442 for_each_sibling_event(event, group) {
1443 if (event->pmu->task_ctx_nr == perf_hw_context &&
1444 event->state != PERF_EVENT_STATE_OFF) {
1448 flags[n] = event->hw.event_base;
1449 events[n++] = event->hw.config;
1456 * Add an event to the PMU.
1457 * If all events are not already frozen, then we disable and
1458 * re-enable the PMU in order to get hw_perf_enable to do the
1459 * actual work of reconfiguring the PMU.
1461 static int power_pmu_add(struct perf_event *event, int ef_flags)
1463 struct cpu_hw_events *cpuhw;
1464 unsigned long flags;
1468 local_irq_save(flags);
1469 perf_pmu_disable(event->pmu);
1472 * Add the event to the list (if there is room)
1473 * and check whether the total set is still feasible.
1475 cpuhw = this_cpu_ptr(&cpu_hw_events);
1476 n0 = cpuhw->n_events;
1477 if (n0 >= ppmu->n_counter)
1479 cpuhw->event[n0] = event;
1480 cpuhw->events[n0] = event->hw.config;
1481 cpuhw->flags[n0] = event->hw.event_base;
1484 * This event may have been disabled/stopped in record_and_restart()
1485 * because we exceeded the ->event_limit. If re-starting the event,
1486 * clear the ->hw.state (STOPPED and UPTODATE flags), so the user
1487 * notification is re-enabled.
1489 if (!(ef_flags & PERF_EF_START))
1490 event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
1492 event->hw.state = 0;
1495 * If group events scheduling transaction was started,
1496 * skip the schedulability test here, it will be performed
1497 * at commit time(->commit_txn) as a whole
1499 if (cpuhw->txn_flags & PERF_PMU_TXN_ADD)
1502 if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1))
1504 if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1))
1506 event->hw.config = cpuhw->events[n0];
1509 ebb_event_add(event);
1516 if (has_branch_stack(event)) {
1517 power_pmu_bhrb_enable(event);
1518 cpuhw->bhrb_filter = ppmu->bhrb_filter_map(
1519 event->attr.branch_sample_type);
1522 perf_pmu_enable(event->pmu);
1523 local_irq_restore(flags);
1528 * Remove an event from the PMU.
1530 static void power_pmu_del(struct perf_event *event, int ef_flags)
1532 struct cpu_hw_events *cpuhw;
1534 unsigned long flags;
1536 local_irq_save(flags);
1537 perf_pmu_disable(event->pmu);
1539 power_pmu_read(event);
1541 cpuhw = this_cpu_ptr(&cpu_hw_events);
1542 for (i = 0; i < cpuhw->n_events; ++i) {
1543 if (event == cpuhw->event[i]) {
1544 while (++i < cpuhw->n_events) {
1545 cpuhw->event[i-1] = cpuhw->event[i];
1546 cpuhw->events[i-1] = cpuhw->events[i];
1547 cpuhw->flags[i-1] = cpuhw->flags[i];
1550 ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr);
1551 if (event->hw.idx) {
1552 write_pmc(event->hw.idx, 0);
1555 perf_event_update_userpage(event);
1559 for (i = 0; i < cpuhw->n_limited; ++i)
1560 if (event == cpuhw->limited_counter[i])
1562 if (i < cpuhw->n_limited) {
1563 while (++i < cpuhw->n_limited) {
1564 cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i];
1565 cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i];
1569 if (cpuhw->n_events == 0) {
1570 /* disable exceptions if no events are running */
1571 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
1574 if (has_branch_stack(event))
1575 power_pmu_bhrb_disable(event);
1577 perf_pmu_enable(event->pmu);
1578 local_irq_restore(flags);
1582 * POWER-PMU does not support disabling individual counters, hence
1583 * program their cycle counter to their max value and ignore the interrupts.
1586 static void power_pmu_start(struct perf_event *event, int ef_flags)
1588 unsigned long flags;
1592 if (!event->hw.idx || !event->hw.sample_period)
1595 if (!(event->hw.state & PERF_HES_STOPPED))
1598 if (ef_flags & PERF_EF_RELOAD)
1599 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1601 local_irq_save(flags);
1602 perf_pmu_disable(event->pmu);
1604 event->hw.state = 0;
1605 left = local64_read(&event->hw.period_left);
1608 if (left < 0x80000000L)
1609 val = 0x80000000L - left;
1611 write_pmc(event->hw.idx, val);
1613 perf_event_update_userpage(event);
1614 perf_pmu_enable(event->pmu);
1615 local_irq_restore(flags);
1618 static void power_pmu_stop(struct perf_event *event, int ef_flags)
1620 unsigned long flags;
1622 if (!event->hw.idx || !event->hw.sample_period)
1625 if (event->hw.state & PERF_HES_STOPPED)
1628 local_irq_save(flags);
1629 perf_pmu_disable(event->pmu);
1631 power_pmu_read(event);
1632 event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
1633 write_pmc(event->hw.idx, 0);
1635 perf_event_update_userpage(event);
1636 perf_pmu_enable(event->pmu);
1637 local_irq_restore(flags);
1641 * Start group events scheduling transaction
1642 * Set the flag to make pmu::enable() not perform the
1643 * schedulability test, it will be performed at commit time
1645 * We only support PERF_PMU_TXN_ADD transactions. Save the
1646 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1649 static void power_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1651 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1653 WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */
1655 cpuhw->txn_flags = txn_flags;
1656 if (txn_flags & ~PERF_PMU_TXN_ADD)
1659 perf_pmu_disable(pmu);
1660 cpuhw->n_txn_start = cpuhw->n_events;
1664 * Stop group events scheduling transaction
1665 * Clear the flag and pmu::enable() will perform the
1666 * schedulability test.
1668 static void power_pmu_cancel_txn(struct pmu *pmu)
1670 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1671 unsigned int txn_flags;
1673 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
1675 txn_flags = cpuhw->txn_flags;
1676 cpuhw->txn_flags = 0;
1677 if (txn_flags & ~PERF_PMU_TXN_ADD)
1680 perf_pmu_enable(pmu);
1684 * Commit group events scheduling transaction
1685 * Perform the group schedulability test as a whole
1686 * Return 0 if success
1688 static int power_pmu_commit_txn(struct pmu *pmu)
1690 struct cpu_hw_events *cpuhw;
1696 cpuhw = this_cpu_ptr(&cpu_hw_events);
1697 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
1699 if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) {
1700 cpuhw->txn_flags = 0;
1704 n = cpuhw->n_events;
1705 if (check_excludes(cpuhw->event, cpuhw->flags, 0, n))
1707 i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n);
1711 for (i = cpuhw->n_txn_start; i < n; ++i)
1712 cpuhw->event[i]->hw.config = cpuhw->events[i];
1714 cpuhw->txn_flags = 0;
1715 perf_pmu_enable(pmu);
1720 * Return 1 if we might be able to put event on a limited PMC,
1722 * An event can only go on a limited PMC if it counts something
1723 * that a limited PMC can count, doesn't require interrupts, and
1724 * doesn't exclude any processor mode.
1726 static int can_go_on_limited_pmc(struct perf_event *event, u64 ev,
1730 u64 alt[MAX_EVENT_ALTERNATIVES];
1732 if (event->attr.exclude_user
1733 || event->attr.exclude_kernel
1734 || event->attr.exclude_hv
1735 || event->attr.sample_period)
1738 if (ppmu->limited_pmc_event(ev))
1742 * The requested event_id isn't on a limited PMC already;
1743 * see if any alternative code goes on a limited PMC.
1745 if (!ppmu->get_alternatives)
1748 flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD;
1749 n = ppmu->get_alternatives(ev, flags, alt);
1755 * Find an alternative event_id that goes on a normal PMC, if possible,
1756 * and return the event_id code, or 0 if there is no such alternative.
1757 * (Note: event_id code 0 is "don't count" on all machines.)
1759 static u64 normal_pmc_alternative(u64 ev, unsigned long flags)
1761 u64 alt[MAX_EVENT_ALTERNATIVES];
1764 flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD);
1765 n = ppmu->get_alternatives(ev, flags, alt);
1771 /* Number of perf_events counting hardware events */
1772 static atomic_t num_events;
1773 /* Used to avoid races in calling reserve/release_pmc_hardware */
1774 static DEFINE_MUTEX(pmc_reserve_mutex);
1777 * Release the PMU if this is the last perf_event.
1779 static void hw_perf_event_destroy(struct perf_event *event)
1781 if (!atomic_add_unless(&num_events, -1, 1)) {
1782 mutex_lock(&pmc_reserve_mutex);
1783 if (atomic_dec_return(&num_events) == 0)
1784 release_pmc_hardware();
1785 mutex_unlock(&pmc_reserve_mutex);
1790 * Translate a generic cache event_id config to a raw event_id code.
1792 static int hw_perf_cache_event(u64 config, u64 *eventp)
1794 unsigned long type, op, result;
1797 if (!ppmu->cache_events)
1801 type = config & 0xff;
1802 op = (config >> 8) & 0xff;
1803 result = (config >> 16) & 0xff;
1805 if (type >= PERF_COUNT_HW_CACHE_MAX ||
1806 op >= PERF_COUNT_HW_CACHE_OP_MAX ||
1807 result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
1810 ev = (*ppmu->cache_events)[type][op][result];
1819 static bool is_event_blacklisted(u64 ev)
1823 for (i=0; i < ppmu->n_blacklist_ev; i++) {
1824 if (ppmu->blacklist_ev[i] == ev)
1831 static int power_pmu_event_init(struct perf_event *event)
1834 unsigned long flags;
1835 struct perf_event *ctrs[MAX_HWEVENTS];
1836 u64 events[MAX_HWEVENTS];
1837 unsigned int cflags[MAX_HWEVENTS];
1840 struct cpu_hw_events *cpuhw;
1846 if (has_branch_stack(event)) {
1847 /* PMU has BHRB enabled */
1848 if (!(ppmu->flags & PPMU_ARCH_207S))
1852 switch (event->attr.type) {
1853 case PERF_TYPE_HARDWARE:
1854 ev = event->attr.config;
1855 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
1858 if (ppmu->blacklist_ev && is_event_blacklisted(ev))
1860 ev = ppmu->generic_events[ev];
1862 case PERF_TYPE_HW_CACHE:
1863 err = hw_perf_cache_event(event->attr.config, &ev);
1867 if (ppmu->blacklist_ev && is_event_blacklisted(ev))
1871 ev = event->attr.config;
1873 if (ppmu->blacklist_ev && is_event_blacklisted(ev))
1880 event->hw.config_base = ev;
1884 * If we are not running on a hypervisor, force the
1885 * exclude_hv bit to 0 so that we don't care what
1886 * the user set it to.
1888 if (!firmware_has_feature(FW_FEATURE_LPAR))
1889 event->attr.exclude_hv = 0;
1892 * If this is a per-task event, then we can use
1893 * PM_RUN_* events interchangeably with their non RUN_*
1894 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
1895 * XXX we should check if the task is an idle task.
1898 if (event->attach_state & PERF_ATTACH_TASK)
1899 flags |= PPMU_ONLY_COUNT_RUN;
1902 * If this machine has limited events, check whether this
1903 * event_id could go on a limited event.
1905 if (ppmu->flags & PPMU_LIMITED_PMC5_6) {
1906 if (can_go_on_limited_pmc(event, ev, flags)) {
1907 flags |= PPMU_LIMITED_PMC_OK;
1908 } else if (ppmu->limited_pmc_event(ev)) {
1910 * The requested event_id is on a limited PMC,
1911 * but we can't use a limited PMC; see if any
1912 * alternative goes on a normal PMC.
1914 ev = normal_pmc_alternative(ev, flags);
1920 /* Extra checks for EBB */
1921 err = ebb_event_check(event);
1926 * If this is in a group, check if it can go on with all the
1927 * other hardware events in the group. We assume the event
1928 * hasn't been linked into its leader's sibling list at this point.
1931 if (event->group_leader != event) {
1932 n = collect_events(event->group_leader, ppmu->n_counter - 1,
1933 ctrs, events, cflags);
1940 if (check_excludes(ctrs, cflags, n, 1))
1943 cpuhw = &get_cpu_var(cpu_hw_events);
1944 err = power_check_constraints(cpuhw, events, cflags, n + 1);
1946 if (has_branch_stack(event)) {
1947 bhrb_filter = ppmu->bhrb_filter_map(
1948 event->attr.branch_sample_type);
1950 if (bhrb_filter == -1) {
1951 put_cpu_var(cpu_hw_events);
1954 cpuhw->bhrb_filter = bhrb_filter;
1957 put_cpu_var(cpu_hw_events);
1961 event->hw.config = events[n];
1962 event->hw.event_base = cflags[n];
1963 event->hw.last_period = event->hw.sample_period;
1964 local64_set(&event->hw.period_left, event->hw.last_period);
1967 * For EBB events we just context switch the PMC value, we don't do any
1968 * of the sample_period logic. We use hw.prev_count for this.
1970 if (is_ebb_event(event))
1971 local64_set(&event->hw.prev_count, 0);
1974 * See if we need to reserve the PMU.
1975 * If no events are currently in use, then we have to take a
1976 * mutex to ensure that we don't race with another task doing
1977 * reserve_pmc_hardware or release_pmc_hardware.
1980 if (!atomic_inc_not_zero(&num_events)) {
1981 mutex_lock(&pmc_reserve_mutex);
1982 if (atomic_read(&num_events) == 0 &&
1983 reserve_pmc_hardware(perf_event_interrupt))
1986 atomic_inc(&num_events);
1987 mutex_unlock(&pmc_reserve_mutex);
1989 event->destroy = hw_perf_event_destroy;
1994 static int power_pmu_event_idx(struct perf_event *event)
1996 return event->hw.idx;
1999 ssize_t power_events_sysfs_show(struct device *dev,
2000 struct device_attribute *attr, char *page)
2002 struct perf_pmu_events_attr *pmu_attr;
2004 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
2006 return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
2009 static struct pmu power_pmu = {
2010 .pmu_enable = power_pmu_enable,
2011 .pmu_disable = power_pmu_disable,
2012 .event_init = power_pmu_event_init,
2013 .add = power_pmu_add,
2014 .del = power_pmu_del,
2015 .start = power_pmu_start,
2016 .stop = power_pmu_stop,
2017 .read = power_pmu_read,
2018 .start_txn = power_pmu_start_txn,
2019 .cancel_txn = power_pmu_cancel_txn,
2020 .commit_txn = power_pmu_commit_txn,
2021 .event_idx = power_pmu_event_idx,
2022 .sched_task = power_pmu_sched_task,
2026 * A counter has overflowed; update its count and record
2027 * things if requested. Note that interrupts are hard-disabled
2028 * here so there is no possibility of being interrupted.
2030 static void record_and_restart(struct perf_event *event, unsigned long val,
2031 struct pt_regs *regs)
2033 u64 period = event->hw.sample_period;
2034 s64 prev, delta, left;
2037 if (event->hw.state & PERF_HES_STOPPED) {
2038 write_pmc(event->hw.idx, 0);
2042 /* we don't have to worry about interrupts here */
2043 prev = local64_read(&event->hw.prev_count);
2044 delta = check_and_compute_delta(prev, val);
2045 local64_add(delta, &event->count);
2048 * See if the total period for this event has expired,
2049 * and update for the next period.
2052 left = local64_read(&event->hw.period_left) - delta;
2060 record = siar_valid(regs);
2061 event->hw.last_period = event->hw.sample_period;
2063 if (left < 0x80000000LL)
2064 val = 0x80000000LL - left;
2067 write_pmc(event->hw.idx, val);
2068 local64_set(&event->hw.prev_count, val);
2069 local64_set(&event->hw.period_left, left);
2070 perf_event_update_userpage(event);
2073 * Finally record data if requested.
2076 struct perf_sample_data data;
2078 perf_sample_data_init(&data, ~0ULL, event->hw.last_period);
2080 if (event->attr.sample_type &
2081 (PERF_SAMPLE_ADDR | PERF_SAMPLE_PHYS_ADDR))
2082 perf_get_data_addr(event, regs, &data.addr);
2084 if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) {
2085 struct cpu_hw_events *cpuhw;
2086 cpuhw = this_cpu_ptr(&cpu_hw_events);
2087 power_pmu_bhrb_read(event, cpuhw);
2088 data.br_stack = &cpuhw->bhrb_stack;
2091 if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC &&
2092 ppmu->get_mem_data_src)
2093 ppmu->get_mem_data_src(&data.data_src, ppmu->flags, regs);
2095 if (event->attr.sample_type & PERF_SAMPLE_WEIGHT &&
2096 ppmu->get_mem_weight)
2097 ppmu->get_mem_weight(&data.weight);
2099 if (perf_event_overflow(event, &data, regs))
2100 power_pmu_stop(event, 0);
2105 * Called from generic code to get the misc flags (i.e. processor mode)
2108 unsigned long perf_misc_flags(struct pt_regs *regs)
2110 u32 flags = perf_get_misc_flags(regs);
2114 return user_mode(regs) ? PERF_RECORD_MISC_USER :
2115 PERF_RECORD_MISC_KERNEL;
2119 * Called from generic code to get the instruction pointer
2122 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2124 bool use_siar = regs_use_siar(regs);
2126 if (use_siar && siar_valid(regs))
2127 return mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
2129 return 0; // no valid instruction pointer
2134 static bool pmc_overflow_power7(unsigned long val)
2137 * Events on POWER7 can roll back if a speculative event doesn't
2138 * eventually complete. Unfortunately in some rare cases they will
2139 * raise a performance monitor exception. We need to catch this to
2140 * ensure we reset the PMC. In all cases the PMC will be 256 or less
2141 * cycles from overflow.
2143 * We only do this if the first pass fails to find any overflowing
2144 * PMCs because a user might set a period of less than 256 and we
2145 * don't want to mistakenly reset them.
2147 if ((0x80000000 - val) <= 256)
2153 static bool pmc_overflow(unsigned long val)
2162 * Performance monitor interrupt stuff
2164 static void __perf_event_interrupt(struct pt_regs *regs)
2167 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
2168 struct perf_event *event;
2169 unsigned long val[8];
2173 if (cpuhw->n_limited)
2174 freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5),
2177 perf_read_regs(regs);
2179 nmi = perf_intr_is_nmi(regs);
2185 /* Read all the PMCs since we'll need them a bunch of times */
2186 for (i = 0; i < ppmu->n_counter; ++i)
2187 val[i] = read_pmc(i + 1);
2189 /* Try to find what caused the IRQ */
2191 for (i = 0; i < ppmu->n_counter; ++i) {
2192 if (!pmc_overflow(val[i]))
2194 if (is_limited_pmc(i + 1))
2195 continue; /* these won't generate IRQs */
2197 * We've found one that's overflowed. For active
2198 * counters we need to log this. For inactive
2199 * counters, we need to reset it anyway
2203 for (j = 0; j < cpuhw->n_events; ++j) {
2204 event = cpuhw->event[j];
2205 if (event->hw.idx == (i + 1)) {
2207 record_and_restart(event, val[i], regs);
2212 /* reset non active counters that have overflowed */
2213 write_pmc(i + 1, 0);
2215 if (!found && pvr_version_is(PVR_POWER7)) {
2216 /* check active counters for special buggy p7 overflow */
2217 for (i = 0; i < cpuhw->n_events; ++i) {
2218 event = cpuhw->event[i];
2219 if (!event->hw.idx || is_limited_pmc(event->hw.idx))
2221 if (pmc_overflow_power7(val[event->hw.idx - 1])) {
2222 /* event has overflowed in a buggy way*/
2224 record_and_restart(event,
2225 val[event->hw.idx - 1],
2230 if (!found && !nmi && printk_ratelimit())
2231 printk(KERN_WARNING "Can't find PMC that caused IRQ\n");
2234 * Reset MMCR0 to its normal value. This will set PMXE and
2235 * clear FC (freeze counters) and PMAO (perf mon alert occurred)
2236 * and thus allow interrupts to occur again.
2237 * XXX might want to use MSR.PM to keep the events frozen until
2238 * we get back out of this interrupt.
2240 write_mmcr0(cpuhw, cpuhw->mmcr[0]);
2248 static void perf_event_interrupt(struct pt_regs *regs)
2250 u64 start_clock = sched_clock();
2252 __perf_event_interrupt(regs);
2253 perf_sample_event_took(sched_clock() - start_clock);
2256 static int power_pmu_prepare_cpu(unsigned int cpu)
2258 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
2261 memset(cpuhw, 0, sizeof(*cpuhw));
2262 cpuhw->mmcr[0] = MMCR0_FC;
2267 int register_power_pmu(struct power_pmu *pmu)
2270 return -EBUSY; /* something's already registered */
2273 pr_info("%s performance monitor hardware support registered\n",
2276 power_pmu.attr_groups = ppmu->attr_groups;
2280 * Use FCHV to ignore kernel events if MSR.HV is set.
2282 if (mfmsr() & MSR_HV)
2283 freeze_events_kernel = MMCR0_FCHV;
2284 #endif /* CONFIG_PPC64 */
2286 perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW);
2287 cpuhp_setup_state(CPUHP_PERF_POWER, "perf/powerpc:prepare",
2288 power_pmu_prepare_cpu, NULL);
2293 static int __init init_ppc64_pmu(void)
2295 /* run through all the pmu drivers one at a time */
2296 if (!init_power5_pmu())
2298 else if (!init_power5p_pmu())
2300 else if (!init_power6_pmu())
2302 else if (!init_power7_pmu())
2304 else if (!init_power8_pmu())
2306 else if (!init_power9_pmu())
2308 else if (!init_ppc970_pmu())
2311 return init_generic_compat_pmu();
2313 early_initcall(init_ppc64_pmu);