2 * MPC8610 HPCD board specific routines
4 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
5 * Recode: Jason Jin <jason.jin@freescale.com>
6 * York Sun <yorksun@freescale.com>
8 * Rewrite the interrupt routing. remove the 8259PIC support,
9 * All the integrated device in ULI use sideband interrupt.
11 * Copyright 2008 Freescale Semiconductor Inc.
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/interrupt.h>
23 #include <linux/kdev_t.h>
24 #include <linux/delay.h>
25 #include <linux/seq_file.h>
28 #include <asm/system.h>
30 #include <asm/machdep.h>
31 #include <asm/pci-bridge.h>
33 #include <mm/mmu_decl.h>
38 #include <linux/of_platform.h>
39 #include <sysdev/fsl_pci.h>
40 #include <sysdev/fsl_soc.h>
41 #include <sysdev/simple_gpio.h>
45 static struct device_node *pixis_node;
46 static unsigned char *pixis_bdcfg0, *pixis_arch;
49 static irqreturn_t mpc8610_sw9_irq(int irq, void *data)
51 pr_debug("%s: PIXIS' event (sw9/wakeup) IRQ handled\n", __func__);
55 static void __init mpc8610_suspend_init(void)
63 irq = irq_of_parse_and_map(pixis_node, 0);
65 pr_err("%s: can't map pixis event IRQ.\n", __func__);
69 ret = request_irq(irq, mpc8610_sw9_irq, 0, "sw9:wakeup", NULL);
71 pr_err("%s: can't request pixis event IRQ: %d\n",
73 irq_dispose_mapping(irq);
79 static inline void mpc8610_suspend_init(void) { }
80 #endif /* CONFIG_SUSPEND */
82 static struct of_device_id __initdata mpc8610_ids[] = {
83 { .compatible = "fsl,mpc8610-immr", },
84 { .compatible = "fsl,mpc8610-guts", },
85 { .compatible = "simple-bus", },
86 /* So that the DMA channel nodes can be probed individually: */
87 { .compatible = "fsl,eloplus-dma", },
91 static int __init mpc8610_declare_of_platform_devices(void)
93 /* Firstly, register PIXIS GPIOs. */
94 simple_gpiochip_init("fsl,fpga-pixis-gpio-bank");
96 /* Enable wakeup on PIXIS' event IRQ. */
97 mpc8610_suspend_init();
99 /* Without this call, the SSI device driver won't get probed. */
100 of_platform_bus_probe(NULL, mpc8610_ids, NULL);
104 machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
106 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
109 * DIU Area Descriptor
111 * The MPC8610 reference manual shows the bits of the AD register in
112 * little-endian order, which causes the BLUE_C field to be split into two
113 * parts. To simplify the definition of the MAKE_AD() macro, we define the
114 * fields in big-endian order and byte-swap the result.
116 * So even though the registers don't look like they're in the
117 * same bit positions as they are on the P1022, the same value is written to
118 * the AD register on the MPC8610 and on the P1022.
120 #define AD_BYTE_F 0x10000000
121 #define AD_ALPHA_C_MASK 0x0E000000
122 #define AD_ALPHA_C_SHIFT 25
123 #define AD_BLUE_C_MASK 0x01800000
124 #define AD_BLUE_C_SHIFT 23
125 #define AD_GREEN_C_MASK 0x00600000
126 #define AD_GREEN_C_SHIFT 21
127 #define AD_RED_C_MASK 0x00180000
128 #define AD_RED_C_SHIFT 19
129 #define AD_PALETTE 0x00040000
130 #define AD_PIXEL_S_MASK 0x00030000
131 #define AD_PIXEL_S_SHIFT 16
132 #define AD_COMP_3_MASK 0x0000F000
133 #define AD_COMP_3_SHIFT 12
134 #define AD_COMP_2_MASK 0x00000F00
135 #define AD_COMP_2_SHIFT 8
136 #define AD_COMP_1_MASK 0x000000F0
137 #define AD_COMP_1_SHIFT 4
138 #define AD_COMP_0_MASK 0x0000000F
139 #define AD_COMP_0_SHIFT 0
141 #define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
142 cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
143 (blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
144 (red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
145 (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
146 (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
148 u32 mpc8610hpcd_get_pixel_format(enum fsl_diu_monitor_port port,
149 unsigned int bits_per_pixel)
151 static const u32 pixelformat[][3] = {
153 MAKE_AD(3, 0, 2, 1, 3, 8, 8, 8, 8),
154 MAKE_AD(4, 2, 0, 1, 2, 8, 8, 8, 0),
155 MAKE_AD(4, 0, 2, 1, 1, 5, 6, 5, 0)
158 MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8),
159 MAKE_AD(4, 0, 2, 1, 2, 8, 8, 8, 0),
160 MAKE_AD(4, 2, 0, 1, 1, 5, 6, 5, 0)
163 unsigned int arch_monitor;
165 /* The DVI port is mis-wired on revision 1 of this board. */
167 ((*pixis_arch == 0x01) && (port == FSL_DIU_PORT_DVI)) ? 0 : 1;
169 switch (bits_per_pixel) {
171 return pixelformat[arch_monitor][0];
173 return pixelformat[arch_monitor][1];
175 return pixelformat[arch_monitor][2];
177 pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
182 void mpc8610hpcd_set_gamma_table(enum fsl_diu_monitor_port port,
183 char *gamma_table_base)
186 if (port == FSL_DIU_PORT_DLVDS) {
187 for (i = 0; i < 256*3; i++)
188 gamma_table_base[i] = (gamma_table_base[i] << 2) |
189 ((gamma_table_base[i] >> 6) & 0x03);
193 #define PX_BRDCFG0_DVISEL (1 << 3)
194 #define PX_BRDCFG0_DLINK (1 << 4)
195 #define PX_BRDCFG0_DIU_MASK (PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK)
197 void mpc8610hpcd_set_monitor_port(enum fsl_diu_monitor_port port)
200 case FSL_DIU_PORT_DVI:
201 clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
202 PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK);
204 case FSL_DIU_PORT_LVDS:
205 clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
208 case FSL_DIU_PORT_DLVDS:
209 clrbits8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK);
214 void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
216 u32 __iomem *clkdvdr;
218 /* variables for pixel clock calcs */
219 ulong bestval, bestfreq, speed_ccb, minpixclock, maxpixclock;
224 clkdvdr = ioremap(get_immrbase() + 0xe0800, sizeof(u32));
226 printk(KERN_ERR "Err: can't map clock divider register!\n");
230 /* Pixel Clock configuration */
231 speed_ccb = fsl_get_sys_freq();
233 /* Calculate the pixel clock with the smallest error */
234 /* calculate the following in steps to avoid overflow */
235 pr_debug("DIU pixclock in ps - %d\n", pixclock);
236 temp = 1000000000/pixclock;
239 pr_debug("DIU pixclock freq - %u\n", pixclock);
241 temp = pixclock * 5 / 100;
242 pr_debug("deviation = %d\n", temp);
243 minpixclock = pixclock - temp;
244 maxpixclock = pixclock + temp;
245 pr_debug("DIU minpixclock - %lu\n", minpixclock);
246 pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
247 pixval = speed_ccb/pixclock;
248 pr_debug("DIU pixval = %lu\n", pixval);
252 pr_debug("DIU bestval = %lu\n", bestval);
255 for (i = -1; i <= 1; i++) {
256 temp = speed_ccb / ((pixval+i) + 1);
257 pr_debug("DIU test pixval i= %d, pixval=%lu, temp freq. = %u\n",
259 if ((temp < minpixclock) || (temp > maxpixclock))
260 pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
261 minpixclock, maxpixclock);
262 else if (abs(temp - pixclock) < err) {
263 pr_debug("Entered the else if block %d\n", i);
264 err = abs(temp - pixclock);
270 pr_debug("DIU chose = %lx\n", bestval);
271 pr_debug("DIU error = %ld\n NomPixClk ", err);
272 pr_debug("DIU: Best Freq = %lx\n", bestfreq);
273 /* Modify PXCLK in GUTS CLKDVDR */
274 pr_debug("DIU: Current value of CLKDVDR = 0x%08x\n", (*clkdvdr));
275 temp = (*clkdvdr) & 0x2000FFFF;
276 *clkdvdr = temp; /* turn off clock */
277 *clkdvdr = temp | 0x80000000 | (((bestval) & 0x1F) << 16);
278 pr_debug("DIU: Modified value of CLKDVDR = 0x%08x\n", (*clkdvdr));
282 enum fsl_diu_monitor_port
283 mpc8610hpcd_valid_monitor_port(enum fsl_diu_monitor_port port)
290 static void __init mpc86xx_hpcd_setup_arch(void)
293 struct device_node *np;
294 unsigned char *pixis;
297 ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
300 for_each_node_by_type(np, "pci") {
301 if (of_device_is_compatible(np, "fsl,mpc8610-pci")
302 || of_device_is_compatible(np, "fsl,mpc8641-pcie")) {
303 struct resource rsrc;
304 of_address_to_resource(np, 0, &rsrc);
305 if ((rsrc.start & 0xfffff) == 0xa000)
306 fsl_add_bridge(np, 1);
308 fsl_add_bridge(np, 0);
312 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
313 diu_ops.get_pixel_format = mpc8610hpcd_get_pixel_format;
314 diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table;
315 diu_ops.set_monitor_port = mpc8610hpcd_set_monitor_port;
316 diu_ops.set_pixel_clock = mpc8610hpcd_set_pixel_clock;
317 diu_ops.valid_monitor_port = mpc8610hpcd_valid_monitor_port;
320 pixis_node = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
322 of_address_to_resource(pixis_node, 0, &r);
323 of_node_put(pixis_node);
324 pixis = ioremap(r.start, 32);
326 printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
329 pixis_bdcfg0 = pixis + 8;
330 pixis_arch = pixis + 1;
332 printk(KERN_ERR "Err: "
333 "can't find device node 'fsl,fpga-pixis'\n");
335 printk("MPC86xx HPCD board from Freescale Semiconductor\n");
339 * Called very early, device-tree isn't unflattened
341 static int __init mpc86xx_hpcd_probe(void)
343 unsigned long root = of_get_flat_dt_root();
345 if (of_flat_dt_is_compatible(root, "fsl,MPC8610HPCD"))
346 return 1; /* Looks good */
351 static long __init mpc86xx_time_init(void)
355 /* Set the time base to zero */
359 temp = mfspr(SPRN_HID0);
361 mtspr(SPRN_HID0, temp);
362 asm volatile("isync");
367 define_machine(mpc86xx_hpcd) {
368 .name = "MPC86xx HPCD",
369 .probe = mpc86xx_hpcd_probe,
370 .setup_arch = mpc86xx_hpcd_setup_arch,
371 .init_IRQ = mpc86xx_init_irq,
372 .get_irq = mpic_get_irq,
373 .restart = fsl_rstcr_restart,
374 .time_init = mpc86xx_time_init,
375 .calibrate_decr = generic_calibrate_decr,
376 .progress = udbg_progress,
377 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,